JPH10173178A - Manufacture of vertical field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the resistance of a FET when operating it, by implanting ions into the whole or one portion of a region to be a recessed portion which is present on a semiconductor substrate with successively laminated oxide and nitride films thereon, and by oxidizing the region through using the nitride film as an anti-oxidation film, and further, by so forming the recessed portion as for the oxidized film to bite into the semiconductor substrate. SOLUTION: Growing an oxide film 11 on the surface of an epitaxial layer 2 formed on a semiconductor substrate 1 of a FET, a nitride film 12 is laminated thereon. Patterning the nitride film 12, a resist 13 is applied to the remaining nitride film 12 after removing the unnecessary nitride film 12. Further, an ion- implantation is performed using the resist 13 as a mask to form a high- concentration layer 21 in place of the semiconductor substrate 1. Then, after the removal of the resist 13, a LOCOS oxide film 14 is formed in the place. At this time, making one portion of the LOCOS oxide film 14 bite into the epitaxial layer 2 via the high-concentration layer 21, a deep recessed portion (C) is formed. Thereby, the resistance of the FET when operating it can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a vertical field effect transistor.

[0002]

2. Description of the Related Art A conventional vertical field effect transistor is shown in FIG.
As shown in the figure, the impurity concentration is 10 ²⁰ cm ^-3 and the thickness is 1
A semiconductor substrate in which an n ⁻ -type epitaxial layer 2 having an impurity concentration of about 10 ¹⁶ cm ⁻³ and a thickness of about 7 μm is grown and formed on an n ⁺ -type silicon substrate 1 of 100 to 300 μm, and about 12 μm on the semiconductor substrate In which a uniset cell was formed.

The structure of a unit cell in the conventional vertical field effect transistor shown in FIG. 9 will be described. A U-groove is formed using a LOCOS oxide film on a main surface of a semiconductor substrate on which a unit cell is formed. Using this oxide film as a mask, a P-type base layer 3 having a junction depth of about 3 μm and an n ⁺ -type source layer 4 having a junction depth of about 1 μm are formed by self-aligned double diffusion. A channel is set on the side wall of the U groove by the n ⁺ -type source layer 4 and the n ⁺ -type source layer 4.

After the double diffusion, the LOCOS oxide film is removed, a gate oxide film having a thickness of about 60 mm is formed on the inner wall of the U-groove, and further, on the semiconductor substrate including the U-groove,
Polysilicon with a thickness of about 400mm (gate electrode)
6. Interlayer insulating film made of BPSG having a thickness of about 1 μm
And a P ⁺ -type base contact having a junction depth of about 0.5 μm is formed on the center surface of the P-type base layer 3. The electrode 8 formed on the interlayer insulating film 7 and the n ⁺ -type source The layer 4 and the P ⁺ type base layer 3 were in ohmic contact via the contact holes. On the back surface of the semiconductor substrate, a drain electrode (not shown) was formed so as to make ohmic contact.

Next, a method of manufacturing the conventional vertical field effect transistor shown in FIG. 9 will be described.

After a field oxide film of about 60 mm is formed on the main surface of the unit cell, a P-type diffusion layer is formed at the center of the cell portion, and a silicon nitride film is formed on the main surface by a thickness of about 200 nm.
0 nm is deposited, and the silicon nitride film is patterned so as to be perpendicular and parallel to the <011> direction to form a lattice-shaped opening pattern.

Next, the field oxide film is etched using the silicon nitride film as a mask, and then isotropically chemically dry-etched to form a concave portion serving as a U groove.

Next, using the silicon nitride film as a mask, U
The portion of the concave portion that becomes the groove is thermally oxidized. This is LOCO
S oxidation, and the oxide film generated by LOCOS oxidation has n
^The U-groove is formed by penetrating into the-type epitaxial layer 2, and the shape of the U-groove is determined. At this time, the bent portion formed in the chemical dry etching step (see FIG. 6B)
Remains on the side of the U-groove. At this time, the surface orientation of the channel forming portion on the side surface of the U groove is a surface close to (111),
The condition of chemical dry etching and the condition of LOCOS oxidation are selected.

Next, boron ions are implanted in a self-aligned manner using the LOCOS oxide film as a mask, thermally diffused to a junction depth of about 3 μm to form a P-type base region, and then a resist and a LOCOS oxide film are formed by lithography. Phosphorus ion implantation as a mask, junction depth 0.5-1.0μ
m is diffused to form an n ⁺ -type source layer 4.

The junction depth obtained by the thermal diffusion is set to be deeper than the bent portion B remaining on the side surface of the U groove until after the selective oxidation formed at the time of the etching. Next, L
The gate electrode 6 is formed by etching the OCOS oxide film and performing gate oxidation with a thickness of about 60 nm, depositing polysilicon with a thickness of about 400 nm, and patterning.

Next, a P ⁺ base contact is formed using the patterned resist as a mask, an interlayer insulating film 7 is grown, a contact is opened, and a source electrode made of aluminum is formed. Has a T
A drain electrode made of i / Ni / Au is formed.

In the vertical field-effect transistor shown in FIG. 9, since the source layer is formed so that the channel is formed at a position deeper than the bent portion B, the flow of electrons may be disturbed at the bent portion B. Is prevented, which reduces the resistance during operation.

FIG. 10 shows a vertical field effect transistor using a U-groove without using LOCOS oxidation. The vertical field-effect transistor shown in FIG. 10 has an impurity concentration of 1 to 3 × 10 ¹⁶ cm ⁻³ and a thickness of 5 μm on an N ⁺ type semiconductor substrate 1 having an impurity concentration of about 10 ²⁰ cm ^−3.
A semiconductor substrate on which an n ^- type epitaxial layer 2 of about m is grown is used. In this semiconductor substrate, a P base region 3 having a depth of about 2.5 μm is formed by boron ion implantation and annealing, and then a trench is formed by RIE. Polysilicon 6 is grown after a gate oxide film 5 of about 2000.degree. Is formed on the inner wall of the trench, etched back after phosphorus diffusion, an n.sup. ⁺ Source region 4 is formed, and an interlayer insulating film 7 and an electrode 8 are formed. Formed to complete as a vertical field effect transistor.

[0014]

However, in the conventional vertical field effect transistor shown in FIGS. 9 and 10, the first problem is that the mobility is reduced, and as a result, the resistance during operation is reduced. There was a problem of becoming larger.

The reason for this is that defects are introduced into the silicon substrate by using dry etching at the time of forming the grooves. In the case where LOCOS oxidation is used, there is a possibility that the defects can be removed. This is because there are restrictions on the thickness and the like.

Further, as a second problem, it is necessary to form the source region deeply, and as a result, there is a problem that the parasitic capacitance becomes large.

The reason is that it is necessary to form the source region deeper than the bent portion existing on the side surface of the U groove.

An object of the present invention is to provide a method of manufacturing a vertical field effect transistor having a low parasitic capacitance while realizing a reduction in resistance (on-resistance) during operation in a vertical field effect transistor having a U groove. It is in.

[0019]

In order to achieve the above object, a method of manufacturing a vertical field effect transistor according to the present invention comprises a vertical electric field transistor having a film forming step, an ion implantation step, and a recess forming step. A method of manufacturing an effect transistor, comprising: a vertical field-effect transistor having a base region of a second conductivity type in a semiconductor substrate of a first conductivity type, and having a source region of the first conductivity type in the base region. A recess is formed so as to straddle the base region and the source region of the adjacent cell,
A channel is formed in the recess, an electrode is applied on an insulating film covering this region so as to overlap, and the electrode is connected to a part of the base region and a part of the source region. The film forming step, the ion implantation step, and the concave part forming step are for forming a concave part of the cell part. The film forming step includes sequentially forming an oxide film and a nitride film on the surface of the semiconductor substrate. The ion implantation step is
This is a process of implanting ions into all or a part of a region to be a concave portion on the semiconductor substrate. In the concave portion forming step, the nitride film is used as an antioxidant film, oxidation is performed, and the oxide film is etched on the semiconductor substrate. This is a process for forming the recessed portion.

[0020]

By controlling the impurity concentration by ion-implanting a part of the semiconductor substrate, the shape of the subsequent LOCOS oxidation (the shape of the concave portion) is controlled, and the resistance of the current path is also controlled.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) A method for manufacturing a vertical field effect transistor according to the present invention shown in FIG. 1 has, as a basic configuration, a vertical field effect transistor having a film forming step, an ion implantation step, and a concave part forming step. This is a method of manufacturing an effect transistor, wherein the vertical field effect transistor has a base region 3 of a second conductivity type in semiconductor substrates 1 and 2 of a first conductivity type and a source region of a first conductivity type in the base region 3. An insulating film 7 having a region 4 is formed so as to extend over the base region 3 and the source region 15 of the adjacent cell, a channel is formed in the recess C, and this region is covered so as to overlap. An electrode 8 is attached thereon, and the electrode 8 is connected to a part of the base region 15 and a part of the source region 4. The film forming step, the ion implantation step, and the concave part forming step are for forming a concave part of the cell part. Next, an ion implantation step of implanting ions into all or a part of the region to be the recess C on the semiconductor substrates 1 and 2 is performed, and further, the nitride film is used as an antioxidant film, and oxidation is performed. The step of forming a concave portion for forming the concave portion by etching an oxide film into the semiconductor substrate is performed.

In the method of manufacturing a vertical field-effect transistor according to the first embodiment of the present invention, a semiconductor substrate having an N ⁻ type epitaxial layer 2 formed on an N ⁺ type semiconductor substrate 1 is used, and a semiconductor substrate is formed on a main surface of the semiconductor substrate. A unit cell of about 10 to 10 μm is formed.

Further, in the first embodiment of the present invention, in order to form a U-groove on a semiconductor substrate, an oxide film and a nitride film are formed on the main surface of the semiconductor substrate by lamination, and all the regions to be U-grooves are formed.
Alternatively, ion implantation is performed on a part of the semiconductor substrate, and the LOCOS oxide film is cut into the main surface of the semiconductor substrate by the effect of accelerated oxidation by LOCOS oxidation to form a recess C, and the recess C is used as a U groove. .

Next, the P-type base layer 3 and the N ⁺ -type source layer 4 are formed by self-aligned double diffusion using the oxide film as a mask.
Is formed, and a channel is set on the side wall of the U groove C.

After the double diffusion, the LOCOS oxide film is removed,
A gate oxide film 5 is formed, and a gate electrode made of polysilicon 6 is formed.

Thereafter, an insulating film (BPSG) 7 is formed,
A region of the insulating film 7 corresponding to a part of the N ⁺ source region 4 and a part of the P-type base region 15 is opened, and an electrode 8 made of aluminum or the like is deposited as a source electrode. A drain electrode is formed. Here, by ion-implanting all or a part of the region to be the concave portion C, a unit cell (device) can be formed in a deeper and defect-free Si layer than usual by accelerated oxidation. In addition, it becomes possible to reduce the resistance during the operation of the transistor and to contribute to the reduction of the capacity.

In a normal vertical field-effect transistor, the on-resistance (resistance during operation) is equal to N as shown in FIG.
⁺ Source region 4, channel 10, base-base (junction FET resistance), N ^- epitaxial layer 2,
It is represented by the sum of the resistance values of the N ⁺ semiconductor substrate 1. When the U groove C is formed, the resistance between the base and the base is basically eliminated, and the on-resistance can be reduced.

Focusing on the channel of the vertical field-effect transistor having the U-shaped groove shown in FIG. 2B (the present invention), it is known that the channel resistance is generally represented by the following equation. Rch = (L / W) · μC 6X (V G -V T) here, L; channel length, W; channel width, mu; mobility, C _6X; volume, V _G; gate voltage, V _T; Gate The respective threshold voltages are shown.

If a bent portion B exists in the channel portion as shown in FIG. 6B or a defect due to dry etching remains in the semiconductor substrate, the mobility due to carrier scattering on the surface is increased. When the value of μ remarkably decreases, Rch increases, and as a result, the on-resistance increases.

According to the present invention, the ion-implanted region is subjected to accelerated oxidation, so that there is no bent portion on the inner wall of the U groove C as shown in FIG. As shown in FIG. 6A, the U-shaped groove C can be formed deeply, and the junction FET resistance can be eliminated. Furthermore, the layer damaged by ion implantation is LOCOS
All are oxidized at the time of oxidation, and there is no defect on the surface of the semiconductor substrate, and the epitaxial resistance can be reduced, so that a low on-resistance can be achieved.

Since no bent portion is formed, the scattering layer can be made shallow, especially the N ⁺ source region can be made shallow, and the parasitic capacitance can be reduced.

(Embodiment 1) Next, Embodiment 1 of the present invention will be described with reference to the drawings. As is about 2 × 10 ¹⁹ cm
P is about 2 × 10 ¹⁶ cm ^{−3 in the -3} doped semiconductor substrate 1.
A semiconductor substrate on which a doped N ^- epitaxial layer 2 is grown by about 5 μm is used.

First, as shown in FIG.
Oxide film 11 is grown on N ⁻ epitaxial layer 2,
Next, a nitride film 12 of about 1000 ° is laminated on the oxide film 11, the nitride film 12 is patterned by lithography, and unnecessary nitride films are removed by dry etching. Applying, As or P is ion-implanted at 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² using the resist 13 as a mask (self-alignment),
The high concentration layer 21 is formed on a part of the semiconductor substrate.

Next, as shown in FIG.
3 after removal of 0.5 at a temperature of 1100 ° C. or higher.
A LOCOS oxide film 14 of about 1.0 μm is formed. At this time, in the region where the ion implantation is performed as compared with the region where the ion implantation is not performed in the semiconductor substrate, the LOCOS oxide film 14 is formed due to the effect of the accelerated oxidation by the LOCOS oxidation.
Grows vertically, and a part of the LOCOS oxide film 14
A deep recess C is formed by digging into N ⁻ epitaxial layer 2 through high concentration layer 21. Since the oxide film is completely filled in the ion-implanted region, no damage remains in the semiconductor substrate.

Next, as shown in FIG. 4A, the P base region 3 is formed so as to have a diffusion depth of about 1.2 μm by using the LOCOS oxide film 14 in a self-aligned manner, After forming the P ⁺ base region 15 by utilizing the above, the N ⁺ source region 4 is set to a depth of 0.4 μm or less. In the present invention, the LOCOS oxide film 14 grows in a wedge shape downward, and the concave portion C formed by the LOCOS oxide film 14 is formed.
The side wall of the (U groove) is shaped into a tapered shape, and the concave portion C (U
Since the side wall of the groove has no bent portion, the N ⁺ layer source region 4
Can be formed shallowly.

Next, as shown in FIG.
After the oxide film 14 has been completely removed by wet etching, a gate oxide film 5 of about 500 ° is formed on the inner wall of the U groove C, and then polysilicon 5000 of about 5000 ° is deposited on the gate oxide film 5. Then, phosphorus is diffused to reduce the gate resistance, and the polysilicon 6 and the gate oxide film 5 are patterned by lithography.

Next, as shown in FIG.
After forming a G film (insulating film) 7 on the polysilicon 6,
^{The +} base region (part of the P base region 3) 15 and the N ⁺ source region 4 are opened at the same contact portion, and an electrode 8 of aluminum or the like is deposited by about 4 μm by sputtering to form a source electrode. An Au / Ni / Ag-based metal is deposited on the back surface of the substrate 1 to form a drain electrode 9.

According to the present embodiment, as shown in FIG. 6A, R
Since the increase of on is prevented and the high concentration layer is part of the epitaxial layer, the resistance in this region is reduced, and as a result, the on-resistance can be reduced by about 20%.

Since the bent portion B does not exist in the U groove C as shown in FIG. 6B, the diffusion depth of the N ⁺ source region can be reduced, so that the polysilicon forming the gate electrode and N ⁺ The area of the overlapping portion with the source region can be reduced, and the capacity can be reduced by about 30%.

(Embodiment 2) Next, Embodiment 2 of the present invention.
Will be described with reference to FIGS. 7 and 8. In the second embodiment of the present invention, a semiconductor substrate having a P ⁻ epitaxial layer 17 on a P ⁺ type semiconductor substrate 16 is used, and a unit cell of about 10 μm is formed on a main surface of the semiconductor substrate.

As shown in FIG. 7A, first, about 500 °
Oxide film 11 is grown on the P ⁻ epitaxial layer 17, then a nitride film 12 of about 1000 ° is formed on the oxide film 11, and after being patterned by lithography, the unnecessary nitride film 12 is removed by dry etching. Then, As or P is ion-implanted into the semiconductor substrate using the oxide film 11 as a mask to form the low concentration layer 22.

Next, as shown in FIG. 7B, the nitride film 12 is again patterned widely from the opening of the oxide film 11 and unnecessary nitride film 12 is etched, and then LOCOS oxidation at 1100 ° C. or more is performed. LOCOS oxide film 14 is grown at a high speed. The point that the U groove C is formed by increasing the growth rate of the LOCOS film 14 is the same as in the first embodiment.

In the above process, the lower oxide film 1 is wet-etched with hydrofluoric acid or the like regardless of the lithography technique.
1 may be side-etched.

Next, as shown in FIG. 8A, an N base region 20, an N ⁺ base region 18, and a P ⁺ source region 19 are sequentially formed.

Next, as shown in FIG.
After the oxide film 14 is wet-etched, a gate oxide film 5 of about 500 ° is formed, and then a polysilicon 6 of about 5000 ° is deposited. Then, the polysilicon 6 is p-typed to reduce the gate resistance, and is patterned by lithography. I do. Subsequent steps are the same as in the first embodiment.

Embodiment 2 of the present invention shown in FIGS. 7 and 8
According to the first embodiment, a high concentration layer is not formed in a part of the epitaxial layer as compared with the first embodiment, but the other effects are the same as those of the first embodiment.

Further, according to the second embodiment of the present invention, since the P ⁻ layer is formed in a part immediately below the gate electrode (a part of the lower part of the U-shaped groove C), the capacity can be further reduced. In addition, since the low-concentration layer does not directly affect the current path, there is an advantage that an increase in on-resistance can be eliminated.

[0049]

As described above, according to the present invention, the on-resistance of the vertical field effect transistor can be reduced. The reason is that there is no bent part in the concave part (U groove) of the cell,
Moreover, this is because damage to the semiconductor substrate and the like due to dry etching can be prevented, and a high concentration layer exists in a part of the epitaxial layer.

Further, the parasitic capacitance of the vertical field effect transistor can be reduced. The reason is the concave part of the cell (U groove)
This is because there is no bent portion and the diffusion layer can be formed shallowly, and furthermore, the concentration of a part of the epitaxial layer other than the current path is reduced.

[Brief description of the drawings]

FIG. 1A is a plan view showing a vertical field effect transistor according to a first embodiment of the present invention, and FIG.
It is a sectional view taken on line -A '.

2A is a cross-sectional view illustrating an operation of a vertical field-effect transistor according to a conventional example, and FIG. 2B is a cross-sectional view illustrating an operation of the vertical field-effect transistor according to the first embodiment of the present invention. is there.

FIG. 3 is a sectional view illustrating a method of manufacturing the vertical field-effect transistor according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing the vertical field-effect transistor according to the first embodiment of the present invention in the order of steps.

FIG. 5 is a sectional view illustrating a method of manufacturing the vertical field-effect transistor according to the first embodiment of the present invention in the order of steps.

FIG. 6A is a cross-sectional view illustrating characteristics of a vertical field-effect transistor according to the first embodiment of the present invention, and FIG. 6B is a cross-sectional view illustrating characteristics of a vertical field-effect transistor according to a conventional example. is there.

FIG. 7 is a cross-sectional view illustrating a method of manufacturing the vertical field-effect transistor according to Embodiment 2 of the present invention in the order of steps.

FIG. 8 is a cross-sectional view illustrating a method of manufacturing the vertical field-effect transistor according to Embodiment 2 of the present invention in the order of steps.

FIG. 9 is a cross-sectional view of a vertical field-effect transistor according to a conventional example.

FIG. 10 is a cross-sectional view of a vertical field-effect transistor according to a conventional example.

[Explanation of symbols]

1 N ⁺ -type semiconductor substrate 2 N ^- -type epitaxial layer 3 P base region 4 N ⁺ -type source region 5 a gate oxide film 6 of polysilicon (gate electrode) 7 BPSG (insulating film) 8 electrode 9 drain electrode 10 channel 11 oxide film 12 Nitride film 13 resist 14 LOCOS oxide film 15 P ⁺ base region 16 P ⁺ type semiconductor substrate 17 P ⁻ type epitaxial layer 18 N ⁺ base layer 19 P ⁺ source layer 20 N base layer 21 high concentration layer 22 low concentration layer

Claims (1)

[Claims] 1. A method of manufacturing a vertical field effect transistor having a film forming step, an ion implantation step, and a recess forming step, wherein the vertical field effect transistor is provided in a semiconductor substrate of a first conductivity type. A base region of the second conductivity type, a source region of the first conductivity type in the base region, and a recess formed over the base region and the source region of an adjacent cell; A channel is formed, an electrode is deposited on an insulating film covering the region so as to overlap the region, and the electrode is connected to a part of the base region and a part of the source region. The forming step, the ion implantation step, and the concave part forming step are for forming a concave part in the cell part. The film forming step is a processing for sequentially forming an oxide film and a nitride film on the surface of the semiconductor substrate. The ion implantation process is a semiconductor This is a process of implanting ions into all or a part of a region to be a concave portion on the plate. In the concave portion forming step, the nitride film is used as an antioxidant film, oxidation is performed, and the oxide film is etched into the semiconductor substrate. A method of manufacturing a vertical field-effect transistor, wherein the method comprises forming the recess.