JPH10173152A - Manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for improving the production yield of a semiconductor integrated circuit device having a DRAM. SOLUTION: Above memory cell selecting MISFETs, a BPSG film is formed to planarize stepped parts caused by gate electrodes FG. Above this BPSG film 12 a little stressed silicon nitride film of about 25nm thick is formed by the thermal CVD method at 770-800 deg.C to thereby suppress the voids from growing in the BPSG film 12 and lessen the warp of a semiconductor wafer, thus suppressing the poor vacuum chucking of the semiconductor wafer in a semiconductor fabrication apparatus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device having a capacitance element for storing information, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory). Things.

[0002]

2. Description of the Related Art In one of semiconductor integrated circuit devices, a memory cell is a memory cell selecting MISFET (Metal Insulator).
There is a DRAM composed of a semiconductor field effect transistor) and an information storage capacitor. But DR
The AM has a problem that the memory cell is miniaturized with the increase in the capacity, the amount of charge stored in the information storage capacitor element is reduced, and the information retention characteristic is deteriorated.

Therefore, in a DRAM of 64 Mbit or more, a capacitor over bit line (Capacitor Over B) in which an information storage capacitor is arranged above a bit line.
It has an itline (COB) structure, and the storage electrode has a three-dimensional shape such as a crown structure or a fin structure to increase the surface area to increase the amount of stored charge.

A storage electrode having a crown structure is described in, for example, "Super LSI Memory" published by Baifukan on November 5, 1994, by Kiyo Ito, p.

A method of manufacturing a conventional information storage capacitor having a crown-shaped storage electrode will be briefly described below.

First, after a memory cell selecting MISFET is formed, a silicon oxide film and a BPS
G (Boron Phospho Silicate Glass) film is CVD (Chem
ical vapor deposition) method, and then the above BPS by reflow treatment at 900 to 950 ° C.
MISFET for memory cell selection by flattening the surface of G film
Of the gate electrode is flattened.

Next, a first plug electrode made of a polycrystalline silicon film is formed on one of the first n-type semiconductor regions of the memory cell selecting MISFET to which a storage electrode is to be connected later. A second plug electrode made of a polycrystalline silicon film is formed on the other second n-type semiconductor region of the memory cell selecting MISFET to which the line is connected.

Next, a polycrystalline silicon film and a tungsten silicide film are sequentially deposited on the semiconductor substrate.
After depositing a silicon nitride film having a thickness of about 200 nm, these films are sequentially etched to form a bit line made of a tungsten silicide film and a polycrystalline silicon film, and a cap made of a silicon nitride film on the bit line. Form.

Next, after depositing a silicon nitride film having a thickness of about 100 nm on the semiconductor substrate, this silicon nitride film is
By processing by an IE (Reactive Ion Etching) method, sidewall spacers made of a silicon nitride film are formed on the side walls of the bit lines. The silicon nitride film constituting the cap and the sidewall spacer is formed by a thermal CVD method, and is deposited at a temperature of 750 ° C. using an ammonia (NH ₃ ) gas + dichlorosilane (SiH ₂ Cl ₂ ) gas as a reaction gas. Is done.

Next, a silicon nitride film having a thickness of about 25 nm is deposited on the semiconductor substrate. This film is also formed by a thermal CVD method similarly to the silicon nitride film forming the cap and the side wall spacer, and N 2 is added to the reaction gas.
Deposition is performed at a temperature of 750 ° C. using H ₃ gas + SiH ₂ Cl ₂ gas.

Next, a BPSG film is formed on the semiconductor substrate by CVD.
After deposition by the method, the surface of the BPSG film is flattened to flatten a step due to the bit line. Next, after forming a storage electrode having a crown structure made of a polycrystalline silicon film above the bit line, the dummy oxide film used for forming the storage electrode is removed by wet etching using a hydrofluoric acid aqueous solution. At this time, the silicon nitride film having a thickness of about 25 nm becomes a stopper layer for wet etching.

Next, after a capacitive insulating film is deposited on the surface of the storage electrode, a plate electrode is formed to form an information storage capacitive element.

[0013]

However, the present inventor has found that there are the following problems in forming a storage electrode having a crown structure by the above manufacturing method.

That is, a MISFET for selecting a memory cell
A BPSG film for flattening a step due to the gate electrode is provided above the gate electrode.
Above the G film, a silicon nitride film constituting a bit line cap and a sidewall spacer, and a silicon nitride film serving as a stopper layer when the dummy oxide film is removed by wet etching are deposited.

However, it has been found that when the silicon nitride film is deposited on a semiconductor substrate by a thermal CVD method, a large number of voids are generated in the BPSG film. It is considered that the voids in the BPSG film are generated because tensile stress of the silicon nitride film is generated in the process of lowering the deposition temperature after depositing the silicon nitride film, and the BPSG film below the silicon nitride film is lifted by the tensile stress. Can be Further, when depositing the silicon nitride film, a large amount of unreacted residual gas, for example, ammonia (NH ₃ ) or chlorine (Cl ₂ ) is taken into the silicon nitride film, and these unreacted residual gas is removed from the BPSG film. It is considered that voids in the BPSG film also occur due to diffusion into the BPSG film.

If a void in the BPSG film is in a region where a contact hole for connecting the wiring layer and the semiconductor substrate is opened, poor coverage or poor conduction of the wiring layer occurs. Further, since the thickness of the silicon nitride film remaining on the front surface of the semiconductor wafer is smaller than the thickness of the silicon nitride film remaining on the rear surface, the semiconductor wafer is largely warped in a convex shape. For this reason, when a semiconductor wafer is mounted on a stage of a semiconductor manufacturing apparatus such as an exposure apparatus or an etching apparatus, suction failure is likely to occur. Defective or short-circuit or disconnection of the wiring layer occurs.

An object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor integrated circuit device having a DRAM.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0019]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, first, a BPSG film is deposited above a memory cell selecting MISFET, and then the surface of the BPSG film is flattened to flatten a step of a gate electrode. I do. Next, after forming a bit line connected to one semiconductor region of the memory cell selection MISFET, 770 to 770
The thickness is 20 to 40n by the thermal CVD method at a temperature of 800 ° C.
m silicon nitride film is deposited. Next, after forming the storage electrode of the information storage capacitance element connected to the other semiconductor region of the memory cell selection MISFET, the dummy oxide film used in forming the storage electrode is removed by wet etching. A capacitor insulating film and a plate electrode of the information storage capacitor are sequentially formed.

According to the above means, the silicon nitride film deposited above the BPSG film provided for flattening the step of the gate electrode is formed by the thermal CVD method at a temperature of 770 to 800 ° C. It is a thin silicon nitride film having a thickness of 20 to 40 nm, and this silicon nitride film has the following effects. That is, 1. Since the film thickness is as thin as 20 to 40 nm, the stress is small.

2. Since the film is formed at a relatively high temperature, the stress is small.

3. Since unreacted residual gas such as NH ₃ or Cl ₂ in the silicon nitride film is reduced by forming the film at a relatively high temperature, a change in the film quality of the silicon nitride film is small and a change in stress due to a thermal load is small.

4. Since the unreacted residual gas such as NH ₃ or Cl ₂ in the silicon nitride film is reduced by forming the film at a relatively high temperature, the amount of the unreacted residual gas diffused into the BPSG film is small.

Therefore, since the stress of the silicon nitride film applied to the BPSG film is reduced, voids are less likely to be generated in the BPSG film, and it is possible to prevent the wiring layer from being poorly covered or conducting poorly due to the voids.

Further, since the difference between the thickness of the silicon nitride film remaining on the front surface of the semiconductor wafer and the thickness of the silicon nitride film remaining on the rear surface is reduced, the amount of warpage of the semiconductor wafer is reduced, and a semiconductor device such as an exposure apparatus or etching apparatus is used. Poor suction of semiconductor wafers occurring in the manufacturing apparatus is reduced. As a result, it is possible to prevent processing failure of a pattern requiring fine processing, for example, a contact hole or a wiring layer.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings.

A method of manufacturing a memory cell of a DRAM according to an embodiment of the present invention will be described with reference to FIGS. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

First, as shown in FIG. 1, p ^- type silicon single crystal is formed on a main surface of a semiconductor substrate 1 by a known method.
Mold well 2, field insulating film 3, and gate insulating film 4
Are sequentially formed.

Next, a polycrystalline silicon film 5 into which phosphorus (P) is introduced, a tungsten silicide (WSi ₂ ) film 6, a silicon oxide film 7, and a silicon nitride film 8 are sequentially deposited on the semiconductor substrate 1 by a CVD method. . Thereafter, by sequentially etching the laminated film of photoresist as a mask the silicon nitride film 8, a silicon oxide film 7, WSi ₂ film 6 and the polycrystalline silicon film 5, a WSi ₂ film 6 and the polycrystalline silicon film 5 The gate electrode FG of the memory cell selecting MISFET is formed.

Next, by subjecting the semiconductor substrate 1 to a thermal oxidation treatment, a thin silicon oxide film 9 is formed on the side walls of the WSi ₂ film 6 and the polysilicon film 5 constituting the gate electrode FG.
To form

Thereafter, the silicon nitride film 10 deposited on the semiconductor substrate 1 is processed by anisotropic etching such as RIE to form sidewall spacers on the side walls of the laminated film.

Next, as shown in FIG. 2, after a silicon oxide film 11 and a BPSG film 12 are sequentially deposited on the semiconductor substrate 1 by a CVD method, the surface of the BPSG film 12 is reflowed at 900 to 950 ° C. After planarization, a polycrystalline silicon film (not shown) in which P is introduced is deposited on the semiconductor substrate 1 by a CVD method.

Thereafter, by using a photoresist as a mask, the polycrystalline silicon film, the BPSG film 12, the silicon oxide film 11, and the insulating film of the same layer as the gate insulating film 4 are sequentially etched to obtain a memory cell selecting MISFET.
A first contact hole 14 is formed on a first n-type semiconductor region 13 formed after one of the above. Then, an n-type impurity, for example, P is ion-implanted, and the memory cell selecting M
One first n-type semiconductor region 13 of the ISFET is formed.

Next, after depositing a polycrystalline silicon film 15 into which P is introduced on the semiconductor substrate 1 by a CVD method, the polycrystalline silicon film 15 and the polycrystalline silicon film on the BPSG film 12 are sequentially etched back. By doing
Forming a first plug electrode PG ₁ made of polycrystalline silicon film 15 in the in the first contact hole 14.

Next, a 50 nm-thick silicon oxide film 16 is deposited on the semiconductor substrate 1 by the CVD method. Then, using the photoresist as a mask, the silicon oxide film 1 is formed.
6, a second n-type semiconductor region (17) formed after the other of the memory cell selecting MISFET by sequentially etching the same insulating film as the BPSG film 12, the silicon oxide film 11, and the gate insulating film 4. A second contact hole 18 is formed thereon.

Next, as shown in FIG. 3, after depositing a polycrystalline silicon film 19 into which P is introduced on the semiconductor substrate 1 by the CVD method, the polycrystalline silicon film 19 is etched back, thereby Second contact hole 18
A second plug electrode P made of a polycrystalline silicon film 19 therein.
To form the G _2.

Next, after a P-doped polycrystalline silicon film 20, a WSi ₂ film 21 and a silicon oxide film 22 are sequentially deposited on the semiconductor substrate 1 by CVD, the silicon oxide film 22, WSi ₂
By sequentially etching the laminated film composed of the film 21 and the polycrystalline silicon film 20, a bit line BL composed of the WSi ₂ film 21 and the polycrystalline silicon film 20 is formed.
The thicknesses of the silicon oxide film 22, the WSi ₂ film 21, and the polycrystalline silicon film 20 are, for example, 150 n each.
m, 80 nm and 70 nm.

Thereafter, the silicon oxide film 23 having a thickness of 100 nm deposited on the semiconductor substrate 1 is processed by anisotropic etching such as RIE to form sidewall spacers on the side walls of the laminated film.

The other second n-type semiconductor region 17 of the memory cell selecting MISFET is formed by diffusion of P introduced into the polycrystalline silicon film 19, and the bit line BL
Is connected to the second n-type semiconductor region 17 of the memory cell selecting MISFET through the second contact hole 18.

Next, as shown in FIG. 4, a silicon nitride film 24 is deposited on the semiconductor substrate 1 by a thermal CVD method.
At this time, the silicon nitride film 24 is made of NH ₃ gas + as a reaction gas.
It is formed at a temperature of 770 to 800 ° C. using SiH ₂ Cl ₂ gas, and has a thickness of about 25 nm. Subsequently, after depositing the BPSG film 25 on the semiconductor substrate 1 by the CVD method, the BPSG film 25 is subjected to a reflow process at 900 to 950 ° C.
The surface of the SG film 25 is flattened, and then a silicon oxide film 26 is deposited on the semiconductor substrate 1. Thereafter, a polycrystalline silicon film 27 into which P is introduced with a thickness of about 70 nm is deposited on the semiconductor substrate 1 by a CVD method, and then the polycrystalline silicon film 27 is etched using a photoresist as a mask.

Next, as shown in FIG. 5, a P-doped polycrystalline silicon film 28 is deposited on the semiconductor substrate 1 by the CVD method, and this polycrystalline silicon film 28 is anisotropically formed by the RIE method or the like. By processing by etching, side wall spacers are formed on the side walls of the polycrystalline silicon film 27. Then, the silicon oxide film 26, BPSG film 25, by sequentially etching the silicon film 24 and silicon oxide film 16 nitride, third to first upper Prabhu electrode PG ₁ provided in the first contact hole 14
Is formed. Thereafter, a polycrystalline silicon film 30 into which P is introduced and a silicon oxide film 31 having a thickness of about 500 nm are sequentially deposited on the semiconductor substrate 1 by a CVD method.

Next, as shown in FIG. 6, after the silicon oxide film 31 and the polycrystalline silicon films 30 and 27 are sequentially etched using a photoresist as a mask, the semiconductor substrate 1 is etched.
A polycrystalline silicon film 32 having a thickness of about 100 nm with P introduced therein is deposited thereon by a CVD method.

Next, this polycrystalline silicon film 32 is
By processing with anisotropic etching such as E method,
The silicon oxide film 31 and the polycrystalline silicon film 30,
The cylindrical polycrystalline silicon film 32 is left on the side wall 27.

Subsequently, as shown in FIG. 7, for example, the silicon oxide film 31, the silicon oxide film 26 and the BPSG film 2 are formed by wet etching using a hydrofluoric acid aqueous solution.
5 is removed, and the polycrystalline silicon films 32 and 3 are removed.
A storage electrode having a crown structure including 0, 28, and 27 is formed.

Next, as shown in FIG. 8, an amorphous tungsten oxide (T
After the a ₂ O ₅ ) film 33 is deposited by the CVD method, the Ta ₂ O ₅ film 33 is crystallized by subjecting the semiconductor substrate 1 to a thermal oxidation treatment. Thereafter, a titanium nitride (TiN) film 34 is deposited on the semiconductor substrate 1 by a CVD method, and then the TiN film 34 is etched using a photoresist as a mask to form a plate electrode made of the TiN film 34.

Thereafter, as shown in FIG.
A silicon oxide film 35 and a BPSG film 36
After successive deposition by the method, the surface of the BPSG film 36 is flattened by a reflow treatment at 900 to 950 ° C.
Next, the BPSG film 36 is formed using the photoresist as a mask.
Then, a fourth contact hole (not shown) is formed by sequentially etching the silicon oxide film 35.

Next, a metal film having a laminated structure in which, for example, a titanium (Ti) film, a titanium nitride (TiN) film, an aluminum (Al) alloy film and a titanium nitride (TiN) film are sequentially deposited on the semiconductor substrate 1 is formed. After the formation, the first wiring layer 37 is formed by etching the metal film having the laminated structure using a photoresist as a mask.

Next, TEOS (Tetra
A silicon oxide film is deposited by a plasma CVD method using Ethyl Ortho Silicate (Si (OC ₂ H ₅ ) ₄ ) as a source, and then SOG (Spin On Glass) is formed on the semiconductor substrate 1.
Apply the film. Thereafter, the SOG film is etched back by the RIE method to perform a flattening process.
By depositing a silicon oxide film by a plasma CVD method using EOS as a source, an interlayer insulating film 38 having a three-layer structure is provided. Thereafter, the interlayer insulating film 38 is etched using a photoresist as a mask to form a through hole (not shown).

Next, for example, Ti
After forming a metal film having a laminated structure in which a film, a TiN film, an Al alloy film, and a TiN film are sequentially deposited, the second wiring layer 39 is formed by etching the metal film having the laminated structure using a photoresist as a mask. I do.

Finally, by covering the surface of the semiconductor substrate 1 with a passivation film (not shown), the DRAM memory cell of the present embodiment is completed.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, a case where the present invention is applied to a storage electrode having a crown structure has been described. However, the present invention is also applicable to a storage electrode having a fin structure.

[0054]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the occurrence of voids in the BPSG film can be suppressed, so that the coating failure or conduction failure of the wiring layer can be prevented, and the occurrence of suction failure of the semiconductor wafer in the semiconductor manufacturing apparatus can be suppressed. As a result, processing defects of the fine pattern can be prevented, so that the production yield of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a memory cell of a DRAM according to an embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

DESCRIPTION OF SYMBOLS 1 semiconductor substrate 2 p-type well 3 field insulating film 4 gate insulating film 5 polycrystalline silicon film 6 tungsten silicide (WSi ₂ ) film 7 silicon oxide film 8 silicon nitride film 9 silicon oxide film 10 silicon nitride film ( Side wall spacer) 11 silicon oxide film 12 BPSG film 13 first n-type semiconductor region 14 first contact hole 15 polycrystalline silicon film 16 silicon oxide film 17 second n-type semiconductor region 18 second contact hole 19 multi Crystal silicon film 20 polycrystalline silicon film 21 tungsten silicide (WSi ₂ ) film 22 silicon oxide film 23 silicon oxide film (sidewall spacer) 24 silicon nitride film 25 BPSG film 26 silicon oxide film 27 polycrystalline silicon film 28 polycrystalline silicon film (side Orusupesa) 29 third contact hole 30 a polycrystalline silicon film 31 a silicon oxide film 32 a polycrystalline silicon film 33 of tungsten oxide (Ta ₂ O ₅₎ film 34 of titanium nitride (TiN) film 35 a silicon oxide film 36 BPSG film 37 first Wiring layer 38 Interlayer insulating film 39 Second wiring layer FG Gate electrode PG ₁ First plug electrode PG ₂ Second plug electrode BL Bit line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/04 21/822 (72) Inventor Keizo Kawakita 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device development center (72 ) Inventor Toshihiro Sekiguchi 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. Inventor Katsunori Matsunaga 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Pref. Within Nippon Texas Instruments Co., Ltd.

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device having a DRAM in which an information storage capacitive element is arranged above a memory cell selecting MISFET, comprising:
(E) a method of manufacturing a semiconductor integrated circuit device, (a) a step of depositing a BPSG film above the memory cell selecting MISFET and then planarizing the surface of the BPSG film; (b) ) The MIS for selecting the memory cell
Forming a bit line connected to one semiconductor region of the FET; (c) 770-800 above the bit line
Depositing a silicon nitride film having a thickness of 20 to 40 nm by a thermal CVD method at a temperature of ° C., and (d) forming a storage electrode of the information storage capacitor element connected to the other semiconductor region of the memory cell selecting MISFET. Forming (e)
Removing the dummy oxide film used for forming the storage electrode by wet etching. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said silicon nitride film is formed by using an ammonia gas and a dichlorosilane gas as reaction gases. Manufacturing method. 3. The semiconductor integrated circuit device according to claim 1, wherein said silicon nitride film is a stopper layer for removing said dummy oxide film by wet etching. Manufacturing method. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said storage electrode has a crown structure or a fin structure. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a silicon oxide film is formed on upper portions and side walls of said bit lines.