JPH10171418A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a thinning processing without changing the AC cycle of a liquid crystal display device with respect to the thinning processing which is performed for display of more video signals than effective lines. SOLUTION: The output of a counter circuit 21 to which a vertical synchronizing signal Vsync and a horizontal synchronizing signal Hsync is compared with a set value set to a thinning setting circuit 22 by a comparison circuit 23; and while they coincide with each other as the result of comparison, the output of a gate clock generation circuit 25 is stopped, and VGON (a voltage which turns on a thin film transistor in a liquid crystal panel) from a voltage generation circuit 24 to a gate driver circuit 26 is fixed to VGOFF (a voltage which turns off the thin film transistor). Thus, display is performed without influences upon the display quality and the life of liquid crystal like unevenness of display, printing, flicker, the reduction of the life of liquid crystal because symmetry of a liquid crystal voltage to a counter electrode voltage VCOM is secured between fields.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an information processing terminal,
The present invention relates to a liquid crystal display device used for a television monitor or the like, particularly to a liquid crystal display device driven by capacitive coupling.

[0002]

2. Description of the Related Art A conventional liquid crystal display of this type is configured as shown in a conceptual diagram of FIG. In FIG. 5, 1
Denotes a driving source driver circuit, 2 denotes a TFT liquid crystal panel, and 3 denotes a driving gate driver circuit. FIG. 6 is an equivalent circuit diagram showing a circuit configuration of a capacitively driven TFT liquid crystal panel. In FIG. 6, 5a and 5b are gate signal lines, 6a and 6b are source signal lines, 7 is a pixel electrode of the liquid crystal panel, 8 is an auxiliary capacitor formed between the pixel electrode 7 and the preceding gate signal line 5a, 9 is TFT
(Thin film transistor), 10 is a common electrode common to all pixels.

FIG. 7A shows a gate signal waveform of a liquid crystal panel driven by capacitive coupling, and FIG. 7B shows an image signal voltage V
FIG. 6 is a diagram showing a temporal change of the waveform of the common electrode voltage VCOM. Assuming that the gate signal voltage is Vg, four voltages of a voltage VGON for turning on the TFT, a voltage VGOFF for turning off the TFT, and compensation voltages VE + and VE− are used. Compensation voltage V
E + and VE- are alternately applied for each gate signal line (or auxiliary capacitance line). As a result, the liquid crystal voltage VIc applied to the pixel is expressed in units of fields as shown in FIG. 3 described later.

In a liquid crystal display device driven by capacitive coupling, particularly when used in a television monitor, the
When an image of the PAL system is displayed on a liquid crystal display device for the TSC system, it is necessary to perform a line thinning process due to a difference in effective lines, and the line is thinned by a method of eliminating a gate clock.

FIG. 8 is a block diagram showing a circuit configuration for performing a thinning process in a conventional liquid crystal display device. Reference numeral 11 denotes a vertical synchronization signal (hereinafter, referred to as Vsync) and a horizontal synchronization signal (hereinafter, referred to as Vsync).
Hsync) counter, 12 is a thinning setting circuit that sets a thinning line, 13 is a comparison circuit that compares the output of the counter circuit 11 with the output result of the thinning setting circuit 12 and outputs the result to a gate clock generation circuit described later. Circuit, 14
Are VGON, VGOF for the gate driver circuit described later.
A voltage generating circuit for outputting four voltages F, VE +, VE-, a gate clock generating circuit 15 for a gate driver circuit, and a gate driver circuit 16 for driving a liquid crystal TFT.

FIG. 9 is a diagram showing signal waveforms at the time of thinning processing in the conventional capacitive coupling drive. FIG. 10 is a diagram showing the waveform of the liquid crystal voltage VIc applied to the pixel during the thinning processing.

The operation of the conventional liquid crystal display device configured as described above will be described. As shown in FIG.
The output of the counter circuit 11 having Vsync and Hsync as inputs is compared with the set value of the thinning-out setting circuit 12 by the comparison circuit 13, and during the period when the comparison results match, the gate clock generation circuit
Stop output of 15. As a result, during the stop period of the gate clock shown in FIG. 9, VGON is output over two lines of the thinned line (one horizontal scanning period) like the gate signal waveform n and the next line (period A). Then, a waveform of the liquid crystal voltage VIc as shown in FIG. 10 is obtained.

[0008]

However, in the image forming apparatus having such a configuration, the time during which the VGON voltage is applied becomes longer as shown by the gate signal waveform n of the thinned line shown in FIG. In the next line capacitively coupled to the line, the counter electrode voltage V between the fields
The liquid crystal voltage VIc with respect to COM becomes asymmetric (see FIG. 10). As a result, uneven display, printing, flicker,
There is a problem that the life of the liquid crystal is shortened.

The present invention solves the above-mentioned problem of the prior art, and realizes a thinning process without changing an alternating cycle of a liquid crystal display device by performing a thinning process for displaying a video signal having more than effective lines. It is another object of the present invention to provide a liquid crystal display device which is free from display unevenness, printing, flickering, and a reduction in liquid crystal life.

[0010]

In order to achieve this object, a liquid crystal display device according to the present invention comprises a pixel electrode arranged in a matrix and connected to a first scanning signal line via a capacitor; A switching element electrically connected to each of the electrode, the image signal wiring, and the second scanning signal wiring;
A counter electrode to which a constant voltage is supplied, and a display material held between the counter electrode and the pixel electrode; an image signal voltage is transmitted to the pixel electrode during an on time of the switching element; By applying a modulation signal in which the voltage changes in the reverse direction every one vertical scanning period to the first scanning signal line, the voltage of the pixel electrode is changed, and the change in the voltage and the image signal voltage are superimposed or canceled each other. In a liquid crystal display device in which a display material is capacitively driven by applying a voltage to be applied, a shift register is internally provided, one of the voltages input according to the register value is selected, and a predetermined voltage is applied to each scanning signal line. A gate driver circuit for outputting, a counting circuit for counting the horizontal synchronizing signal and comparing it with a predetermined period set in advance to perform thinning-out determination; Characterized in that it comprises a generator of a clock to the shift register, and a generation circuit of the voltage inputted to the gate driver circuit.

Further, the gate driver circuit is configured to include an off control terminal for inputting a thinning-out determination output of the counting circuit.

According to the above configuration, when a video signal having a display capability higher than the display capability of the liquid crystal display device is input, the clock to the shift register of the gate driver circuit is stopped by the thinning-out determination output of the counting circuit, and the gate driver is stopped. All the voltages input to the circuit can be fixed at a predetermined voltage.

Further, the output voltage of the gate driver circuit can be fixedly output to a predetermined voltage value irrespective of an internal register value by inputting an ON control terminal provided in the gate driver circuit.

Further, only the voltage value corresponding to the on-level of the voltage output from the gate driver circuit is fixedly output at the off-level according to the thinning-out judgment input of the off-control terminal, so that more video signals than the effective lines are displayed unevenly and printed. It can be displayed on the liquid crystal display device without being affected by, for example, flicker, reduction in the life of the liquid crystal, and the like.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration for performing a thinning process of the liquid crystal display device according to the first embodiment of the present invention. In FIG. 1, 21 is V
A counter circuit for counting sync (vertical synchronization signal) and Hsync (horizontal synchronization signal), 22 is a thinning setting circuit for setting a thinning line, and 23 is an output of the counter circuit 21 and a thinning setting circuit.
A comparison circuit 22 compares the output result of 22. 24 is a VGON, VGOFF, VE +, VE-
A voltage generation circuit for selecting and outputting the four voltages according to the output of the comparison circuit 23, a gate clock generation circuit 25 for a gate driver circuit, and a gate driver circuit 26 for driving a liquid crystal TFT. The counting circuit includes a counter circuit 21, a thinning setting circuit 22, and a comparing circuit 23.

FIG. 2 is a diagram showing signal waveforms at the time of thinning processing in the capacitive coupling drive according to the first embodiment.
The broken line in FIG. 2 is a waveform according to the conventional method shown in FIG. FIG. 3 is a diagram showing the waveform of the liquid crystal voltage VIc applied to the pixel (display material) at the time of the thinning processing, which is the same as the signal waveform of the normal capacitive coupling drive without thinning.

The operation of the liquid crystal display device according to the first embodiment configured as described above will be described below. Vsy
The comparison circuit 23 compares the output of the counter circuit 21 having nc and Hsync as inputs with the set value set in the thinning-out setting circuit 22,
During the period when the comparison result matches, the output of the gate clock generation circuit 25 is stopped, and at the same time, the gate driver circuit is stopped.
VGON output from the voltage generation circuit 24 to VGOF
F (see gate signal waveform n shown in FIG. 2). Thus, according to the first embodiment, as shown in FIG. 3, the liquid crystal voltage V with respect to the common electrode voltage VCOM between the fields.
Since the symmetry of Ic is ensured, uneven display, printing,
The display can be performed without affecting the display quality and the life of the liquid crystal such as flicker and reduction of the life of the liquid crystal.

FIG. 4 shows Embodiment 2 of the present invention.
FIG. 3 is a block diagram showing a circuit configuration for performing a thinning process of the liquid crystal display device of FIG. In FIG. 4, 31 is a counter circuit for counting Vsync and Hsync, 32 is a thinning setting circuit for setting a thinning line, 33 is a comparing circuit for comparing the output of the counter circuit 31 with the output result of the thinning setting circuit 32, and 34 is a gate. A voltage generation circuit for outputting four voltages VGON, VGOFF, VE +, VE- to the driver circuit, 35 is a gate clock generation circuit for a gate driver circuit, and 36 is a liquid crystal TFT.
And a gate driver circuit that selectively outputs a predetermined voltage at the timing of the thinning process by the output signal (DOFF) of the comparison circuit 33 input to the off control terminal.

The operation of the liquid crystal display device according to the second embodiment configured as described above will be described below. Vsy
The output of the counter circuit 31 having nc and Hsync as inputs is compared with the set value of the thinning-out setting circuit 32 by the comparison circuit 33, and the output of the gate clock generation circuit 35 is stopped during the period when the comparison results match. At the same time, the gate driver circuit 36 selectively outputs the output of the voltage generation circuit 34 or an arbitrary voltage according to the output signal (DOFF) of the thinning process from the comparison circuit 33 to the gate driver circuit 36.

In the second embodiment as described above, the selected output of the output voltage of the voltage generation circuit 34 is set to an arbitrary voltage at the timing of the thinning-out processing in the gate driver circuit 36. In addition, it is possible to ensure the symmetry of the liquid crystal voltage VIc at the time of the thinning processing, and display can be performed without affecting display quality and liquid crystal life such as display unevenness, burn-in, flicker, and decrease in liquid crystal life.

Next, a third embodiment of the present invention will be described. The block diagram showing the circuit configuration for performing the thinning processing of the liquid crystal display device according to the third embodiment is the same as that of FIG. 4 showing the second embodiment, but in the operation, the output signal (DOFF) of the thinning processing is used. , And the gate driver circuit 36 selectively outputs VGOFF. Therefore, the waveforms are the same as in FIGS. 2 and 3 showing the respective waveforms in the first embodiment, and as in the first embodiment, the symmetry of the liquid crystal voltage VIc at the time of the thinning process can be ensured. The display can be performed without affecting display quality and liquid crystal life, such as burn-in, flicker, and reduction in liquid crystal life.

[0022]

As described above, according to the present invention,
In a liquid crystal display device driven by capacitive coupling, the thinning-out process performed to display more video signals than the effective lines is performed without changing the AC cycle of the liquid crystal display device.
Furthermore, it is possible to display video signals of more lines than the liquid crystal display device without being affected by display quality and liquid crystal life, such as display unevenness, burn-in, flicker, and reduction of liquid crystal life, thereby obtaining an image with high display quality. It works.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration for performing a thinning process of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing signal waveforms at the time of thinning processing in capacitive coupling drive according to the first embodiment.

FIG. 3 is a diagram showing a waveform of a liquid crystal voltage VIc applied to a pixel during a thinning process according to the first embodiment.

FIG. 4 is a block diagram illustrating a circuit configuration for performing a thinning process of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 5 is a conceptual diagram showing a configuration of a conventional liquid crystal display device.

FIG. 6 is an equivalent circuit diagram showing a circuit configuration of a conventional capacitively driven TFT liquid crystal panel.

7A is a gate signal waveform of a liquid crystal panel driven by capacitive coupling, and FIG. 7B is an image signal voltage Vs and a counter electrode voltage VC.
FIG. 6 is a diagram illustrating a temporal change of an OM waveform.

FIG. 8 is a block diagram showing a circuit configuration for performing a thinning process in a conventional liquid crystal display device.

FIG. 9 is a diagram showing signal waveforms at the time of thinning processing in the conventional capacitive coupling drive.

FIG. 10 is a diagram showing a waveform of a liquid crystal voltage VIc applied to a pixel during a conventional thinning process.

[Explanation of symbols]

1. Source driver circuit 2. TFT liquid crystal panel
3: gate driver circuit, 5a, 5b: gate signal line, 6a, 6b: source signal line, 7: pixel electrode,
8: storage capacitor, 9: TFT, 10: counter electrode, 1
1, 21, 31 ... counter circuit, 12, 22, 32 ... thinning setting circuit, 13, 23, 33 ... comparison circuit, 14, 24, 34 ... voltage generation circuit, 15, 25, 35 ... gate clock generation circuit, 1
6, 26, 36: Gate driver circuit.

Claims (3)

[Claims] 1. A pixel electrode arranged in a matrix and connected to a first scanning signal line via a capacitor, and electrically connected to each of the pixel electrode, the image signal line and the second scanning signal line. A switching element, a counter electrode to which a constant voltage is supplied, and a display material held between the counter electrode and the pixel electrode; and transmitting an image signal voltage to the pixel electrode during an ON time of the switching element. And applying a modulation signal in which the voltage changes in the reverse direction every one vertical scanning period to the first scanning signal line during the off time of the switching element, thereby changing the voltage of the pixel electrode, and changing the voltage and the voltage. A liquid crystal display device in which the display material is capacitively coupled and driven by applying a voltage that superimposes or cancels the image signal voltage on each other. Accordingly, a gate driver circuit that selects one of the input voltages and outputs a predetermined voltage to each scanning signal wiring, counts the horizontal synchronization signal, compares it with a predetermined period set in advance, and performs thinning determination. A counting circuit, a circuit for generating a clock to a shift register of the gate driver circuit,
A circuit for generating a voltage to be input to a gate driver circuit, wherein when a video signal having a display capability equal to or greater than the display capability of the liquid crystal display device is input, a clock to the shift register of the gate driver circuit is output by the thinning-out determination output of the counting circuit. , And all voltages input to the gate driver circuit are fixed to predetermined voltages. 2. The gate driver circuit according to claim 1, further comprising an off control terminal for inputting a thinning-out determination output of the counting circuit, and fixing an output voltage to a predetermined voltage value by an input of the off control terminal regardless of an internal register value. The liquid crystal display device according to claim 1, wherein: 3. The liquid crystal display device according to claim 2, wherein the gate driver circuit fixes only a voltage value corresponding to an on level of a voltage output by a thinning determination input of an off control terminal to an off level. .