JPH10170612A - Method and device for inspecting internal mutual wiring in semiconductor integrated circuit - Google Patents

Method and device for inspecting internal mutual wiring in semiconductor integrated circuit

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Publication number
JPH10170612A
JPH10170612A JP9290734A JP29073497A JPH10170612A JP H10170612 A JPH10170612 A JP H10170612A JP 9290734 A JP9290734 A JP 9290734A JP 29073497 A JP29073497 A JP 29073497A JP H10170612 A JPH10170612 A JP H10170612A
Authority
JP
Japan
Prior art keywords
semiconductor integrated
integrated circuit
current
wiring
change
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9290734A
Other languages
Japanese (ja)
Inventor
Kiyoshi Futagawa
清 二川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9290734A priority Critical patent/JPH10170612A/en
Publication of JPH10170612A publication Critical patent/JPH10170612A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PROBLEM TO BE SOLVED: To detect defects of internal mutual wiring in semiconductor integrated circuit quickly and non-destructively. SOLUTION: In the condition where electric current is supplied on a semiconductor integrated circuit chip 1 from a voltage supplying source 9, narrowed laser light is scanned and radiated on the chip 1, and a variable current detecting/amplifying component 8 detects a part where current changes largely. Because the part with large current change detected by the variable current detecting/amplifying component 8 is corresponding to the part where heat conduction is disturbed, defects such as void are detected. Based on this principle, even a defect which is not exposed on the surface can be detected.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体集積回路チッ
プ上の欠陥の検査方法および装置に関し、特に半導体集
積回路チップ上内部相互配線の欠陥をレーザビームまた
は電子ビームやイオンビームを用いて検査する方法およ
び装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for inspecting a defect on a semiconductor integrated circuit chip, and more particularly to a method for inspecting a defect of an internal interconnection on a semiconductor integrated circuit chip by using a laser beam, an electron beam or an ion beam. And devices.

【0002】[0002]

【従来の技術】従来、この種の欠陥の「検査方法および
装置」(以下「方法」とのみ略して記す)は、たとえば
「W.,Lee Smith et.al.,“Dir
ectmeasurement of stress−
induced voidgrowth by the
rmal wave modulated optic
al reflectance imaging”,1
990IRPS(IEEE),200−208,(19
90).」に示されるように、2種類のレーザビームを
用い、一方のレーザビームでプローブし、もう一方のビ
ームで検知するという方法をとっている。
2. Description of the Related Art Conventionally, this type of defect "inspection method and apparatus" (hereinafter abbreviated as "method" only) is described, for example, in "W., Lee Smith et. Al.," Dir.
ectmeasurement of stress-
induced voidby by the
rmal wave modulated optic
al reflection imaging ", 1
990 IRPS (IEEE), 200-208, (19
90). As shown in ", two types of laser beams are used, a probe is made with one laser beam, and a detection is made with the other beam.

【0003】図3は、従来の半導体集積回路チップ上内
部相互配線の欠陥をレーザビームを用いて検査する方法
の一例(第1の従来例)を示す図である。プローブレー
ザ発生部19からのプローブレーザ21により試料26
をプローブする。一方、ポンプレーザ発生部18から、
ポンプレーザと呼ばれる強度変化のあるレーザ20を試
料26上に照射し、その結果試料上に生じた反射率の変
化をプローブレーザ21の反射率の変化としてサーマル
ウェーブシグナル検出器22で検出する。
FIG. 3 is a diagram showing an example (first conventional example) of a conventional method for inspecting a defect of an internal interconnection on a semiconductor integrated circuit chip using a laser beam. The sample 26 is generated by the probe laser 21 from the probe laser generator 19.
Probe. On the other hand, from the pump laser generator 18,
The sample 26 is irradiated with a laser 20 having a change in intensity called a pump laser, and a change in the reflectance generated on the sample as a result is detected by the thermal wave signal detector 22 as a change in the reflectance of the probe laser 21.

【0004】図中、24はプローブレーザ強度の時間変
化を示し、23はポンプレーザ強度の時間変化を示し、
25はサーマルウェーブシグナルによる反射率の検出を
示している。
[0004] In the figure, reference numeral 24 denotes a time change of the probe laser intensity, 23 denotes a time change of the pump laser intensity,
25 shows the detection of the reflectance by the thermal wave signal.

【0005】また半導体試料の欠陥を検査する方法に
も、レーザビームを用いるものがある(第2の従来
例)。これは図4にその概念を示すように、電圧供給源
9により電圧が印加された半導体試料27にレーザビー
ム17を照射し、その結果半導体内部に発生する電子−
正孔対(電子28,正孔29)を電流の変化として検出
しようとするもので、OBIC(optical be
am induced current)法としてよく
知られている。
There is also a method for inspecting a defect in a semiconductor sample using a laser beam (second conventional example). As shown in FIG. 4, a semiconductor sample 27 to which a voltage is applied by the voltage supply source 9 is irradiated with a laser beam 17, and as a result, electrons generated inside the semiconductor are exposed.
A hole pair (electrons 28, holes 29) is to be detected as a change in current, and an OBIC (optical bead) is detected.
It is well known as the am induced current method.

【0006】[0006]

【発明が解決しようとする課題】図3で説明した従来の
欠陥検出法では、レーザを2台用いる必要があり、かつ
その2つのレーザビームをμmオーダからサブμmオー
ダの精度で同一箇所に照射しなければならないため、レ
ーザビームを直接走査できず、試料台を走査しなければ
ならない。従って走査に時間がかかり、像を取得するの
に時間がかかるという問題があった。
In the conventional defect detection method described with reference to FIG. 3, it is necessary to use two lasers, and the two laser beams are irradiated to the same spot with an accuracy of the order of μm to sub-μm. Therefore, the laser beam cannot be directly scanned, and the sample stage must be scanned. Therefore, there is a problem that it takes time to scan, and it takes time to acquire an image.

【0007】また図4で説明した従来のOBIC法は、
試料が半導体あるいは半導体を含むものを対象物質とし
ており、金属を対象物質とすることについては、開示し
ていない。
The conventional OBIC method described with reference to FIG.
It does not disclose that the sample is a semiconductor or a substance containing a semiconductor and that a metal is the target substance.

【0008】本発明の目的は、照射レーザ自体を走査で
き、半導体集積回路の内部相互配線の欠陥を短時間で非
破壊で検出する検査方法および装置を提供することにあ
る。
It is an object of the present invention to provide an inspection method and apparatus capable of scanning an irradiation laser itself and detecting a defect of an internal interconnection of a semiconductor integrated circuit in a short time without destruction.

【0009】[0009]

【課題を解決するための手段】本発明の半導体集積回路
内部相互配線の検査方法は、半導体集積回路の内部相互
配線に電流を流した状態で、半導体集積回路にレーザビ
ームを走査しながら照射加熱し、照射による温度上昇に
起因する配線抵抗の増大によって生じる前記内部相互配
線に流れる電流の変化を検知し、欠陥のある箇所では熱
伝導が悪化し前記配線の抵抗が欠陥がないところより増
大することにより電流変化がより大きくなることで前記
内部相互配線の欠陥を検出することを特徴とする。
According to the present invention, there is provided a method for inspecting internal interconnections of a semiconductor integrated circuit, the method comprising: applying irradiation current to a semiconductor integrated circuit while scanning a laser beam while applying a current to the internal interconnections of the semiconductor integrated circuit; Then, a change in a current flowing through the internal interconnection, which is caused by an increase in wiring resistance due to a rise in temperature due to irradiation, is detected. At a defective portion, heat conduction is deteriorated, and the resistance of the wiring is increased from a position without a defect. In this case, the defect of the internal interconnection is detected by increasing the current change.

【0010】本発明の半導体集積回路内部相互配線の検
査装置は、半導体集積回路の内部相互配線に電流を供給
する手段と、前記半導体集積回路にレーザビームを走査
しながら照射加熱するレーザビーム照射加熱手段と、照
射による温度上昇に起因する配線抵抗の増大によって生
じる前記内部相互配線に流れる電流の変化を検知し、欠
陥のある箇所では熱伝導が悪化し前記配線の抵抗が欠陥
のないところより増大することにより電流変化がより大
きくなることで前記内部相互配線の欠陥を検出する手段
と、を備えることを特徴とする。
According to the present invention, there is provided an apparatus for inspecting internal interconnections of a semiconductor integrated circuit, comprising: means for supplying a current to the internal interconnections of the semiconductor integrated circuit; and laser beam irradiation heating for irradiating and heating the semiconductor integrated circuit while scanning the laser beam. Means for detecting a change in a current flowing through the internal interconnection caused by an increase in wiring resistance caused by a temperature rise due to irradiation, and in a defective portion, heat conduction is deteriorated, and the resistance of the wiring is increased from a position without a defect. Means for detecting a defect in the internal interconnection due to a larger current change.

【0011】[0011]

【発明の実施の形態】次に本発明の実施例について図面
を参照して説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

【0012】図1は、本発明の一実施例を示す装置構成
図である。この半導体集積回路内部相互配線の検査装置
は、検査対象物である試料を設置する試料台3を備え、
この試料台3には、試料に電圧を供給する電圧供給源9
と、試料の各点にレーザビームを照射した瞬間の電流の
変化を検出する変動電流検出/増幅部8とが、電流伝送
路13a,13bをそれぞれ介して接続されている。ま
た、試料台3には、試料の温度を制御するための温度制
御部10が、熱媒体用パイプ12を介して連結されてい
る。
FIG. 1 is a block diagram of an apparatus showing one embodiment of the present invention. The apparatus for inspecting interconnections inside a semiconductor integrated circuit includes a sample table 3 on which a sample to be inspected is placed.
The sample stage 3 has a voltage source 9 for supplying a voltage to the sample.
And a fluctuating current detection / amplification unit 8 for detecting a change in current at the moment when the laser beam is irradiated to each point of the sample, are connected via current transmission paths 13a and 13b, respectively. Further, a temperature control unit 10 for controlling the temperature of the sample is connected to the sample table 3 via a heat medium pipe 12.

【0013】試料台3の上部には、レーザを発生するレ
ーザ発生部6,レーザを試料に走査するレーザ走査部5
と、顕微鏡部4とが設けられている。
A laser generator 6 for generating a laser and a laser scanner 5 for scanning the sample with the laser are provided above the sample table 3.
And a microscope unit 4 are provided.

【0014】本実施例の装置は、さらに、信号処理/画
像処理/システム制御部7と、これに接続されたCRT
15とを備えている。
The apparatus of this embodiment further includes a signal processing / image processing / system control unit 7 and a CRT connected thereto.
15 is provided.

【0015】信号処理/画像処理/システム制御部7
は、信号線14を介してレーザ走査部5と、変動電流検
出/増幅部8と、温度制御部10に接続されており、信
号を位置と輝度の情報に変換したのちCRT15上に、
輝度が電流値の変化に対応した像として表示させる。
Signal processing / image processing / system control unit 7
Is connected to the laser scanning unit 5, the fluctuating current detection / amplification unit 8, and the temperature control unit 10 via the signal line 14, and converts the signal into position and luminance information, and then, on the CRT 15,
The luminance is displayed as an image corresponding to the change in the current value.

【0016】次に、この検査装置を用いて、半導体集積
回路内部相互配線の欠陥を検出する方法を説明する。
Next, a description will be given of a method for detecting a defect in an interconnection inside a semiconductor integrated circuit using the inspection apparatus.

【0017】チップ1がマウントされたパッケージ2を
試料台3に設置する。チップ1に電圧供給源9から電圧
を供給する。これによりチップ配線に電圧が印加され
る。この状態で、レーザ発生部6は、レーザを発生す
る。発生されたレーザは光伝送路11を経てレーザ走査
部5へ送られる。顕微鏡部4を介して、μmオーダから
サブμmオーダに絞ったレーザ光17をチップ1上に走
査しながら照射する。レーザ光の照射によりチップ上配
線に流れる電流が変化する。チップ1上の各点での電流
の変化を変動電流検出/増幅部8で検出し、信号処理/
画像処理/システム制御部7で信号を位置と輝度の情報
に変換したのち、CRT15上に、輝度が電流値の変化
に対応した像として表示する。ボイド等の欠陥がある箇
所は熱伝導が悪いためその付近の抵抗が増大する結果、
電流変化が大きくなる。従って電流の変化に対応したコ
ントラストの変化が観測できる。欠陥が表面に出ておら
ず光学顕微鏡像や走査型電子顕微鏡像では検出できない
欠陥が検出できる点は前述の第1の従来例と同様であ
る。また、検出の感度を上げるためにレーザを照射しな
い状態での電流量をできる限り減らすために、温度制御
部10から熱媒体用パイプ12を介してチップ1の温度
を制御し最も電流の小さい温度においてこの検査を実施
することも有効である。
A package 2 on which a chip 1 is mounted is placed on a sample table 3. A voltage is supplied to the chip 1 from a voltage supply 9. As a result, a voltage is applied to the chip wiring. In this state, the laser generator 6 generates a laser. The generated laser is sent to the laser scanning unit 5 via the optical transmission line 11. A laser beam 17 focused from the order of μm to the order of sub μm is irradiated onto the chip 1 through the microscope unit 4 while scanning. The current flowing through the on-chip wiring changes due to the irradiation of the laser light. A change in current at each point on the chip 1 is detected by a fluctuating current detection / amplification unit 8 and signal processing / amplification is performed.
After the signal is converted into position and luminance information by the image processing / system control unit 7, the luminance is displayed on the CRT 15 as an image corresponding to the change in the current value. As there is a defect such as voids, heat conduction is poor, and as a result, the resistance in the vicinity increases,
The current change increases. Therefore, a change in contrast corresponding to a change in current can be observed. It is the same as the above-mentioned first conventional example in that the defect can not be detected on the surface and cannot be detected by the optical microscope image or the scanning electron microscope image. In order to reduce the amount of current without laser irradiation as much as possible to increase the detection sensitivity, the temperature of the chip 1 is controlled from the temperature control unit 10 via the heat medium pipe 12, and the temperature at which the current is minimized is controlled. It is also effective to carry out this inspection in.

【0018】図2は、本発明の検査装置の他の実施例を
示す図である。本実施例は、図1での電圧供給源9をL
SIテスタ16に置き換えたことが特徴である。その他
の構成は、図1と同一であり、同一の構成要素には、同
一の参照番号を付して示してあるが、レーザ発生部6,
レーザ走査部5,顕微鏡部4,信号処理/画像処理/シ
ステム制御部7,温度制御部10は図示を省略してあ
る。
FIG. 2 is a view showing another embodiment of the inspection apparatus of the present invention. In the present embodiment, the voltage supply source 9 in FIG.
The feature is that the SI tester 16 is replaced. Other configurations are the same as those in FIG. 1, and the same components are denoted by the same reference numerals.
The laser scanning unit 5, microscope unit 4, signal processing / image processing / system control unit 7, and temperature control unit 10 are not shown.

【0019】LSIテスタ16は、電流伝送路13によ
り、図示のようにパッケージ2,変動電流検出/増幅部
8に接続され、また、信号線31によりパッケージ2に
接続されている。
The LSI tester 16 is connected to the package 2 and the fluctuating current detecting / amplifying unit 8 by a current transmission path 13 as shown in the figure, and is connected to the package 2 by a signal line 31.

【0020】本実施例によれば、LSIテスタにより電
源供給および信号供給を行いながらこの検査を実施する
ことで、特別な動作状態でしか電流が流れないようなチ
ップ上の内部相互配線に対しても検査が可能になる。
According to the present embodiment, by performing this inspection while supplying power and signals by the LSI tester, internal interconnections on the chip on which a current flows only in a special operation state are provided. Can also be inspected.

【0021】以上、本発明の実施例を説明したが、本発
明はこれら実施例に限定されるものではない。例えば、
レーザビームの代わりに電子ビームやイオンビームを用
いることもできる。
Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments. For example,
An electron beam or an ion beam can be used instead of a laser beam.

【0022】[0022]

【発明の効果】以上説明したように、本発明の欠陥検査
方法および装置では、欠陥検出のための特性値として抵
抗の温度変化を用いているので、その変化を見るために
照射するレーザは1本で済み、従来のように2本のレー
ザビームの位置合わせが不要となるため、照射レーザ自
体を走査することが容易にでき、高速な走査が可能なた
め像取得時間の大幅な短縮が計れる。一例では、第1の
従来例では6分かかったものが、本発明による方法では
0.5秒と実に7200分の1という大幅な短縮が実現
できた。
As described above, in the defect inspection method and apparatus according to the present invention, the temperature change of the resistance is used as the characteristic value for defect detection. Since it is only necessary to use a book, it is not necessary to align the two laser beams as in the related art, so that the irradiation laser itself can be easily scanned, and high-speed scanning can be performed, so that the image acquisition time can be greatly reduced. . In one example, the method according to the present invention, which took 6 minutes in the first conventional example, was able to realize a significant reduction of 0.5 seconds to 1 / 7,200.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1の実施例を示す装置構成図である。FIG. 1 is an apparatus configuration diagram showing a first embodiment.

【図2】第2の実施例を示す装置構成図である。FIG. 2 is an apparatus configuration diagram showing a second embodiment.

【図3】第1の従来例を示す概念図である。FIG. 3 is a conceptual diagram showing a first conventional example.

【図4】第2の従来例を示す概念図である。FIG. 4 is a conceptual diagram showing a second conventional example.

【符号の説明】[Explanation of symbols]

1 チップ 2 パッケージ 3 試料台 4 顕微鏡部 5 レーザ走査部 6 レーザ発生部 7 信号処理/画像処理/システム制御部 8 変動電流検出/増幅部 9 電圧供給源 10 温度制御部 11 光伝送路 12 熱媒体用パイプ 13 電流伝送路(電源線) 14,31 信号線 15 CRT 16 LSIテスタ 17 レーザ 18 ポンプレーザ発生部 19 プローブレーザ発生部 20 ポンプレーザ 21 プローブレーザ 22 サーマルウェーブシグナル検出器 23 ポンプレーザ強度の時間変化概念図 24 プローブレーザ強度の時間変化概念図 25 サーマルウェーブシグナルによる反射率の検出概
念図 26 サンプル 27 半導体試料 28 電子 29 正孔
REFERENCE SIGNS LIST 1 chip 2 package 3 sample table 4 microscope section 5 laser scanning section 6 laser generation section 7 signal processing / image processing / system control section 8 fluctuating current detection / amplification section 9 voltage supply source 10 temperature control section 11 optical transmission path 12 heat medium Pipe 13 Current transmission path (power supply line) 14, 31 Signal line 15 CRT 16 LSI tester 17 Laser 18 Pump laser generator 19 Probe laser generator 20 Pump laser 21 Probe laser 22 Thermal wave signal detector 23 Time of pump laser intensity Conceptual diagram of change 24 Conceptual diagram of temporal change in probe laser intensity 25 Conceptual diagram of reflectance detection by thermal wave signal 26 Sample 27 Semiconductor sample 28 Electron 29 Hole

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】半導体集積回路の内部相互配線に電流を流
した状態で、半導体集積回路にレーザビームを走査しな
がら照射加熱し、照射による温度上昇に起因する配線抵
抗の増大によって生じる前記内部相互配線に流れる電流
の変化を検知し、欠陥のある箇所では熱伝導が悪化し前
記配線の抵抗が欠陥がないところより増大することによ
り電流変化が大きくなることで前記内部相互配線の欠陥
を検出することを特徴とする半導体集積回路内部相互配
線の検査方法。
1. A semiconductor integrated circuit is irradiated and heated while scanning a laser beam in a state where a current is applied to internal interconnections of the semiconductor integrated circuit, and the internal interconnection caused by an increase in wiring resistance caused by a temperature rise due to the irradiation. A change in the current flowing in the wiring is detected, and a defect in the internal interconnection is detected by increasing the current change by increasing the resistance of the wiring from a defect-free area where the heat conduction is deteriorated and increasing the resistance of the wiring. A method for inspecting interconnections inside a semiconductor integrated circuit, comprising:
【請求項2】前記電流変化を、輝度の情報に変換して画
像表示し、前記電流変化の検知を画像上で行うことを特
徴とする請求項1記載の半導体集積回路内部相互配線の
検査方法。
2. The method according to claim 1, wherein the current change is converted into luminance information and displayed as an image, and the current change is detected on the image. .
【請求項3】前記電流変化の検知を行う際に、外部から
前記半導体集積回路の温度制御を行うことで変化前の電
流をできる限り小さくすることにより、前記電流変化の
検出の感度を向上させることを特徴とする請求項1また
は2記載の半導体集積回路内部相互配線の検査方法。
3. The sensitivity of the current change detection is improved by minimizing the current before the change by externally controlling the temperature of the semiconductor integrated circuit when detecting the current change. 3. The method according to claim 1, wherein the interconnects in the semiconductor integrated circuit are inspected.
【請求項4】前記レーザビームの代わりに電子ビームま
たはイオンビームを用いることを特徴とする請求項1,
2または3記載の半導体集積回路内部相互配線の検査方
法。
4. The method according to claim 1, wherein an electron beam or an ion beam is used instead of the laser beam.
4. The method for inspecting interconnections inside a semiconductor integrated circuit according to 2 or 3.
【請求項5】半導体集積回路の内部相互配線に電流を供
給する手段と、前記半導体集積回路にレーザビームを走
査しながら照射加熱するレーザビーム照射加熱手段と、
照射による温度上昇に起因する配線抵抗の増大によって
生じる前記内部相互配線に流れる電流の変化を検知し、
欠陥のある箇所では熱伝導が悪化し前記配線の抵抗が欠
陥のないところより増大することにより電流変化がより
大きくなることで前記内部相互配線の欠陥を検出する手
段と、を備えることを特徴とする半導体集積回路内部相
互配線の検査装置。
5. A means for supplying a current to internal interconnections of a semiconductor integrated circuit, a laser beam irradiation heating means for irradiating and heating the semiconductor integrated circuit while scanning a laser beam,
Detecting a change in current flowing through the internal interconnection caused by an increase in wiring resistance due to a temperature rise due to irradiation;
Means for detecting a defect in the internal interconnection by increasing the current change by increasing the resistance of the wiring and increasing the resistance of the wiring in a defective part and the resistance of the wiring as compared with the part without the defect. Inspection system for interconnects inside semiconductor integrated circuits.
【請求項6】前記電流変化を輝度の情報に変換して画像
表示し、前記電流変化の検知を画像上で行う手段とを備
えることを特徴とする請求項5記載の半導体集積回路内
部相互配線の検査装置。
6. The interconnection according to claim 5, further comprising means for converting the current change into luminance information, displaying an image, and detecting the current change on an image. Inspection equipment.
【請求項7】前記半導体集積回路の温度制御を行う手段
をさらに備えることを特徴とする請求項5または6記載
の半導体集積回路内部相互配線の検査装置。
7. The apparatus according to claim 5, further comprising means for controlling the temperature of said semiconductor integrated circuit.
【請求項8】前記レーザビーム照射加熱手段の代わり
に、電子ビームまたはイオンビーム照射加熱手段を用い
ることを特徴とする請求項5、6または7記載の半導体
集積回路内部相互配線の検査装置。
8. The inspection apparatus according to claim 5, wherein an electron beam or ion beam irradiation heating means is used in place of said laser beam irradiation heating means.
【請求項9】前記電流を供給する手段が電圧供給源ある
いはLSIテスタであることを特徴とする請求項5、
6、7または8記載の半導体集積回路内部相互配線の検
査装置。
9. The device according to claim 5, wherein said means for supplying a current is a voltage supply source or an LSI tester.
9. The inspection apparatus for interconnects inside a semiconductor integrated circuit according to 6, 7, or 8.
JP9290734A 1997-10-23 1997-10-23 Method and device for inspecting internal mutual wiring in semiconductor integrated circuit Pending JPH10170612A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9290734A JPH10170612A (en) 1997-10-23 1997-10-23 Method and device for inspecting internal mutual wiring in semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9290734A JPH10170612A (en) 1997-10-23 1997-10-23 Method and device for inspecting internal mutual wiring in semiconductor integrated circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP5085817A Division JP2765427B2 (en) 1993-04-13 1993-04-13 Method and apparatus for inspecting interconnections inside semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH10170612A true JPH10170612A (en) 1998-06-26

Family

ID=17759838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9290734A Pending JPH10170612A (en) 1997-10-23 1997-10-23 Method and device for inspecting internal mutual wiring in semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH10170612A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444895B1 (en) 1998-09-28 2002-09-03 Nec Corporation Device and method for nondestructive inspection on semiconductor device
TWI578366B (en) * 2008-12-19 2017-04-11 漢民微測科技股份有限公司 Method and system for identifying defects on substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444895B1 (en) 1998-09-28 2002-09-03 Nec Corporation Device and method for nondestructive inspection on semiconductor device
US6610918B2 (en) 1998-09-28 2003-08-26 Nec Electronics Corporation Device and method for nondestructive inspection on semiconductor device
US6759259B2 (en) 1998-09-28 2004-07-06 Nec Electronics Corporation Device and method for nondestructive inspection on semiconductor device
TWI578366B (en) * 2008-12-19 2017-04-11 漢民微測科技股份有限公司 Method and system for identifying defects on substrate

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