JPH10164062A - Fault monitoring method for arithmetic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily use a method in common to polishing and shaping without depending on algorithm with a small hardware scale by using an OH generation cell which is periodically generated at the time of converting an ATM cell format into a format in a device from the format of a transmission line. SOLUTION: Parameters for monitoring OH(overhead) generation cell are previously set for respective memories 42-45 and 401. A header detection part 40 identifies the cells. In the case of the OH generation cell, an OH generation cell period monitoring part 400 monitors an arriving period. When it is a regulated period, the parameters for OH generation cell are sequentially read from the respective memories 42-45 and 401 and the fault is monitored. When a polishing operation is executed and the cell is judged to be illegal in a conformity test and when a cell interval after shaping is not similar to that of the cell, it is judged that abnormality occurs in the arithmetic circuit. Thus, the increase of a circuit scale is small and miniaturization can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a usage parameter control (UPC: User Parameter Control) apparatus and network parameter control between networks.
The present invention relates to a fault monitoring method for a policing / shaping arithmetic circuit that performs an arithmetic operation in a traffic shaping device.

[0002] Asynchronous transfer mode (ATM: Asynchronous transfer mode) in which information to be communicated is divided into fixed-length cell units and transferred.
Transfer Mode) In traffic control performed in a network, in particular, by detecting a violation of a traffic amount with respect to a negotiated parameter, and performing an appropriate measure, a QOS (Quality of Security) of another connection is determined.
rvice) to protect users and networks from interference by malicious users, etc. (UPC: User Parameter Control) and inter-network usage parameter control (Network Parame
ter Control) is performed by an arithmetic circuit in a UPC device or an NPC device. In addition, a traffic shaping operation for reducing cell delay fluctuation (CDV: Cell Delay Variation) occurring in the ATM device and shaping traffic characteristics into a desired shape is performed in the shaping device (shaper). The present invention relates to a fault monitoring method for such a polishing / shaping operation circuit.

[0003]

2. Description of the Related Art The role of a UPC device / shaper In ATM communication, a user declares a transfer amount of information to a network side, and the network side performs a housing design and gives an allocation permission to the user (contract). If a certain user transfers information in excess of the contracted amount, there is a possibility that other users will be affected, such as cell loss. For this reason,
UPC device (or NPC device) at the entrance of the network
To monitor the flow rate of information flowed by the user, and if there is a violation, discard the information. UPC (or NPC)
Is also called policing because it has the above functions.

However, in order to avoid that information is discarded in the UPC device due to cell delay fluctuation (CDV) generated in the user device or the like, despite the fact that the user complies with the contracted amount, a certain amount of information is discarded. Violations are passed. For this reason, a shaper is arranged after the UPC device to reduce cell delay fluctuation (CDV).

[0005] Regarding the UPC device The UPC device monitors whether the traffic characteristics of the cell flow transmitted from the user of the ATM service comply with the parameters contracted with the user, and controls the cell flow as necessary. For example, disposal processing is performed on cells that violate the contract. Violation is determined using a virtual scheduling algorithm, a leaky bucket algorithm, or an equivalent algorithm.

FIG. 2 shows an example of a policing algorithm (virtual scheduling algorithm). In FIG. 2, the minimum cell interval T and the allowable CDV value τ are parameters set as a result of the negotiation. The theoretical cell arrival time TAT and the cell arrival time ta are parameters for calculation.

In the cell flow defined by the cell interval T, cells usually arrive at T intervals. Therefore, based on the cell arriving at the time ta, the next time the cell arrives is theoretically defined by (ta + T). The time of the cell to arrive is called a theoretical cell arrival time TAT.

The theoretical cell arrival time TAT is compared with the cell arrival time ta (step S2). If the time ta at which the cell actually arrives arrives later than the theoretically specified time (YES in step S2), it is determined that the cell is a conforming cell, and the TAT is changed to the current time (step S3). ), The TAT is updated (step S4).

If the actual arrival time ta of the cell arrives earlier than the theoretically specified time (NO in step S2), it means that the cell violates the contract, but immediately Does not judge that the user is a nonconforming cell that has violated the contract, and determines the difference between the theoretical cell arrival time TAT and the cell arrival time ta (TAT-ta: indicates how much the arriving cell violates the contract). And the CDV allowable value τ is compared to determine a match / mismatch (step S5).

If the difference (TAT-ta) is larger than the CDV allowable value τ (YES in step S5), the cell is determined to be a nonconforming cell and discard processing is performed (step S6). On the other hand, if the difference (TAT-ta) is equal to or smaller than the CDV allowable value τ (NO in step S5), it is determined that the cell violates the contract but conforms to the allowable range and updates the TAT (step S4).

Shaper The shaper has a function of reducing cell delay fluctuation (CDV) including cell flow. The cell that has violated the contract due to cell delay fluctuation (CDV) is buffered and the cell is output at a desired time. The cell output time Tout is determined using a virtual scheduling algorithm, a leaky bucket algorithm, or an equivalent algorithm. When the cell output time Tout competes with another cell, output competition control based on FIFO is performed.
Output without reversing the order of cells in the same connection.

FIG. 3 shows an example of a shaping algorithm (virtual scheduling algorithm).
In FIG. 3, the minimum cell interval T and the CDV residual value τ are parameters set as a result of the negotiation. The theoretical cell transmission time TET, cell output time Tout, and cell arrival time ta are parameters for calculation.

In a cell flow defined by a cell interval T, cells usually arrive at T intervals. Thus, based on the cell arriving at time ta, the next time the cell should arrive is
It is theoretically defined by (ta + T). The time of the cell to arrive is called a theoretical cell arrival time TAT. Since the shaper basically controls output at that time,
In particular, it is also called the theoretical cell transmission time TET.

The theoretical cell transmission time TET is compared with the cell arrival time ta (step S12). The time ta when the cell actually arrives is the TET at the time theoretically defined.
If the vehicle arrives later (YES in step S12),
After determining that the cell is a conforming cell and changing the theoretical cell transmission time TET to the current time ta (step S13), the theoretical cell transmission time TET is updated (step S17). The cell is output at the current time (step S14).

If the actual arrival time ta of the cell arrives earlier than the theoretically specified time (NO in step S12), it means that the cell violates the contract, but immediately Does not judge that the user is a nonconforming cell that has violated the contract, and determines the difference between the theoretical cell transmission time TET and the cell arrival time ta (TET-ta: indicates how much the arriving cell violates the contract). And the CDV residual value τ
Is determined by comparing the magnitude relations (step S15).

If the difference (TET-ta) is larger than the CDV residual value τ (YES in step S15), the cell is determined to be a non-conforming cell, shaping is performed, and the cell is output at the time of (TET-T) (step S16). ), Difference (TET-ta)
Is equal to or smaller than the CDV residual value τ (N in step S15).
O) The cell violates the contract but is output at the current time as a conformable cell within the allowable range (step S14), and updates the theoretical cell transmission time TET (step S17).

FIG. 4 shows an example of an algorithm of the UPC / shaper device.
FIG. 4 shows an embodiment in which a VSA (virtual scheduling algorithm) is used as a traffic monitoring method in a UPC (NPC) device and an output time calculation method in traffic shaping.

In FIG. 4, a minimum cell interval T (UPC,
CDV allowable value τ _u , CDV residual value τ _S
Is a parameter set as a result of the negotiation. Theoretical cell arrival time TAT, cell output time Tout,
The cell arrival time ta is a parameter for calculation. UPC
A feature of the present algorithm is that the minimum cell interval T used in the device and the minimum cell interval T used in the shaper are expressed by a common parameter, and the CDV is reduced immediately after the violation is determined.

In the cell flow defined by the cell interval T, cells usually arrive at T intervals. Therefore, based on the cell arriving at the time ta, the time when the cell should arrive next is theoretically defined by ta + T. The time of the cell to arrive is called a theoretical cell arrival time TAT.

The theoretical cell arrival time TAT is compared with the cell arrival time ta (step S22). If the actual arrival time ta of the cell arrives later than the theoretically specified time (YES in step S22), it is determined that the cell is a conforming cell, and the theoretical cell arrival time TAT is set to the current time t.
After changing to a (step S23), the theoretical cell arrival time TAT is updated (step S25). The cell is output at the current time (step S24).

If the actual arrival time ta of the cell arrives earlier than the theoretically specified time (NO in step S22), it means that the cell violates the contract, but immediately Does not judge that the user is a nonconforming cell that has violated the contract, and determines the difference between the theoretical cell arrival time TAT and the cell arrival time ta (TAT-ta: indicates how much the arriving cell violates the contract). And the CDV tolerance τ
Comparing / non-conforming is determined by comparing the magnitude relationship of _u (step S26).

If the difference (TAT-ta) is larger than the allowable CDV value τ _u (YES in step S26), the cell is determined to be a non-conforming cell and discard processing is performed (step S3).
0). On the other hand, if the difference (TAT-ta) is equal to or smaller than the CDV allowable value τ _u (NO in step S26), the contract is violated but is not discarded as a conformable cell within the allowable range, and shaping (reducing CDV) is performed. Do.

In shaping, the difference (TAT)
−ta) is compared with the CDV residual value τ _S (step S).
27). If the difference (TAT-ta) is larger than the CDV residual value τ _S (YES in step S27, [(TA
T−ta) −τ _S ], and reduce the CDV by the time (T
AT-τ _S ), the cell is output (step S28). If the difference (TAT-ta) is equal to or smaller than the CDV residual value τ _S (NO in step S27), the cell is output at the current time ta (step S29). ), And updates the theoretical cell arrival time TAT (step S25).

FIG. 5 shows a circuit example of the UPC / shaper device. This device can be operated as a single UPC or a single shaper by hardware or software control. The device configuration includes a cell detection device 3, storage devices 6 and 7 for storing traffic parameters and calculation parameters, a calculation device 4 for determining a violation and calculating an output time, a storage device 1 for writing cell data, and a memory control. It comprises a device 5, a memory control storage device 8, and an output control device 2.

Here, the cell detecting section 3 reads out the control data described in the header of the arriving cell. The parameter storage 6 stores traffic parameters, and the operation storage 7 stores operation parameters.
The calculation unit 4 performs a violation determination and calculates the output time of the cell. The cell data storage 1 writes the input cell data. The memory control unit 5 stores the address of the cell data written in the storage device 1 for cell data storage into the arithmetic unit 4
It manages based on the output time input from. The memory device 8 for the memory control device manages the address of the cell data.
The output control unit 2 reads and outputs the data of the corresponding cell from the cell data storage device 1 at the output time of the cell.

The storage devices 6 and 7 store parameters for each cell type. When a cell arrives, the cell detector 3 reads the control data described in the header of the cell and identifies the cell type. The computing unit 4 determines violations and calculates the output time Tout according to the above algorithm for each cell type while accessing the storage devices 6 and 7 as necessary. The memory control unit 5 manages the address of the cell data written in the cell data storage device 1 based on the output time Tout input from the operation unit 4. The memory control storage device 8 stores data necessary for managing the address of the cell data. At the output time Tout of the cell, the output control unit 2 reads and outputs the data of the cell from the storage device 1 for storing cell data.

Example of Violation Monitoring Circuit of UPC / Shaper Apparatus FIG. 6 shows an example of a circuit for monitoring a violation in the arithmetic unit 4 of the UPC / shaper apparatus. This circuit performs violation monitoring according to the algorithm shown in FIG. In FIG. 6, reference numeral 40 denotes a header detector for transmitting the sender information, and reference numeral 41 denotes a time counter for counting the cell arrival time. 42
45 are memories, a memory 42 stores a theoretical cell arrival time TAT, a memory 43 stores a CDV allowable value τ _u , a memory 44 stores a CDV residual value τ _S , and a memory 45 stores a minimum cell The interval T is stored. An adder 47 updates the theoretical cell arrival time TAT stored in the memory 42 by adding the minimum cell interval T stored in the memory 45 thereto. Reference numeral 46 denotes a differentiator which outputs (TAT-ta)
) And output it. 48 is a comparator, (TAT
−ta) is compared with τ _u to perform UPC determination and UPC failure detection. 49 is a comparator, which is (TAT-ta) and τ _S
Are compared to make a SHPR (shaper) determination.

The operation of this circuit will be described below. The header detector 40 extracts header information such as VPI and VCI of the connection. Based on the value, the theoretical cell arrival time TAT is read and stored in the memory 42. Similarly, the CDV allowable value τ _u , the CDV residual value τ _S , and the minimum cell interval T are read and stored in the memories 43, 4, respectively.
4, 45.

The time counter 41 is a time counter that counts up every cell time, and its output is the current time ta. Next, the current time ta
By calculating the difference between the theoretical cell arrival time TAT and the theoretical cell arrival time TAT, it is possible to determine how earlier or later the arriving cell arrives from the theoretically stipulated time of the cell to arrive.

Next, the CDV allowable value τ _{u of the} connection concerned
Is read from the memory 43. This CDV allowable value τ _u
Is compared with the time interval (TAT-ta), and the UPC violation is determined. If (TAT-ta) is larger than the CDV allowable value τ _u , the cell is determined to be a non-conforming cell and discard processing is performed. When (TAT-ta) is equal to or smaller than the CDV allowable value τ _u , shaping (reducing CDV) is performed without violating the contract but discarding as a conformable cell within the allowable range.

Next, the CDV residual value τ _{S of the} connection concerned
Is read from the memory 44. Shaping is performed by comparing (TAT-ta) obtained by the above calculation with the CDV residual value τ _S. If (TAT-ta) is greater than the CDV residual value tau _S is to reduce [(TAT-ta) -τ _S] amount corresponding cell delay variation (CDV), time (TAT
−τ _S ), and outputs the cell at the current time ta when (TAT−ta) is equal to or smaller than the CDV residual value τ _S.

Next, the minimum cell interval T of the connection concerned is read from the memory 45, and added to the theoretical cell arrival time TAT previously read from the memory 42 by the adder 47 to update its value. Cell arrival time TAT
Is stored in the memory 42 again.

[0033]

When a failure occurs in the above-mentioned policing operation circuit, there is a possibility that a user who is not violated will be discarded, thereby causing much trouble to the user. For this reason, the UPC / NPC calculation unit monitors the failure, and when a failure is detected, a failure alarm is notified to the OPS (Operation System).

Further, in order to avoid inconvenience to the user and the network due to the failure of the shaping arithmetic circuit, the failure is monitored by the shaping arithmetic.
When a failure is detected, a failure alarm is notified to the OPS.

By the way, before the coming of the full-scale multimedia era, there is a demand for miniaturization of ATM-related devices. Therefore, the fault monitoring method of the arithmetic circuit
It is necessary to devise a method that has as small a hardware scale as possible, is simple, and can be monitored regardless of a policing algorithm such as a leaky bucket algorithm (LBA) and a virtual scheduling algorithm (VSA). In particular, when the policing function and the shaping function are realized by one device (LSI), further simplification is attempted due to restrictions on the circuit scale, etc., and a monitoring method that can be used commonly for policing and shaping is devised. There is a need to.

For example, a method is conceivable in which the hardware of the operation unit is duplicated and the result is compared to detect the presence / absence of an operation failure. However, this method increases the hardware scale and becomes redundant.

Also, known data (parameters for the operation unit to perform the operation) whose operation results are known are prepared in advance, the known data is set in the operation unit, and the known data is operated. A method of comparing the operation result with a previously known result can be considered.
It is difficult to determine when, what data, and how often it is effective. When actually performing fault detection by this method, a large number of parameters (data)
It is thought that it is necessary to perform the operation based on the data selected at random, and the faults that can be detected are necessarily limited.

Further, there is a possibility that the hardware scale of the failure detection circuit is large and complicated as compared with the arithmetic circuit. For example, FIG. 7 shows an example of an apparatus configuration in the case of performing fault monitoring by the above method. When performing the fault monitoring by the above method, in addition to the device configuration described in the related art, a storage device 10 that stores a plurality of known data for fault monitoring, and a plurality of fault monitoring stored in the storage device 10 based on fault detection timing. A failure monitoring control unit 9 for randomly reading a set of data from known data for use and a failure determination unit 11 for comparing the result calculated with the read parameters with the known data to determine a violation are required. Becomes very large. In particular, the storage device 10 that needs to store a large amount of data requires a large storage capacity. For the data for failure monitoring, it is necessary to consider what value should be used and how much data should be prepared.

Further, it is considered that the failure monitoring control becomes very complicated. It is also necessary to pay attention to the timing of performing failure detection. That is, when performing this failure determination, the operating system must be temporarily stopped for failure determination. Considering the above, it can be said that there is no merit to adopt this failure monitoring method.

The present invention has been made in view of the above problems, and is simple, has a small hardware scale, is independent of an algorithm, and is capable of being used commonly for policing and shaping. It is to provide a monitoring method.

[0041]

In order to solve the above-mentioned problems, according to the present invention, traffic control is performed in an asynchronous transfer mode network in which information to be communicated is divided into fixed length cells and transferred. In this case, a traffic parameter violation for the negotiated parameter is detected, and a failure of the calculation unit of the usage parameter controller or the inter-network usage parameter controller that performs processing such as discarding the violating cell is periodically generated. A policing operation is performed on the OH-generating cell to be performed with a monitoring parameter having a cycle corresponding to the cycle of the OH-generating cell.

In the present invention, as another form,
When performing traffic control in an asynchronous communication mode network in which information to be communicated is divided into fixed-length cell units and transferred, a failure in the arithmetic unit of the shaper that reduces cell delay fluctuations and shapes traffic characteristics to a desired shape To
Compare the input and output cell intervals of the OH-generating cell input to the shaper with respect to the periodically generated OH-generating cell, and when they differ, detect by detecting that some abnormality has occurred in the shaping calculation unit. A method for monitoring a failure of an arithmetic circuit is provided.

The fault monitoring method described above detects a fault in the calculation unit by calculating a fault monitoring cell that is periodically generated with a different definition other than the OH generating cell, instead of the OH generating cell. It may be.

In the fault monitoring method of the present invention, the AT
The failure monitoring of the operation unit is performed by using the OH generation cell generated when the M cell format is converted from the format of the transmission line to the format in the device. Since the OH generation cell is basically input to the UPC at a constant period, for example, if a policing operation is performed using monitoring parameters of the same period, it is not determined that a violation occurs in the conformity test. If it is determined that the violation has occurred, it can be determined that some abnormality has occurred in the arithmetic unit. Alternatively, by performing a policing operation with a monitoring parameter having a period slightly longer than the period of the OH generation cell, it is possible to determine that some abnormality has occurred in the operation unit when it is determined that the operation is appropriate in the adaptation test.

If a cell flow of a fixed period that does not violate the shaper is input, and if the cell interval after shaping is not the same as the input cell interval, it is determined that some abnormality has occurred in the arithmetic unit. it can.

By using this method, even if the user does not violate, the violation is determined by the policing, and the normal cell is discarded, or the trouble of the shaper unit causes much trouble to the user. Can be avoided.

[0047]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. The circuit of this embodiment is provided in an arithmetic unit in the UPC / shaper device of FIG. In FIG. 1, circuits having the same reference numerals as those of the fault monitoring circuit described in the conventional example of FIG. 6 are circuits having the same configuration. That is, the header detector 40, the time counter 41,
Memories 42 to 45, differentiator 46, adder 47, comparator 4
8 and 49 are the same circuits. As different points, a start unit 400 for monitoring the cycle of the OH generation cells, a memory 401 for storing the previous cell transmission time (previous Tout), a differentiator 402 for obtaining a difference between the theoretical cell arrival time TAT and the previous Tout,
A comparator 403 for comparing the difference (TAT-previous Tout) from the differentiator 402 with the minimum cell interval T is added.

The circuit of this embodiment monitors the failure of the arithmetic unit using an OH generation cell (overhead generation cell) generated when the ATM cell format is converted from the format of the transmission line to the format in the device. It is. That is, since the cell format of 53 bytes on the transmission line is converted and processed in the cell format of 54 bits in the ATM exchange, an OH generation cell for correcting this difference is generated at a constant period. .

Since the OH-generating cell is basically input to the UPC at a constant period, if a policing operation is performed using monitoring parameters of the same period, no violation is determined in the conformity test. If it is determined that the violation has occurred, it can be determined that some abnormality has occurred in the arithmetic unit.
In addition, when a cell flow of a fixed period that does not violate the shaper (that is, an OH generation cell) is input, and if the cell interval after shaping is not the same as the input cell interval, some abnormality has occurred in the arithmetic unit. Can be determined.

In FIG. 1, each of the memories 42, 43, 4
OH cell monitoring parameters (that is, TAT, τ _u , τ _S , and previous T out) are set in advance in 4, 45, and 401, respectively. Since the setting parameters are monitored in the same cycle as the OH generation cell, a specified OH generation cell is set for the minimum cell interval T, and the CDV allowable value τ _u , CDV residual value τ _S , theoretical cell arrival time TAT 0 is set for the previous cell transmission time Tout.

The header detection unit 40 extracts the header information (information on the cell type, etc.) of the connection and identifies the cell. If the cell type is an OH-generated cell, the OH-generated cell cycle monitoring unit 400 monitors the arrival cycle, and if it is a specified cycle, performs fault monitoring. No fault monitoring is performed because the cycle is incorrect.

The theoretical cell arrival time TAT is read based on the header information such as the VPI and VCI of the connection extracted by the header detection unit 40. Time counter 4
Reference numeral 1 denotes a time counter that counts up every cell time, and its output is the current time ta. Next, the difference between the current time ta of the time counter 41 and the theoretical cell arrival time TAT of the memory 42 is calculated by the differentiator 46, so that the arriving cell can be calculated from the theoretically stipulated arrival time of the cell. You can ask how early or how late you arrive.

Next, the CDV allowable value τ _{u of the} connection concerned
Is read from the memory 43. This CDV allowable value τ _u
And the time interval (TAT-ta) are compared by a comparator 48, and U
The violation of the PC is determined. The time interval (TAT-ta) is C
If the value is larger than the DV allowable value τ _u , the cell is a nonconforming cell. However, if the OH generation cell is monitored, it is monitored at the same cycle as the OH generation cell cycle. It is not determined to be non-conforming. When it is determined that there is no conformity, it can be determined that some abnormality has occurred in the UPC calculation unit. However, at this time, the OH generation cell is passed without being discarded. If the time interval (TAT-ta) is equal to or less than the CDV allowable value τ _u , shaping (CDV deletion) is performed without violating the contract but discarding as a conformable cell within the allowable range.

Next, the CDV residual value τ _{S of the} connection concerned
Is read from the memory 44. The shaping is performed by comparing the time interval (TAT-ta) calculated in advance with the CDV residual value τ _S by the comparator 49. Time interval (TAT
−ta) is greater than the CDV residual value τ _S ,
[(TAT-ta) -τ _S] amount corresponding cell delay variation (C
By reducing the DV), and it outputs the cell to the time (TAT-τ _S), the time interval (TAT-ta) is in the following cases: CDV residual value tau _S outputs the cell to the current time ta.

Next, Tout before the relevant connection is read from the memory 401, and subtraction from the theoretical cell arrival time TAT read from the memory 42 is performed by the differentiator 402. At this time, since the difference (TAT-Tout before) always becomes T, the minimum cell interval T read from the memory 45 is compared with the comparator 403. If the difference is not equal, there is some abnormality in the shaper calculation unit. Can be determined.

Next, the minimum cell interval T of the connection
Is read from the memory 45, and is added to the theoretical cell arrival time TAT previously read from the memory 42.
2 to update the value of the theoretical cell arrival time TAT.

In practicing the present invention, various modifications other than those described above are possible. For example, by configuring the device so that the parameters for monitoring the OH-generated cells can be set in the memory, the present invention can be applied to devices having different OH cell generation periods. Even if the cell is a cell of another definition other than the OH-generating cell, if the cell is periodically input, it is possible to detect a failure of the arithmetic unit by causing the cell to operate.

In the above-described embodiment, the policing operation is performed with the monitoring parameter having the same period as the period of the OH-generating cell, and if a violation is determined in the conformity test, it is assumed that some abnormality has occurred in the operation unit. However, the present invention is not limited to this. For example, a policing operation is performed using a monitoring parameter having a period slightly longer than the period of the OH generation cell, and if the conformity test determines that the policing operation is appropriate, some abnormality occurs in the operation unit. May be generated.

The parameters for monitoring the OH-generated cells are set in various forms, such as: setting in the internal memory of the LSI, setting in the external memory of the LSI, and holding a fixed value inside the LSI. be able to.

[0060]

As described above, according to the present invention, the fault monitoring of the polishing operation circuit or the shaping operation circuit is performed by using the periodically generated OH generation cells. The effect can be achieved.

It is only necessary to extract a failure monitoring cell that is periodically input and calculate the cell by a normal calculation method, which can be easily realized.

In terms of circuit, the existing arithmetic circuit includes an OH generation cell cycle monitoring unit, a memory device before Tout, a TAT-T
out Subtraction circuit, TAT-can be realized only by adding a comparison circuit between Tout and Tout before, otherwise it can be realized by using the existing circuit as it is, and there is little increase in circuit scale and downsizing by this fault monitoring method It is.

The monitoring can be performed by the same method regardless of the algorithm such as the virtual scheduling method and the leaky bucket method.

The method can be used commonly for the start of the failure of the policing and the shaping, and this method can be applied when the policing function or the shaping function is realized by separate LSIs or when the same LSI is used.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a violation monitoring circuit that performs a method of monitoring a failure of an arithmetic circuit according to one embodiment of the present invention;

FIG. 2 is a flowchart illustrating an example of a UPC algorithm.

FIG. 3 is a flowchart illustrating an example of a shaping algorithm.

FIG. 4 is a flowchart illustrating an example in which the present invention is applied to a virtual scheduling algorithm (VSA).

FIG. 5 is a diagram illustrating a configuration example of a UPC / shaper device.

6 is a diagram illustrating a configuration example of a failure monitoring circuit (shaper type UPC circuit) in a calculation unit in the apparatus in FIG. 5;

FIG. 7 is a diagram illustrating a configuration example of a UPC / shaper device when a failure monitoring circuit is added.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Storage device for cell data storage 2 Output control unit 3 Cell detection unit 4 Operation unit 5 Memory control unit 6 Parameter storage storage device 7 Operation storage device 8 Memory control storage device 9 Failure monitoring control unit 10 Failure monitoring data storage Apparatus 11 Failure determination unit 40 Header detection unit 41 Time counter 42 to 45, 401 Memory 46, 402 Difference unit 47 Adder 48, 49, 403 Comparator 400 OH generation cell cycle monitoring unit

──────────────────────────────────────────────────の Continuation of the front page (51) Int.Cl. ⁶ Identification symbol FI H04Q 3/00 (72) Inventor Toshinori Koyanagi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Koji Nishikawa 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Ryoichi Iwase 3-192-2 Nishishinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (3)

[Claims] When performing traffic control in an asynchronous transfer mode network in which information to be communicated is divided into fixed-length cell units and transferred, a violation of a traffic amount with respect to a negotiated parameter is detected, and a violation cell is detected. On the other hand, a failure of the operation unit of the usage parameter control device or the inter-network usage parameter control device that performs a process such as discarding is performed in accordance with the cycle of the OH generation cell with respect to the periodically generated OH generation cell. A fault monitoring method for an arithmetic circuit that performs a policing operation with the above monitoring parameters and detects the policing operation based on the determination result of the compliance test. 2. A shaper for reducing cell delay fluctuations and shaping traffic characteristics into a desired shape when performing traffic control in an asynchronous communication mode network in which information to be communicated is divided into fixed length cell units and transferred. If the failure of the arithmetic unit is compared with the periodically generated OH-generating cell and the input and output cell intervals of the OH-generating cell input to the shaper are compared and different, some abnormality occurs in the shaping arithmetic unit. A method for monitoring a failure of an arithmetic circuit that is detected by using 3. The method according to claim 1, wherein a fault monitoring cell, which is periodically generated by another definition other than the OH generating cell, is calculated in place of the OH generating cell, thereby detecting a fault in the calculating unit. Item 3. The failure monitoring method for an arithmetic circuit according to item 1 or 2.