JPH10163830A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the variance of delay time due to the variance of power voltage by adding plural continuous resistances and an output inverter to an input inverter and connecting a delay time correction circuit in parallel to the resistances according to the power potential. SOLUTION: This semiconductor integrated circuit includes a delay time correction circuit that consists of a delay circuit 1', a delay detection circuit 30 and a resistance value correction circuit 40. The input signal IN of the circuit 1' is turned into a delay output signal OUT via an inverter 13, the resistances R1 and R2 , and an inverter 14. The input node N of the inverter 14 is grounded via a capacitor C. The circuit 30 consists of a delay circuit 1 which outputs an output signal OUT1 and a double input EX-OR circuit 22 where the signals IN and OUT1 are inputted and is connected to the circuit 1' via the circuit 40. The circuit 40 is connected in parallel to the resistance R2 of the circuit 1' to serve as a transfer gate against the circuit 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a delay time correction circuit for suppressing a variation in delay time of a delay circuit.

[0002]

2. Description of the Related Art Circuits having various functions are incorporated in a semiconductor integrated circuit. Among them, there is a delay circuit for giving a predetermined delay to an input signal.

FIG. 6 is a circuit diagram of a conventional delay circuit, and FIG. 7 is a timing chart of the delay circuit of FIG.

The circuit configuration of the delay circuit 1 is as follows. That is, the first inverter 10 to which the input signal IN is input, the resistor R having one end connected to the node A on the output side of the first inverter 10, and the node R between the other end of the resistor R and the ground. Capacitor C, and node B on the input side
And the second inverter 11 from which the output signal OUT is output from the output side, constitutes the delay circuit 1.

The signal A at the node A on the output side of the first inverter 10 to which the input signal IN is input is input to the second inverter 11 via the resistor R and the capacitor C. The potential at node B changes according to signal A at node A and the CR time constant. Also, delay circuit 1
The output signal OUT changes in accordance with the magnitude relationship obtained by comparing the potential of the node B with the circuit threshold value Vthc of the second inverter 11. The circuit threshold Vthc is usually set to の of the power supply potential of the integrated circuit. As shown in the timing chart of FIG. 7, the input signal IN of the delay circuit 1 and the output signal OU
A delay time t1 corresponding to the resistance R, the capacitor C, and the on-resistance of the first inverter 10 occurs between T and T.

FIG. 8 is a circuit configuration diagram of a quadruple circuit using the delay circuit 1 of FIG. 6, and FIG. 9 is a timing chart at the time of normal operation of the quadruple circuit of FIG.

The configuration of the quadruple circuit 2 is as follows. That is, the first delay circuit 1 to which the input signal IN is input
A second and a third delay circuit in which the same delay circuit as the first delay circuit 1 is sequentially connected in cascade to the first delay circuit 1;
Input signal IN and output signal OU from first delay circuit 1
A first two-input EX-OR (E
XCLUSIVE OR) circuit 20, a second two-input EX-OR circuit 21 to which output signals OUT2 and OUT3 from the second and third delay circuits are input, respectively,
And a two-input NOR circuit 30 to which the output signals a and b of the second two-input EX-OR circuits 20 and 21 are input, respectively.
And the inverter 12 connected in cascade to the output side of the two-input NOR circuit 30 and outputting the output signal OUT.
The multiplication circuit 2 is configured.

If the resistance R, the capacitor C, and the on-resistance of the first inverter 10 that constitute the first, second, and third delay circuits 1 are all equal, the delay time of the output signal OUT1 with respect to the input signal IN, Output signal O
The delay time of the output signal OUT2 with respect to the UT1 and the delay time of the output signal OUT3 with respect to the output signal OUT2 are all equal. In the timing chart of FIG.
The case where the delay time of each delay circuit 1 is equal and the delay time per stage is t1 is shown. And the input signal I
N, and an output signal a generated from the output signal OUT1 through the first two-input EX-OR circuit 20, and an output signal OU.
From T2 and OUT3, a second two-input EX-OR circuit 21
, An output signal OUT having a frequency four times the frequency of the input signal IN is generated through the two-input NOR circuit 30 and the inverter 12.

[0009]

However, a circuit using the conventional delay circuit 1, for example, the above-mentioned quadruple circuit 2, has the following problems.

[0010] Even if the values of the resistor R and the capacitor C are constant, if the ON resistance of the first inverter 10 constituting the delay circuit 1 increases due to a drop in the power supply voltage or the like,
The delay time per stage of the delay circuit 1 increases.

FIG. 10 is a timing chart when the delay time of each delay circuit 1 constituting the quadruple circuit of FIG. 8 increases, that is, a timing chart when the quadruple circuit of FIG. 8 operates abnormally.

[0012] The delay circuit 1
, The first, second, and third delay circuits 1
If the resistance R, the capacitor C, and the on-resistance of the first inverter 10 are all equal to each other,
The delay time of each delay circuit 1 increases uniformly, and the input signal IN
Delay time of the output signal OUT1 with respect to the
1 and the output signal OU
The delay times of the output signal OUT3 with respect to T2 are all equal, and are t2 (t2> t1).

As a result of the increase in the delay time, when the output signal OUT3 rises later than the input signal IN falls, the output signal OUT3 falls later than the input signal IN rises. A period P occurs in which the H (High) level states of a overlap. As a result, the output signal a
The frequency of the output signal OUT generated from the output signal b through the two-input NOR circuit 30 and the inverter 12 is twice the frequency of the input signal IN, and the output signal OUT having a quadruple frequency cannot be obtained.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor integrated circuit capable of suppressing a change in delay time of a delay circuit due to a change in power supply voltage or the like. It is.

[0015]

According to a semiconductor integrated circuit of the present invention, a first delay element to which an input signal is input and a first delay element having one end connected to the output side of the first delay element. A resistor, at least one series-connected resistor having one end connected to the other end of the first resistor, and a second delay element having an input connected to the other end of the at least one series-connected resistor and outputting an output signal; A capacitor having one side connected to a node between the output side of the first delay element and the input side of the second delay element, and having a ground potential applied to the other side, and one or more series connected in accordance with the power supply potential One or more delay time correction circuits for short-circuiting both ends of one of the resistors constituting the connection resistance are provided. With this configuration, the delay time of the delay circuit caused by the fluctuation of the power supply voltage or the like can be reduced. Can be suppressed.

According to another configuration of the semiconductor integrated circuit according to the present invention, the first inverter to which the input signal is input and the first inverter having one end connected to the output side of the first inverter.
And an input side is connected to the other end of the first resistor, a second inverter that outputs an output signal, one side is connected to the input side of the second inverter, and a ground potential is applied to the other side. A first capacitor, one or more delay time correction circuits for applying a ground potential to one of the one or more capacitors, one of which is connected to the input side of the second inverter, according to a power supply potential; With this configuration, it is possible to suppress fluctuations in the delay time of the delay circuit due to fluctuations in the power supply voltage and the like.

[0017]

Embodiments of a semiconductor integrated circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. Specifically, a circuit of a circuit in which a delay time correction circuit according to the present invention is added to a delay circuit It is a block diagram.

The semiconductor integrated circuit according to the first embodiment of the present invention includes a delay circuit 1 ', a delay time correction circuit including a delay detection circuit 30 and a resistance value correction circuit 40 added to the delay circuit 1'. It is composed of The specific configuration is
It is as follows.

The delay circuit 1 ′ includes a third inverter 13 to which the input signal IN is input, resistors R 1 and R 2 and a fourth inverter 14 connected in series to the output side of the third inverter 13, And a capacitor C disposed between the input node N of the four inverters 14 and the ground.

The delay detection circuit 30 includes a delay circuit 1 for outputting an output signal OUT1, an input signal IN and an output signal OU.
And a two-input EX-OR circuit 22 to which T1 is input. The delay circuit 1 provided in the delay detection circuit 30 is a circuit similar to the circuit shown in FIG. 6, and includes a first inverter 10 to which an input signal IN is input, and an output side of the first inverter 10. A resistor R having one end connected to
A capacitor C disposed between the other end of the resistor R and ground;
The other end of the resistor R is connected to the input side, and the second inverter 11 outputs the output signal OUT1 from the output side. Output node M of two-input EX-OR circuit 22
Is the output signal M of the delay detection circuit 30.
Becomes

The resistance correction circuit 40 is a transfer gate connected in parallel to the resistance R2 of the delay circuit 1 '.
This transfer gate is an n-channel MOSFET
Q1 and p-channel MOSFET Q2, and the input side is n
A fifth inverter 15 whose output side is connected to the gate of the p-channel MOSFET Q2 is connected to the gate of the channel-type MOSFET Q1.
The output signal M of the delay detection circuit 30 is input to the gate of the OSFET Q1.

Hereinafter, the principle that the semiconductor integrated circuit according to the present invention can suppress the fluctuation of the delay time of the delay circuit will be described with reference to the configuration of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. It will be described based on.

The drive current IDS in the saturation region of the MOSFET constituting the transfer gate as the resistance value correction circuit 40 is given by the following equation, where V is the power supply voltage, L is the channel length of the MOSFET, and W is the channel width of the MOSFET. expressed. IDS = (K / 2) .times. (W / L) .times. (V-VTH) 2 where K = .epsilon.OX.times..mu. / TOX. From the above formula, MOSF
It can be seen that the drive current IDS of the ET is proportional to the ratio W / L of the channel width W to the channel length L of the MOSFET. Further, when the power supply voltage V decreases, the value of V-VTH decreases, so that the drive current IDS also decreases. For example, when the threshold voltage VTH is 0.8 V, the power supply voltage V is 1.2
The current ratio MI at 1.8V with respect to V is: MI = {(1.8V-0.8V) / (1.2V-0.8V)} 2 = 6.25 The voltage ratio MV is MV = 1.8V / 1.2V = 1.5 From this example, the current ratio MI is equal to the voltage ratio MV of 1.
It turns out that 6.25 is larger than 6.

Next, the following two different delay circuits:
The first and second delay circuits will be compared and examined. The circuit configuration of the first and second delay circuits is the same as that of the delay circuit of FIG. 6, and the values of the power supply voltage V, the ON resistance of the inverter, and the resistance R are set as shown in Table 1 below. However, capacitor C
Is a constant value.

[0026]

[Table 1] As can be seen from Table 1, the first delay circuit has a larger ON resistance of the inverter than the resistance R, whereas the second delay circuit has the second delay circuit.
In the delay circuit, the ON resistance of the inverter is smaller than that of the resistor R.

Like the first delay circuit, a delay circuit having a larger ON resistance of the inverter than the resistance R is a delay circuit 1 'in the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. In addition, a delay circuit in which the ON resistance of the inverter is smaller than the resistance R as in the second delay circuit is shown in FIG.
This is used for the delay circuit 1 in the semiconductor integrated circuit according to the first embodiment of the present invention. In the delay circuit 1 'in the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 1, the resistance R of the first delay circuit is replaced by a combined resistance of the resistances R1 and R2. Thus, hereinafter, the resistance values of the resistors R1 and R2 to be set are determined by calculation.

Under the above conditions, the first case where the power supply voltage V is high (1.8 V) and the case where the power supply voltage V is low (1.2 V) are as follows.
When the resistance amplification ratio of the second delay circuit is obtained, the resistance amplification ratio of the first delay circuit = 245 kΩ / 140 kΩ = 1.75 The resistance amplification ratio of the second delay circuit = 270 kΩ / 60 kΩ = 4.5 . That is, when the power supply voltage V drops from 1.8 V to 1.2 V, the delay time of the first delay circuit becomes 1.75 times, whereas the delay time of the second delay circuit becomes 4.5 times. become.

In the semiconductor integrated circuit according to the first embodiment of the present invention, when the delay detection circuit 30 outputs an H level signal, the resistance of the delay circuit 1 'is R1 and the delay detection circuit 30 is When the L-level signal is being output, the resistance of the delay circuit 1 'is R1 + R2, so the time when the output signal of the delay detection circuit 30 is at the H level is obtained. The time when the output signal of the delay detection circuit 30 is at the H level is the delay time of the delay circuit 1, that is, the second delay circuit in Table 2.
Here, a voltage equation based on the CR time constant of the delay circuit 1 is expressed as V (t) = V × exp (−t / CR).

Therefore, the initial value of the potential of the node N is V, and the potential of the node N is the circuit threshold VTHC of the fourth inverter 14.
Assuming that the time when (= V / 2) becomes tc, from the above equation,
The following equation holds. V / 2 = V × exp (−tc / CR) Therefore, tc = 0.693CR.

Here, C = 1 / 0.693 = 1.44p
Assuming that F, tc = R. From this equation, it can be seen that the time tc is proportional to the value of the resistor R. Therefore, the H level signal output time td (1.8 V) and td (1.2 V) of the delay detection circuit 30 is as follows: td (1.8 V) = 60 ns td (1.2 V) = 270 ns

Similarly, the delay circuit 1 ', that is, the first
Is as follows: td (1.8 V) = 140 ns td (1.2 V) = 245 ns

Since the delay time t1 of the delay circuit 1 'when the power supply voltage V = 1.2V is shorter than the H level signal output time 270 ns of the delay detection circuit 30, Vthc = V / 2 = V.times.exp (-t1) / CR). Therefore, t1 = R

As described above, in the semiconductor integrated circuit according to the first embodiment of the present invention, the delay detection circuit 30
Is outputting an H level signal, the resistances R1 and R
The resistance R of the delay circuit 1 ', which is a combined resistance of the delay circuit 2 and the resistance R2, becomes R1. In a first delay circuit having a conventional circuit configuration, a resistor R =
Although it is 120 kΩ, the resistance value of the resistor R1 when a delay circuit having substantially the same circuit configuration as the first delay circuit is used for the delay circuit 1 ′ in the semiconductor integrated circuit according to the first embodiment of the present invention Is 100 kΩ, the delay time t1 of the delay circuit 1 ′ when the power supply voltage V is 1.2 V, including the ON resistance of the inverter, is t1 = 100 + 125 = 225 ns.

Next, for comparison between the semiconductor integrated circuit according to the first embodiment of the present invention in which an appropriate resistance value is set and the conventional delay circuit 1, a case where the power supply voltage V = 1.8V is used. , The resistance value of the resistor R2 when the delay time is equal is obtained.

The voltage equation based on the CR time constant of the delay circuit 1 'is given by the H level signal output time td of the delay detection circuit 30.
(1.8 V) = 60 ns, delay time t1 of delay circuit 1 '
= 140 ns, the resistance R1 = 100 kΩ, and the potential of the node B when the resistance of the delay circuit 1 'is switched is V1, the following equation is satisfied when the delay detection circuit 30 outputs the H level signal. V1 = V × exp (−td / CR1) When the L level signal is output from the delay detection circuit 30, the following equation is satisfied. Vthc = V / 2 = V1 × exp ｛− (t1-td) / C
(R1 + R2)｝ Therefore, R2 = 100 kΩ

Based on the above calculations, the first aspect of the present invention
Resistors R1 and R in the semiconductor integrated circuit according to the embodiment of FIG.
2 is set to R1 = R2 = 100 kΩ, and the resistance value of the resistor R in the conventional delay circuit is set to R = 120 kΩ, so that the semiconductor integrated circuit according to the first embodiment of the present invention and the conventional delay circuit The circuit was compared. When the respective circuits are adjusted so that the delay time when the power supply voltage V is 1.8 V is 140 ns, the delay time when the power supply voltage V is 1.2 V is 245 ns in the conventional delay circuit, and the first delay time of the present invention is obtained. 225 ns in the semiconductor integrated circuit according to the embodiment.

Therefore, according to the semiconductor integrated circuit of the present invention, it is possible to suppress the fluctuation of the delay time due to the fluctuation of the power supply voltage V.

FIG. 2 shows a case where the power supply voltage V is high (V = 1.
8V) is a timing chart of the semiconductor integrated circuit according to the first embodiment of the present invention and the conventional delay circuit at 8V), and a solid line graph L1H indicates a node N of the semiconductor integrated circuit according to the first embodiment of the present invention. , And the dotted line graph L2H indicates the change in the potential of the node B of the conventional delay circuit.

In this case, the H-level signal output (H-level potential of the node M) of the delay detection circuit 30 indicates that the potential of the node N of the delay circuit 1 'is equal to the circuit threshold Vth of the fourth inverter 14.
Before reaching c, the signal changes to an L level signal output.

The resistance of the delay circuit 1 'is changed from the time td0 at which the delay detection circuit 30 starts outputting the H level signal to the low level.
It is R1 until time td1 when it changes to a level signal, and R1 + R2 from time td1 when the delay detection circuit 30 starts outputting an L level signal to time td0 when it changes to an H level signal.

Accordingly, the time from when the input signal rises or falls until the potential of the node N reaches the circuit threshold Vthc of the fourth inverter 14, that is, the delay time is
The semiconductor integrated circuit according to the first embodiment of the present invention is equal to the conventional delay circuit.

FIG. 3 shows a case where the power supply voltage V is low (V = 1.
2V) is a timing chart of the semiconductor integrated circuit according to the first embodiment of the present invention and the conventional delay circuit, wherein a solid line graph L1L indicates a node N of the semiconductor integrated circuit according to the first embodiment of the present invention; And the dotted line graph L2L shows the change in the potential of the node B of the conventional delay circuit.

In this case, the H-level signal output (H-level potential of the node M) of the delay detection circuit 30 indicates that the potential of the node N of the delay circuit 1 'is equal to the circuit threshold Vth of the fourth inverter 14.
After reaching c, the signal changes to an L level signal output.

Since the delay time td occurs after the potential of the node N reaches the circuit threshold Vthc of the fourth inverter 14, the resistance of the delay circuit 1 'is
Starts outputting an H level signal from time td2 to node N
Until time td3 at which the potential of the fourth inverter 14 reaches the circuit threshold Vthc of the fourth inverter 14, and from the time td3 when the potential of the node N reaches the circuit threshold Vthc of the fourth inverter 14, the delay detection circuit 30 outputs the H level signal. R1 + R2 until time td2 when output starts.

Accordingly, the time from when the input signal rises or falls until the potential of the node N reaches the circuit threshold Vthc of the fourth inverter 14, that is, the delay time is
While the delay time is 245 ns in the conventional delay circuit, it is 225 ns in the semiconductor integrated circuit according to the first embodiment of the present invention, which is shorter than the conventional delay circuit. That is, according to the semiconductor integrated circuit of the present invention, it is possible to suppress the fluctuation of the delay time of the delay circuit due to the fluctuation of the power supply voltage V and the like.

FIG. 4 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment of the present invention. More specifically, FIG. 4 shows a circuit in which a plurality of delay time correcting circuits according to the present invention are added to a delay circuit. It is a circuit block diagram.

The semiconductor integrated circuit according to the second embodiment of the present invention comprises a delay circuit 1 ", delay detection circuits 31 and 32 and resistance correction circuits 41 and 42 added to the delay circuit 1".
And a delay detection circuit 31, a resistance value correction circuit 41, and a delay detection circuit 41 for the resistors R2, R3, respectively, of the resistors R1, R2, R3 constituting the delay circuit 1 ″. 32 and a resistance correction circuit 42 are added.

The specific configuration of each circuit included in the semiconductor integrated circuit according to the second embodiment of the present invention is substantially the same as that of the first embodiment, and a plurality of delay detection circuits having different delay times are provided. Is used to control the delay time with higher accuracy.

According to the semiconductor integrated circuit according to the second embodiment of the present invention, the fluctuation of the delay time of the delay circuit caused by the fluctuation of the power supply voltage V and the like is also based on the same principle as that of the first embodiment. Can be suppressed.

FIG. 5 is a circuit configuration diagram of a semiconductor integrated circuit according to a third embodiment of the present invention. Specifically, a circuit of a circuit in which a delay time correction circuit according to the present invention is added to a delay circuit It is a block diagram.

The semiconductor integrated circuit according to the third embodiment of the present invention includes a delay circuit 3 and a delay time correction circuit including a delay circuit 1 and a two-input EX-OR circuit 23 added to the delay circuit 3. It is configured. The specific configuration is as follows.

The delay circuit 3 includes a sixth inverter 16 to which the input signal IN is input, a resistor R and a seventh inverter 17 connected in series to the output side of the sixth inverter 16.
And a capacitor C1 disposed between the input side of the seventh inverter 17 and the ground.

The delay time correction circuit includes a delay circuit 1 to which the input signal IN is input, a two-input EX-OR circuit 23 to which the input signal IN and the output of the delay circuit 1 are input, and an input of the seventh inverter 17. An output signal from the two-input EX-OR circuit 23 is input to the gate of the n-channel MOSFET Q3.

The semiconductor integrated circuit according to the third embodiment of the present invention is a semiconductor integrated circuit having a configuration in which the delay time is controlled by a capacitor, and the semiconductor integrated circuit according to the third embodiment of the present invention can also be used. Based on the same principle as in the first embodiment, it is possible to suppress fluctuations in the delay time of the delay circuit due to fluctuations in the power supply voltage V and the like.

As in the relationship between the first embodiment and the second embodiment, the delay time correction circuit using a capacitor in the semiconductor integrated circuit according to the third embodiment of the present invention is A plurality of circuits 3 may be added.

Further, the delay time correction circuit using the transfer gate in the semiconductor integrated circuit according to the first embodiment of the present invention and the capacitor using the capacitor in the semiconductor integrated circuit according to the third embodiment of the present invention are used. You may use together with a delay time correction circuit.

[0058]

According to the semiconductor integrated circuit of the present invention,
A first delay element to which an input signal is input, a first resistor having one end connected to the output side of the first delay element, and one or more series circuits having one end connected to the other end of the first resistor Connection resistance,
An input side is connected to the other end of the one or more series-connected resistors, and a second delay element that outputs an output signal is connected to a node between the output side of the first delay element and the input side of the second delay element. A capacitor connected to one side and having a ground potential applied to the other side; and one or more delay time correction circuits for short-circuiting both ends of one or more resistors connected in series according to the power supply potential. Therefore, it is possible to suppress a change in the delay time of the delay circuit due to a change in the power supply voltage or the like.

According to another configuration of the semiconductor integrated circuit according to the present invention, the first inverter to which the input signal is input and the first inverter having one end connected to the output side of the first inverter.
And an input side is connected to the other end of the first resistor, a second inverter that outputs an output signal, one side is connected to the input side of the second inverter, and a ground potential is applied to the other side. A first capacitor, one or more delay time correction circuits for applying a ground potential to one of the one or more capacitors, one of which is connected to the input side of the second inverter, according to a power supply potential; , The fluctuation of the delay time of the delay circuit due to the fluctuation of the power supply voltage or the like can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 shows a case where the power supply voltage V is high (V = 1.8
7 is a timing chart of the semiconductor integrated circuit according to the first embodiment of the present invention and a conventional delay circuit in V).

FIG. 3 shows a case where the power supply voltage V is low (V = 1.2
7 is a timing chart of the semiconductor integrated circuit according to the first embodiment of the present invention and a conventional delay circuit in V).

FIG. 4 is a circuit configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of a conventional delay circuit.

FIG. 7 is a timing chart of the delay circuit of FIG. 6;

8 is a circuit configuration diagram of a quadruple circuit using the delay circuit 1 of FIG. 6;

FIG. 9 is a timing chart at the time of normal operation of the quadruple circuit of FIG. 8;

FIG. 10 is a timing chart at the time of an abnormal operation of the quadruple frequency multiplier of FIG. 8;

[Explanation of symbols]

 1, 1 ', 1 ", 3, 31, 32 delay circuit 24 quadruple circuit 30 delay detection circuit 40, 41, 42 resistance correction circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Junichi Nakama 25-1, Ekimae Honmachi, Kawasaki-ku, Kawasaki, Kanagawa Prefecture Inside Toshiba Microelectronics Co., Ltd. (72) Inventor Hidehiko Tachibana Ekimae-Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa 25-1 Toshiba Microelectronics Corporation

Claims (14)

[Claims] A first delay element to which an input signal is input; a first resistor having one end connected to an output side of the first delay element; and one end connected to the other end of the first resistance. An input side connected to the other end of the one or more series-connected resistors, and the other end of the one or more series-connected resistors;
A second delay element that outputs an output signal, one end is connected to a node between an output side of the first delay element and an input side of the second delay element, and a ground potential is applied to the other side. And a delay time correction circuit for short-circuiting both ends of any one of the resistors constituting the one or more series-connected resistors according to a power supply potential. 2. A first inverter to which an input signal is input, and a first inverter having one end connected to an output side of the first inverter.
A second resistor having one end connected to the other end of the first resistor, a second inverter having an input connected to the other end of the second resistor, and outputting an output signal; A first capacitor having one side connected to the input side of the second inverter and a ground potential applied to the other side; and a delay time correction circuit for short-circuiting both ends of the second resistor according to a power supply potential. And a semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 2, wherein said delay time correction circuit comprises: a delay circuit to which said input signal is inputted; and a two-input to which said input signal and an output signal of said delay circuit are inputted. EX-O
A first MOS transistor having a gate to which an output signal of the two-input EX-OR circuit is input, and a source and a drain having a source and a drain of the first MOS transistor. A second MOS transistor connected in common with each other; and a third inverter having an input side connected to the gate of the first MOS transistor and an output side connected to the gate of the second MOS transistor, respectively. A semiconductor integrated circuit, comprising: a circuit including a transfer gate connected in parallel to a resistor. 4. The semiconductor integrated circuit according to claim 3, wherein said delay circuit comprises: a fourth inverter to which said input signal is input; and a third terminal having one end connected to an output side of said fourth inverter.
A fifth inverter having an input connected to the other end of the third resistor and outputting an output signal of the delay circuit; one input connected to the input of the fifth inverter, and the other A semiconductor integrated circuit, comprising: a circuit including a second capacitor to which a ground potential is applied. 5. A first inverter to which an input signal is input, and a first inverter having one end connected to an output side of the first inverter.
A second resistor having one end connected to the other end of the first resistor; a third resistor having one end connected to the other end of the second resistor; A second inverter having an input connected to the other end and outputting an output signal; a first capacitor having one connected to an input of the second inverter and having a ground potential applied to the other; A first short-circuiting both ends of the second resistor in accordance with
And a second circuit for short-circuiting both ends of the third resistor according to the power supply potential.
And a delay time correction circuit. 6. The semiconductor integrated circuit according to claim 5, wherein said first delay time correction circuit comprises: a first delay circuit to which said input signal is inputted; and said input signal and said first delay circuit. And a first delay detection circuit comprising a first two-input EX-OR circuit to which the output signal of the first two-input EX-OR circuit is inputted. MOS transistor, a second MOS transistor having a source and a drain commonly connected to a source and a drain of the first MOS transistor, an input side being a gate of the first MOS transistor, and an output side being a second MOS transistor. And a first transfer gate connected in parallel to the second resistor, and a third inverter connected to each of the third inverters. A second delay time correction circuit comprising: a second delay circuit to which the input signal is input; a second two-input EX-OR circuit to which the input signal and an output signal of the second delay circuit are input; A second delay detection circuit comprising: a third MOS transistor having a gate to which an output signal of the second two-input EX-OR circuit is input; and a source having a source and a drain of the third MOS transistor , A drain commonly connected to the drain, and a fourth inverter whose input side is connected to the gate of the third MOS transistor and whose output side is connected to the gate of the fourth MOS transistor, respectively. A semiconductor integrated circuit, comprising: a circuit including a second transfer gate connected in parallel to a third resistor. 7. The semiconductor integrated circuit according to claim 6, wherein said first delay circuit has a fifth inverter to which said input signal is inputted, and one end connected to an output side of said fifth inverter. The fourth
And a sixth inverter having an input connected to the other end of the fourth resistor and outputting an output signal of the first delay circuit, one end connected to an input of the sixth inverter, A second capacitor to which a ground potential is applied to the other side, wherein the second delay circuit is a circuit in which two stages of delay circuits having the same configuration as the first delay circuit are connected in cascade. A semiconductor integrated circuit, comprising: 8. A first inverter to which an input signal is input, and a first inverter having one end connected to an output side of the first inverter.
A second inverter having an input connected to the other end of the first resistor and outputting an output signal; one input connected to the input of the second inverter, and a ground potential applied to the other. And at least one delay time for applying a ground potential to one of the one or more capacitors, one of which is connected to the input side of the second inverter, in accordance with a power supply potential. A semiconductor integrated circuit comprising a correction circuit. 9. A first inverter to which an input signal is input, and a first inverter having one end connected to an output side of the first inverter.
A second inverter having an input connected to the other end of the first resistor and outputting an output signal; one input connected to the input of the second inverter, and a ground potential applied to the other. And a delay time correction circuit for applying a ground potential to the other side of the second capacitor, one side of which is connected to the input side of the second inverter, according to a power supply potential. Characteristic semiconductor integrated circuit. 10. The semiconductor integrated circuit according to claim 9, wherein said delay time correction circuit comprises: a delay circuit to which said input signal is inputted; and a two-input to which said input signal and an output signal of said delay circuit are inputted. EX-O
A source and a drain are respectively connected between the other side of the second capacitor and a ground potential point, and a gate receives an output signal of the two-input EX-OR circuit; And a MOS transistor. 11. The semiconductor integrated circuit according to claim 10, wherein said delay circuit comprises: a third inverter to which said input signal is input; and a second inverter having one end connected to an output side of said third inverter.
And a fourth inverter having an input connected to the other end of the second resistor and outputting an output signal of the delay circuit, one side connected to the input side of the fourth inverter, and the other end connected to the other side. A semiconductor integrated circuit, comprising: a circuit including a third capacitor to which a ground potential is applied. 12. The semiconductor integrated circuit according to claim 5, wherein at least one of said third resistor is inserted and connected between the other end of said third resistor and an input side of said second inverter. And a delay time correction circuit for short-circuiting one of both ends of the one or more resistors according to a power supply potential. 13. The semiconductor integrated circuit according to claim 9, further comprising: one or more capacitors each having one side connected to an input side of said second inverter, and a power supply potential. A semiconductor integrated circuit, comprising: one or more delay time correction circuits for applying a ground potential to the other of the one or more capacitors. 14. A first inverter to which an input signal is input, and a first inverter having one end connected to an output side of the first inverter.
And one or more series-connected resistors each having one end connected to the other end of the first resistor, and an input side connected to the other end of the one or more series-connected resistors,
A second inverter that outputs an output signal; a first capacitor having one side connected to the input side of the second inverter, and a ground potential applied to the other side; One or more delay time correction circuits having a first configuration for short-circuiting either end of a connection resistor, one or more capacitors each having one side connected to an input side of the second inverter, and a power supply potential And a delay time correction circuit having at least one second configuration for applying a ground potential to one of the other side of the at least one capacitor.