JPH10163448A - Manufacture of case-type capacitor having folds on single side - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a stack capacitor of high capacitance value and a stack DRAM in high packing density. SOLUTION: In process, the things other than a capacitor region are removed from alternate complex layer structure composed of thermochemical growth silicon dioxides and plasma silicon dioxides, and a cavity is made between the thermochemical growth silicon dioxides of remaining alternate complex layer structure, so as to make folds on the surface of the alternate complex layer structure and form the second polysilicon 36 of one layer. Using etching technique, etch back is performed to the second polysilicon 36, and the second polysilicon 36 above the alternate complex layer structure, and the second polysilicon 36 and the first polysilicon 18 above the second dielectric layer, are etched, whereby the second polysilicon spacer 36A is made at the side of the alternate complex layer structure, the alternate complex layer structure having folds on the surface is removed, and the lower electrode of the capacitor is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a kind of DRAM. In the present invention, first, a field effect transistor and a word line are formed on a silicon semiconductor substrate, and then, a first dielectric layer and a second dielectric layer are deposited.
A memory cell contact is formed, followed by a layer of first polysilicon, which is filled with the memory cell contact described above. Furthermore, a layer of nitrated silicon is formed, and then an alternating multilayer structure composed of thermal chemical vapor deposition silicon dioxide and plasma silicon dioxide is formed. After removing the above-mentioned alternate multilayer structure, a part of the above-mentioned alternate multilayer structure is etched using a hydrofluoric acid solution, and the etching rate of the plasma silicon dioxide is reduced by the above-described thermal chemical vapor. Being much larger than phase grown silicon dioxide, forming cavities between the thermochemical vapor grown silicon dioxide,
Forming wrinkles on the surface of the alternating multilayer structure, followed by a second layer
Depositing polysilicon, and then performing a vertical unidirectional etchback on the second polysilicon using a plasma etching technique to form the second polysilicon and the second dielectric above the alternating multilayer structure; Removing the layer and forming a second polysilicon spacer beside the alternate multilayer structure described above, followed by removing the alternate multilayer structure having wrinkles on its surface, thereby removing the first polysilicon and the second polysilicon spacer. A lower electrode of a capacitor composed of a polysilicon spacer is formed.

[0002]

2. Description of the Related Art A typical stacked DRAM is manufactured by manufacturing a MOS field effect transistor and a capacitor on a silicon semiconductor substrate, and connecting a source electrode of the MOS field effect transistor to a lower electrode of a capacitor.
The memory cell of the DRAM is formed by utilizing the connection with the memory device (de), and an enormous number of memory cells are integrated to form a memory integrated circuit.

Recently, the integration density of DRAMs (packin
g density is increasing rapidly and now it is already a memory cell size of 1.5 square microns (um ² ).
Has been mass-produced at 64 million bits, and the NEC company announced in 1995 that it had already manufactured a prototype of a billion-bit DRAM. Also in Taiwan, Hsinchu Chemical Industrial Park (Science-Based Ind.)
integrated park manufacturer)
For example, Mosel-Vitelic and TI-Ac
er has already entered the stage of preparing for mass production of 0.4-0.45 micron, 16 million bit DRAMs.

In order to achieve the purpose of high integration of DRAM, it is necessary to reduce the size of a memory cell, that is, to reduce the size of a field effect transistor and a capacitor. However, the reduction in the size of the capacitor lowers the capacitance value, thereby lowering the signal-to-noise ratio of the memory circuit, leading to drawbacks such as erroneous determination of the electric circuit and instability of the electric circuit.

When reducing the size of a capacitor, it is necessary to maintain or increase the capacitance value of the capacitor as typified by US Pat. No. 5,021,357 to Masao Taguchi of Fujitsu Limited of Japan. Fin type capacitor structure described in H.E. Wa
Novel capacitor structure by Tanabe et al.

[0006]

The main objects of the present invention are as follows.
An object of the present invention is to provide a method of manufacturing a high-capacity stacked capacitor.

Another object of the present invention is to provide a method of manufacturing a stacked DRAM having a high integration density.

[0008]

According to a first aspect of the present invention, an oxide layer for isolating a field effect transistor is formed on a silicon semiconductor substrate, and a field effect transistor and a word line are formed. Is the gate oxide layer,
A gate electrode, a source electrode, and a drain electrode are included, a first dielectric layer and a second dielectric layer are formed, and the first dielectric layer and the second dielectric layer are etched using lithography and etching techniques to form the above-described electric field. Exposing the source pole of the effect transistor, thereby forming a memory cell contact, forming one layer of first polysilicon, filling the first polysilicon with the memory cell contact, and forming a third dielectric layer; Then, an alternate multilayer structure composed of thermal chemical vapor deposition silicon dioxide and plasma silicon dioxide is formed, and the above alternate multilayer structure other than the capacitor region is removed using lithography technology and plasma etching technology. Is terminated at the surface of the third dielectric layer, and the alternate multilayer structure is etched, and a cavity is formed between the thermal chemical vapor deposition silicon dioxide. Forming a wrinkle on the surface of the alternate multilayer structure, forming one layer of second polysilicon, performing etch-back on the second polysilicon using an etching technique, A second polysilicon over the structure, and a second polysilicon and a first over the second dielectric layer.
Etching the polysilicon, thereby forming a second polysilicon spacer beside the alternating multilayer structure, removing the aforementioned alternating multilayer structure having wrinkles on the surface, forming a lower electrode of the capacitor, Forming a layer, forming a third polysilicon, etching the third polysilicon and the capacitor dielectric layer using lithography and etching techniques to form an upper electrode of the capacitor. I have.

According to a second aspect of the present invention, the first dielectric layer and the second dielectric layer are made of silicon dioxide, and the thickness of the first dielectric layer is 3000.
2. The method of claim 1, wherein the thickness of the second dielectric layer is between 500 and 1500 Angstroms.

According to a third aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the first polysilicon is formed by using a chemical vapor deposition method, and has a thickness between 2000 and 3500 angstroms. And how to do it.

The invention according to claim 4 wherein the third dielectric layer is nitrated silicon and has a thickness between 500 and 1500 angstroms.
M manufacturing method.

According to a fifth aspect of the present invention, there is provided a thermal chemical vapor deposition silicon dioxide having an alternating multilayer structure, wherein the low pressure chemical vapor deposition method, the atmospheric pressure chemical vapor deposition method, the subatmospheric pressure chemical vapor deposition method, or various other methods. 2. The method according to claim 1, wherein the stacked DRAM is formed using a chemical vapor deposition method, and each layer has a thickness between 200 and 400 Å.

According to a sixth aspect of the present invention, the plasma silicon dioxide having an alternating multilayer structure is formed by using a plasma enhanced chemical vapor deposition method, and the thickness of each layer is between 200 and 400 angstroms. Stack D according to item 1
This is a method for manufacturing a RAM.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a stacked DRAM according to the first aspect, wherein the second polysilicon is formed by using a chemical vapor deposition method, and has a thickness between 1000 and 2500 angstroms. And how to do it.

The invention according to claim 8 is the method for manufacturing a stacked DRAM according to claim 1, wherein the cavity is formed by using a hydrofluoric acid solution.

According to a ninth aspect of the present invention, the capacitor dielectric layer comprises:
2. The method for manufacturing a stacked DRAM according to claim 1, wherein the stacked DRAM is composed of nitrated silicon oxide, nitrated silicon and silicon dioxide, or composed of ditantalum pentoxide.

According to a tenth aspect of the present invention, the third polysilicon is formed using a chemical vapor deposition method, and has a thickness of 10
2. The method for manufacturing a stacked DRAM according to claim 1, wherein the method is between 00 and 2000 angstroms.

[0018]

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a well-known shallow trench isolation technique (Shallow) on a silicon semiconductor substrate.
An oxide layer of the field effect transistor is formed by using Trench Isolation (STI) or a local oxidation isolation technique. Thereafter, a field effect transistor and a word line are formed using a standard process. The above-described field effect transistor includes a gate oxide layer, a gate electrode, and a source electrode and a drain electrode.

Subsequently, a first dielectric layer and a second dielectric layer are deposited, and a well-known chemical mechanical polishing technique (Chemica) is used.
l Mechanical Polishing; CM
P) is used to planarize the first dielectric layer, and further, the first and second dielectric layers are etched using lithography and plasma etching techniques to expose the source electrode of the field effect transistor. Thus, a memory cell contact of the field effect transistor is formed. continue,
A layer of first polysilicon is formed, and the first polysilicon is filled in the above-mentioned memory cell contacts. later,
The above-mentioned first polysilicon is brought into electrical contact with the source electrode of the field-effect transistor via the above-mentioned memory cell contact.

Subsequently, one layer of nitrated silicon is formed, and thereafter, one layer of first thermal chemical vapor deposition silicon dioxide is formed using a thermal chemical vapor deposition method, and further, plasma enhanced chemical vapor deposition. Forming a first plasma silicon dioxide layer using the method, and subsequently successively, a second thermal chemical vapor deposition silicon dioxide layer, a second plasma silicon dioxide layer, and a third thermochemical vapor deposition silicon dioxide layer. Forming a third plasma silicon dioxide and a fourth thermal CVD silicon dioxide, thereby forming an alternating multilayer structure composed of the thermal CVD silicon dioxide and the plasma silicon dioxide.

Subsequently, the above-mentioned alternate multilayer structure other than the capacitor region is removed using a lithography technique and a plasma etching technique, and the plasma etching ends at the above-mentioned nitrated silicon surface. Thereafter, when a part of the above-mentioned alternating multilayer structure is etched from the side using a hydrofluoric acid solution, the etching rate of the above-mentioned plasma silicon dioxide is much larger than that of the thermal chemical vapor deposition silicon dioxide, and thus the first thermal etching is performed. Chemical vapor deposition silicon dioxide and second thermal chemical vapor deposition silicon dioxide, second thermal chemical vapor deposition silicon dioxide and third thermal chemical vapor deposition silicon dioxide,
A cavity is formed between the third and fourth thermal chemical vapor deposition silicon dioxides, and wrinkles are formed on the surface of the alternating multilayer structure.

Subsequently, a second layer of second polysilicon is deposited, and thereafter, the second polysilicon is deposited using a plasma etching technique.
Proceed with a unidirectional etchback perpendicular to the polysilicon, thus forming a second etch over the fourth thermal chemical vapor deposition silicon dioxide.
Removing the second polysilicon and the first polysilicon above the polysilicon and the second dielectric layer, thereby removing a second layer next to the alternate multilayer structure;
A polysilicon spacer is formed.

Subsequently, the above-mentioned alternating multilayer structure having wrinkles on the surface is removed, thereby forming a lower electrode (storage node) of the capacitor composed of the first polysilicon and the second polysilicon spacer. However, since the surface of the above-mentioned alternate multilayer structure has wrinkles, the inner surface of the second polysilicon spacer also has wrinkles, so that the surface area of the lower electrode of the capacitor is increased. Thereafter, a capacitor dielectric layer and a third polysilicon layer are deposited, and the third polysilicon layer and the capacitor dielectric layer are etched using a lithography technique and a plasma etching technique to form a capacitor plate upper electrode. .

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. Shown is a single unit of memory cell, the well structure can be an n-well region and a p-well region in the present invention, and the process can be extended and combined with a CMOS process.

First, please refer to FIG. Using a standard process, a well-known shallow trench isolation technique (Shallow Trench) is formed on the p-type silicon semiconductor substrate 10.
Isolation; STI) or a local silicon oxide isolation technique (LOCOS) is used to form an oxide layer that isolates the field effect transistor. The thickness of this oxide layer is between about 3000 Angstroms and 6000 Angstroms. After that, a field effect transistor and a word line are formed. This field effect transistor forms a gate oxide layer, a gate pole, a source pole 12 and a drain pole. In FIG. 1, the source electrode 12 is slightly shown, and the above-described oxide layer, gate oxide layer, gate electrode, drain electrode, and word line are not shown.

The above-mentioned gate oxide layer is formed by oxidizing a p-type silicon semiconductor substrate and has a thickness between 80 and 200 Å. The above-mentioned gate electrode is made of polysilicon or polycide (Polycide) formed by low pressure chemical vapor deposition (LPCVD), and has a thickness between 2000 and 3500 angstroms. The above-mentioned source electrode 12 and drain electrode are made of arsenic ions (As
⁷⁵ ), the ion layout is made to proceed, the amount of ion layout agent is between 2E15 and 5E16 atoms / cm ² , and the amount of ion layout energy is 3
It is between 0 and 80 kev.

As shown in FIG. 1, after the fabrication of the field effect transistor is completed, the first dielectric layer 14 and the second dielectric layer 16 are formed.
And first and second dielectric layers 14 and 1 described above using lithography and plasma etching techniques.
6 is etched to expose the source electrode 12 of the field effect transistor, thereby forming the memory cell contact 17 of the field effect transistor. The above is as shown in FIG. Later, the lower electrode of the above-mentioned capacitor is brought into electrical contact with the source electrode 12 of the field effect transistor via the memory cell contact 17.

The above-mentioned first dielectric layer 14 is usually a doped borophosphate glass film (BSSG) formed using atmospheric pressure chemical vapor deposition (APCVD), and its reaction pressure is 1.0 torr. The reaction temperature is about 400 ° C., the reaction gas is a mixed gas composed of Si (C ₂ H ₅ O) ₄ , TMB and N ₂ , the thickness is between 3000 and 8000 angstroms, and the thermal flow (Therm)
al Flow) or etch back (Etchbac)
k) or chemical mechanical polishing technology (Chemical M)
The above-mentioned first dielectric layer 14 is planarized by using mechanical policing (CMP). The above-mentioned second dielectric layer 16 is usually undoped silicon dioxide formed using low pressure chemical vapor deposition, and its reaction gas is Si (C ₂ H ₅ O) ₄ , N ₂ O and O ₂ . A gas mixture is formed, the reaction temperature is about 720 ° C., the reaction pressure is about 0.25 torr, and the thickness is 500 to 15
00 angstrom. First dielectric layer 1 described above
The plasma etching of the fourth and second dielectric layers 16 may be performed using a magnetic field enhanced active ion plasma etching technique,
Alternatively, the process proceeds using an electron cyclotron resonance plasma etching technique (ECR) or a traditional active ion plasma etching technique (RIE), and the reaction gas is usually CF ₄ , CHF ₃ and Ar.

Next, please refer to FIG. Subsequently, a first polysilicon layer 18 is formed. The first polysilicon 18 fills the memory cell contact 17 described above. The above-mentioned first polysilicon 18 is usually formed by low-pressure chemical vapor deposition in which phosphorus is synchronously doped. The reaction gases are (15% PH ₃ /85% SiH ₄ ) and (5%
% PH ₃ 95% N ₂ ) at a reaction temperature of about 5%.
At 50 ° C., its thickness is between 1000 and 4000 Å, depending on the dimensions of the memory cell contacts 17 described above.

Referring now to FIG. Subsequently, one layer of nitrated silicon 20 is formed, and then, one layer of first thermal chemical vapor grown silicon dioxide 22 (First Thermal CVD Oxi) is formed using a thermal chemical vapor deposition method.
de), and further a first plasma silicon dioxide 24 (First PE-Oxide) is formed using plasma enhanced chemical vapor deposition (PECVD). Subsequently, successively, one layer of the second thermal chemical vapor deposition silicon dioxide 26, the second plasma silicon dioxide 28, the third thermal chemical vapor deposition silicon dioxide 30, the third plasma silicon dioxide 32, the fourth thermal chemical vapor A phase-grown silicon dioxide 34 is formed, thereby forming an alternating multilayer structure (a) composed of thermochemical vapor-grown silicon dioxide and plasma silicon dioxide.
forming alternating layers).
The above is as shown in FIG.

The above-mentioned nitrated silicon 20 is formed by using a low-pressure chemical vapor deposition method, and its reaction gas is SiH ₂ C.
With l ₂ and NH ₃ , the reaction temperature is about 720 ° C., the reaction pressure is between 0.2 and 0.4 torr, and the thickness is between 500 and 1500 angstroms. The above-mentioned thermal chemical vapor deposition silicon dioxide is formed using a low pressure chemical vapor deposition method, and its reaction gas is SiH ₂ Cl ₂ and N ₂ O or SiH ₄ and O ₂ , and its reaction temperature is 750 to 900.
C. The above-mentioned plasma silicon dioxide is formed by using a plasma enhanced chemical vapor deposition method, and its reaction gas is SiH ₄ and O ₂ , and the reaction temperature is between 300 and 400 ° C. The first thermal chemical vapor deposition silicon dioxide 22, the first plasma silicon dioxide 24, the second
Thermal chemical vapor grown silicon dioxide 26, second plasma silicon dioxide 28, third thermal chemical vapor grown silicon dioxide 3
0, the third plasma silicon dioxide 32, and the fourth thermal chemical vapor deposition silicon dioxide 34 each have a thickness of 200 to 40.
0 angstrom. In addition to low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition (APCV)
D) or sub-atmospheric pressure chemical vapor deposition (Sub-Atom)
sphere Chemical Vapor Dep
The above-mentioned thermal chemical vapor deposition silicon dioxide can be formed by using an alternative method (position; SACVD) or various other chemical vapor deposition methods.

It should be noted that the etch selectivity (e) of the above-described plasma silicon dioxide to thermochemical vapor grown silicon dioxide in a hydrofluoric acid solution.
(tch selectivity) is about 4: 1, that is, the etch rate of plasma silicon dioxide is faster than that of thermochemical vapor grown silicon dioxide. Normally, by adjusting the electrode spacing, reaction pressure and firing frequency of the plasma deposition reaction chamber, the thin film properties of the plasma silicon dioxide can be changed, and consequently the etching rate in the hydrofluoric acid solution can be changed.

Next, please refer to FIG. 4 and FIG. Subsequently, a capacitor region (capacitor region) is formed using lithography technology and plasma etching technology.
Etching the above-mentioned alternate multilayer structure other than n), but this plasma etching ends at the above-mentioned nitrated silicon 20 surface. The above is shown in FIG. Thereafter, lateral etching is performed using a hydrofluoric acid solution (lateral etching).
etch) to remove a portion of the alternate multilayer structure, but since the etch rate of the plasma silicon dioxide is much greater than the thermal CVD silicon dioxide, the first thermal CVD Grown silicon dioxide 22
Between the second thermal chemical vapor grown silicon dioxide 26 and the second thermal chemical vapor grown silicon dioxide 26, between the second thermal chemical vapor grown silicon dioxide 26 and the third thermal chemical vapor grown silicon dioxide 30, 4 Between the thermal chemical vapor deposition silicon dioxide 34, a cavity 35 is formed,
A wrinkled surface (corruga) in the above-mentioned alternating multilayer structure
A ted surface is formed, and the state shown in FIG. 5 is obtained. A magnetic field-enhanced active ion plasma etching technique using a reaction gas of a mixed gas of CH ₄ , CHF ₃ and Ar can also be used for plasma etching of the above-mentioned alternating multilayer structure.

Next, please refer to FIG. 6 and FIG. Subsequently, as shown in FIG. 6, one layer of second polysilicon 36 is deposited. Thereafter, a unidirectional etch-back is performed perpendicularly to the second polysilicon 36 using a plasma etching technique, thereby forming a fourth thermally-chemically-grown silicon dioxide 34.
Removing the second polysilicon 36 above and the second polysilicon 36 above the second dielectric layer 16 and the first polysilicon 18,
Thus, a second polysilicon spacer 36 is provided next to the alternate multilayer structure.
A (second polysilicon spac)
er) is formed as shown in FIG. The method of forming the second polysilicon 36 is the same as that of the first polysilicon 18 and its thickness is between 1000 and 2500 angstroms. For the above-described vertical unidirectional etch back with respect to the second polysilicon 36, the aforementioned magnetic field enhanced active ion plasma etching technique can be used, and the plasma reaction gas is usually a gas mixture of Cl ₂ , SF ₆ and HBr. And

Next, please refer to FIG. 8 and FIG. Subsequently, using a hydrofluoric acid solution (HF), the above-mentioned alternating multilayer structure having the above-mentioned wrinkles on the surface is etched. Silicon 18 and second polysilicon spacer 3
6A capacitor lower electrode (storage)
node). Since the surface of the alternate multilayer structure has wrinkles, the inner surface of the second polysilicon spacer 36A also has wrinkles (FIG. 8), and therefore, the surface area of the lower electrode of the capacitor is increased. After completion of the lower electrode of the capacitor in this manner, the capacitor dielectric layer 38 is formed by a standard process, as shown in FIG.

Next, please refer to FIG. further,
A third polysilicon layer 40 is formed, and the capacitor dielectric layer 38 and the third polysilicon layer 40 are etched using lithography and plasma etching techniques to form a capacitor upper electrode (plate electrode).
mode) to form the state shown in FIG. 10, thus completing a high-capacity stacked capacitor and a high-density stacked DRAM.

The capacitor dielectric layer 38 described above is typically composed of silicon nitride (N) and silicon oxynitride (O). The above-mentioned nitrated silicon is formed by a low-pressure chemical vapor deposition method, and its thickness is between 40 and 60 angstroms. The above-mentioned nitrated silicon oxide is formed by oxidizing the above-mentioned nitrated silicon, and its thickness is formed. Is between 20 and 50 angstroms. The method of forming the third polysilicon 40 is the same as that of the first polysilicon 18, and the thickness thereof is
Between 2,000 and 2,000 angstroms. Also, the capacitor dielectric layer 38 described above can be composed of a tantalum pentoxide material (Ta ₂ O ₅ ).

[0038]

The present invention provides a method for manufacturing a stacked capacitor having a high capacitance and a method for manufacturing a stacked DRAM having a high integration density.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing an embodiment of the present invention.

FIG. 2 is a process sectional view showing an embodiment of the present invention.

FIG. 3 is a process sectional view showing an embodiment of the present invention.

FIG. 4 is a process sectional display diagram of the embodiment of the present invention.

FIG. 5 is a process sectional view showing an embodiment of the present invention.

FIG. 6 is a process sectional display diagram of the embodiment of the present invention.

FIG. 7 is a process sectional view showing an embodiment of the present invention.

FIG. 8 is a process sectional display diagram of the embodiment of the present invention.

FIG. 9 is a process sectional view showing an embodiment of the present invention.

FIG. 10 is a process sectional view showing an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 12 Source pole 14 1st dielectric layer 16 2nd dielectric layer 17 Memory cell contact 18 1st polysilicon 20 nitrated silicon 22 1st thermochemical vapor deposition silicon dioxide 24 1st plasma silicon dioxide 26 2nd thermochemical vapor deposition Silicon dioxide 28 Second plasma silicon dioxide 30 Third thermochemical vapor deposition silicon dioxide 32 Third plasma silicon dioxide 34 Fourth thermochemical vapor deposition silicon dioxide 35 Cavity 36 Second polysilicon 36A Second polysilicon spacer 38 Capacitor Dielectric layer 40 Third polysilicon

Claims (10)

[Claims] An oxide layer for isolating a field effect transistor is formed on a silicon semiconductor substrate, a field effect transistor and a word line are formed, and the field effect transistor is connected to a gate oxide layer, a gate electrode and a source electrode. Forming a first dielectric layer and a second dielectric layer, etching the first dielectric layer and the second dielectric layer using lithography and etching techniques to form a source electrode of the field effect transistor; Exposing, thereby forming a memory cell contact, forming a layer of first polysilicon, filling said first polysilicon with said memory cell contact, forming a third dielectric layer, thermal chemical vapor deposition An alternating multilayer structure composed of silicon dioxide and plasma silicon dioxide is formed, and lithography and plasma etching techniques are used to form a multilayer structure. Removing the alternating multilayer structure of the above-described non-support region,
Terminating the plasma etch at the surface of the third dielectric layer, etching the alternating multilayer structure to form cavities between the thermal chemical vapor grown silicon dioxide, and forming wrinkles on the surface of the alternate multilayer structure. Forming a second polysilicon layer, etching back the second polysilicon layer by using an etching technique, and forming a second polysilicon layer above the alternate multilayer structure and a second dielectric layer above the alternate multilayer structure; Etching the second polysilicon and the first polysilicon, thereby forming a second polysilicon spacer beside the alternate multilayer structure, removing the alternate multilayer structure having wrinkles on its surface, Forming lower electrode, forming capacitor dielectric layer, forming third polysilicon, etching the third polysilicon and capacitor dielectric layer using lithography and etching techniques And forming an upper electrode of the capacitor. 2. The method of claim 1, wherein the first and second dielectric layers are silicon dioxide, the thickness of the first dielectric layer is between 3000 and 8000 angstroms, and the thickness of the second dielectric layer is between 500 and 15.
2. The method according to claim 1, wherein the time is between 00 angstrom. 3. The stack DR of claim 1, wherein the first polysilicon is formed using chemical vapor deposition and has a thickness between 2000 and 3500 Å.
Manufacturing method of AM. 4. The method of claim 1, wherein the third dielectric layer is nitrated silicon and has a thickness between 500 and 1500 angstroms. 5. The thermal chemical vapor deposition silicon dioxide of the alternating multilayer structure is formed by low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, subatmospheric pressure chemical vapor deposition, or various other chemical vapor deposition methods. And the thickness of each layer is 20
2. The method according to claim 1, wherein the thickness is between 0 and 400 angstroms. 6. The method of claim 1, wherein the alternating multi-layer plasma silicon dioxide is formed using a plasma enhanced chemical vapor deposition method, wherein each layer has a thickness between 200 and 400 angstroms. Manufacturing method of stacked DRAM. 7. The stack DR according to claim 1, wherein the second polysilicon is formed using a chemical vapor deposition method and has a thickness between 1000 and 2500 angstroms.
Manufacturing method of AM. 8. The method according to claim 1, wherein the cavity is formed using a hydrofluoric acid solution. 9. The method according to claim 1, wherein the capacitor dielectric layer is composed of nitrated silicon oxide, nitrated silicon and silicon dioxide, or is composed of ditantalum pentoxide. 10. The method of claim 1, wherein the third polysilicon is formed using a chemical vapor deposition method, and has a thickness between 1000 and 2000 angstroms.