JPH10162570A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor storage device which is free from capacitance drop and does not consume much current at a standby time and the memory cell of which is not deteriorated in a data holding time by connecting one electrode of a memory cell capacitor to a fixed voltage source having an intermediate potential between a power supply potential and a grounding potential through a switching means which is controlled by control signal. SOLUTION: The storage node 2 of a memory cell capacitor 1 is connected to the source of a memory cell transistor 3. The plate electrode 4 of the capacitor 1 is connected to a (Vcc/2)-potential through a control transistor the turning on/off of which is commonly controlled by a control signal PD. The drain of the transistor 3 is connected to a bit line 5 or complementary bit line 6 and the gate of the transistor 3 is connected to a ward line 7. A control transistor is added to the plate electrode of the capacitor 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (hereinafter referred to as "DRAM"), and more particularly to a power-off mode for effectively reducing all leakage currents generated during standby. The present invention relates to a DRAM having a function.

[0002]

2. Description of the Related Art In a conventional DRAM, a power supply voltage is kept applied during standby to prevent destruction of memory cell data, and a constant standby current is consumed. On the other hand, a power-off mode has been proposed to effectively reduce all leakage currents generated during standby (IEICE Technical Report IC).
D95-51, "Study of ultra-low standby current DRAM"). In this power-off mode, the DRA
In order to shut off the power supply of M, the leakage current can be completely reduced to zero during standby. However, since a constant power-on current is required when the power is turned on again, the average current is proportional to the power-on current and inversely proportional to the maximum power-off time. For example, in the case of 1 Gbit DRAM data, the leakage current when the maximum power-off time is 512 ms is 0.8 μA,
In the case of the same 10 s, it was reported that it was 0.4 μA. By extending the data retention time of the memory cell, which is directly related to both the maximum power-off time and the refresh cycle, the standby current can be further reduced.

In order to extend the data retention time, it is necessary to suppress the leakage of the charge stored in the memory cell while the power is off. For this reason, an SOI structure or the like has been considered.
As another problem, it is necessary to prevent leakage of accumulated charges from the memory cells when power is turned off and power is turned on again. FIG. 5 shows a memory cell array of a conventional DRAM. Storage node 2 of memory cell capacitor 1
Are connected to the source of the memory cell transistor 3 and the plate electrode 4 of the memory cell capacitor 1 is commonly connected to (V
cc / 2) potential. The drain of the memory cell transistor 3 is connected to the bit line 5 or the complementary bit line 6, and the gate of the memory cell transistor 3 is connected to the word line 7.

[0004] There are two possible mechanisms for the leakage of the accumulated charges generated when the power of the DRAM is turned off and when the power is turned on.

[0005] The first is a leak of accumulated charges due to noise on the word line 7. When the power is turned off and the power is turned on, the potential of each node in the DRAM is unstable. If a word line is selected by mistake, the memory cell transistor 3 is turned on, and the accumulated charge flows out. It has been reported that this problem can be solved by grounding the word line boosted power supply about 1 μs before the power is cut off, and generating the word line boosted power supply about 1 μs after the power is turned on.

The second mechanism is a leak of accumulated charges due to a drop in plate electrode potential. FIG. 4 is a diagram showing potential changes of the storage node and the plate electrode when the power is turned on / off. In the conventional (Vcc / 2) plate method, after the power is turned off, the plate electrode potential drops to the ground potential, thereby causing a storage node (SN) of "0" data.
The potential of (“0”)) decreases from 0 V to (−Vcc / 2) due to cell capacitor coupling. As a result, the conduction of the memory cell transistor or the forward bias of the PN junction is caused, the potential approaches the ground direction rapidly (on the order of 1 to 10 ns), and the cell data is destroyed. This is because the potential difference between the storage node and the plate electrode becomes zero. Even after the power is turned on, the plate electrode potential returns to Vcc / 2, and the potential of the storage node is changed from 0 V to Vc by the cell capacitor coupling.
It is raised to c / 2, but of course the cell data remains corrupted. The storage node of data "1" (S
Immediately after the power is turned off, the potential of N ("1") drops from Vcc to Vcc / 2 due to cell capacitor coupling, and then relatively slowly reaches the ground potential due to leakage of the memory cell transistor or PN junction. Descend toward you. Even after power-on, the voltage rises by Vcc / 2 due to cell capacitor coupling.
Due to the leak of the memory cell transistor or the PN junction, the voltage drops relatively slowly toward the ground potential.

[0007] A 0 V plate system has been proposed for the Vcc / 2 system. This is a method in which the plate potential is kept at 0 V irrespective of the power on / off, and therefore, immediately after the power is turned off, the potential of the storage node does not change,
The stored charge of the cell is retained. FIG. 3 is a diagram showing potential changes of the storage node and the plate electrode when the power is turned on / off. The plate potential is kept at 0 V regardless of whether the power is on or off. After the power is turned off, the potential of the storage node (SN ("0")) of the data "0" converges to approximately 0 V toward the ground potential, and the same applies after the power is turned on again. Although the potential of the storage node (SN ("1")) of data "1" is faster than the potential of the storage node of data "0" due to leakage of the memory cell transistor or the PN junction, the potential of the storage node is relatively slowly reduced to the ground potential. The same is true after descending and returning to power-on again. In order to recover the lost charge, a refresh operation similar to the conventional one is required after the power is turned on.

[0008]

As described above, in the conventional Vcc / 2 plate system, after the power is cut off, the plate potential drops to the ground potential, and the cell capacitor coupling causes the "0" data storage node to lose its potential. The potential is 0V
From-to -Vcc / 2, causing conduction of the memory cell transistor or forward bias of the PN junction,
As shown in FIG. 4, the voltage rapidly approaches the ground potential (on the order of 1 to 10 ns), and the cell data is destroyed.

In addition, in the 0V plate system, since the maximum Vcc (V) is applied to both ends of the cell capacitor, the withstand voltage of the capacitor becomes a problem. In order to guarantee the pressure resistance,
The thickness of the capacitor insulating film must be increased, and the capacity is reduced. Therefore, the data retention time of the memory cell decreases, and the current consumption during standby increases.

The present invention has been made to solve the above-mentioned conventional problems.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor memory device having a memory cell including a memory cell capacitor and a memory cell transistor, wherein a source of the memory cell transistor is connected to the memory cell capacitor. A semiconductor memory device in which a plurality of memory cells are arranged in a matrix by connecting to one electrode, connecting the drain of the memory cell transistor to a bit line, and connecting the gate of the memory cell transistor to a word line Wherein the other electrode of the memory cell capacitor is connected to a fixed voltage source having an intermediate potential between a power supply potential and a ground potential via switch means controlled by a control signal. It is.

According to a second aspect of the present invention, there is provided a semiconductor memory device according to the first aspect, wherein the switch means is turned on during a read operation, a write operation, and a refresh operation, and the power is turned off. While the power supply is being applied and while the power is being applied, the switch means is turned off.

Further, the semiconductor memory device according to the present invention (claim 3) is the semiconductor memory device according to claim 1, wherein the semiconductor memory device is during a read operation, a write operation, and a refresh operation, and during a standby state when power is applied. Is characterized in that the switch means is turned on and the switch means is turned off while the power is cut off.

According to a fourth aspect of the present invention, in the semiconductor memory device of the first, second, or third aspect, the switch means is turned off immediately before the power is cut off, and the power is turned on again. Is turned on immediately after the is supplied.

According to the semiconductor memory device of the present invention,
When the power is turned off, the plate electrode is brought into a floating state by turning off the switch means. Since the plate electrode itself is made of polysilicon or metal,
Leakage from itself does not cause any problem. Rather, the plate electrode potential decreases toward the ground potential due to the leakage of the switch means (control transistor) or the leakage of the PN junction, but the area of the plate electrode itself increases. Since its capacity is large, its decreasing speed is slow (on the order of 10 to 100 s).

When the data "0" is held, the potential of the storage node is kept at 0 V regardless of whether the power is on or off. As described above, since the rate of decrease in the plate electrode potential is slow, the time during which data "0" information can be retained is much longer than in the conventional Vcc / 2 plate system.

The potential of the storage node when data "1" is held is relatively slow due to the leakage of the memory cell transistor or the PN junction, but is faster than the rate of reduction of the plate electrode potential toward the ground potential. It is going down. Since the potential drop of the storage node is not much different from the case of the conventional Vcc / 2 plate method or the case of the 0 V plate method, the time in which data "1" information can be retained is not much different from the conventional method.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a memory array configuration in a DRAM according to an embodiment of the present invention.

Storage node 2 of memory cell capacitor 1
Are connected to the source of the memory cell transistor 3 and the plate electrode 4 of the memory cell capacitor 1 is commonly connected to the potential (Vcc / 2) via the control transistor 8 which is on / off controlled by the control signal PD. You. The drain of the memory cell transistor 3 is connected to the bit line 5 or the complementary bit line 6, and the memory cell transistor 3
Are connected to the word line 7. The feature is that the control transistor 8 is added to the plate electrode of the memory cell capacitor.

At the time of read, write and refresh operations, an ON control signal PD is applied to the gate of the control transistor 8 to make the transistor 8 conductive, and the fixed voltage Vc is applied to the plate electrode 4 of the memory cell capacitor 1.
Give c / 2. On the other hand, during the power-on standby and the power-off period, an off-control signal PD is applied to the gate of the control transistor 8 to render the transistor 8 non-conductive and the plate electrode 4 of the memory cell capacitor 1 to be in a floating state. . Note that even during standby at power-on, an on-control signal PD is applied to the gate of the control transistor 8 to make the transistor 8 conductive, and the fixed voltage Vcc /
2, the off-control signal PD is applied to the gate of the control transistor 8 only during the power-off period to make the transistor 8 non-conductive and the plate electrode 4 of the memory cell capacitor 1 to be in a floating state. Is also good.

FIG. 2 shows potential changes of the storage node and the plate electrode when the power is turned on / off. When power is applied, the potentials of the storage node (SN ("1")) for data "1" and the storage node (SN ("0")) for data 0 are Vcc and 0V, respectively, and the plate electrode potential Is
Vcc / 2. After the power is turned off, the potential of the plate electrode which has been brought into a floating state by turning off the control transistor 8 decreases toward the ground potential due to the leak of the control transistor 8 or the leak of the PN junction. However, the area of the plate electrode itself is large. Since its capacity is large, its decreasing speed is slow (on the order of 10 to 100 s) as shown in the figure. The potential of the storage node (SN ("1")) of data "1" is relatively slow due to the leakage of the memory cell transistor or the PN junction, but more rapidly toward the ground potential than the decreasing speed of the plate electrode potential. It is going down. The potential of the storage node (SN ("0")) for data "0" is maintained at 0 V regardless of whether the power is on or off.

The potential drop at the storage node for data "1"
Since there is not much difference from the power-off mode of the conventional Vcc / 2 plate system or 0V plate system, the data "
The time during which the "1" information can be retained is not much different from that in the conventional power-off mode, while the time during which the data "0" information can be retained is not much different from that in the conventional 0V plate power-off mode, and The cell information is not destroyed as in the case of the conventional power-off mode of the Vcc / 2 plate system, and since the voltage applied across the cell capacitor is Vcc / 2 at the maximum, the conventional 0 V plate system is not used. The capacitor withstand voltage can be further reduced, the capacitor insulating film thickness can be reduced, the capacitor capacity can be increased, the data retention time of the memory cell can be increased, and the standby current can be reduced.

When the control transistor 8 is turned off after the power is turned off, the potential of the plate electrode drops during that time, and the potential of the storage node for data "0" becomes a negative potential. Immediately before, the control transistor 8 is preferably turned off.

When the power supply returns to the ON state, the control transistor 8 is turned on, the plate electrode is connected to the fixed voltage of Vcc / 2, and the plate electrode potential rises by the amount (ΔV) dropped during power OFF. . Accompanying this, data "1"
The potential of the storage node for data “0” also increases by ΔV due to cell capacitor coupling. As described above, the potential drop of the data "1" storage node during the power-off is faster than the decrease of the plate electrode potential, so that the potential of the data "1" storage node immediately after the power-on is lower than Vcc. Further, the potential of the storage node for data "0" immediately after the power is turned on becomes at least higher than the ground potential. In any case, after the power is turned on, a refresh operation similar to the conventional one is required.

If the timing of turning on the power supply and the timing of turning on the control transistor 8 are too close, the control transistor 8 conducts even though the fixed voltage has not yet reached Vcc / 2, and the plate electrode potential drops. Since the potential of the storage node for data "0" may become a negative potential, it is preferable to turn on the control transistor 8 after the power is completely turned on.

In the standby state at power-on, the data holding time when data "1" is held can be extended even if the plate electrode potential is floated. FIG. 6 shows changes in the potentials of the storage node and the plate electrode in the standby state when the power is turned on. That is, immediately before the standby, the potentials of the storage node for data "1" and the storage node for data "0" are Vcc and 0V, respectively, and the plate electrode potential is Vcc / 2. The potential of the plate electrode which has entered the standby state and has become a floating state due to the turning off of the control transistor 8 gradually decreases, but the leakage current of the PN junction in the negative substrate potential direction and the control from the Vcc / 2 potential. Since the directions of the leak current of the transistor 8 are opposite to each other, the rate of the decrease is slow. The potential of the storage node for data "1" is
It decreases due to the leakage of the memory cell transistor or the PN junction, but the rate of the decrease is equal to the case where the control transistor is in the ON state. Therefore, the standby state is released, the control transistor 8 is turned on, the plate electrode is connected to the potential of Vcc / 2, and the plate electrode potential rises by the amount (ΔV) dropped during standby. Therefore, the potential of the storage node for data “1” also increases by ΔV due to the cell capacitor coupling.
The potential drop at the time of standby is compensated, and the data retention time is substantially lengthened. When the data "0" is held, the potential of the storage node leaks from the bit line precharged to Vcc / 2 through the memory cell transistor 3, and leaks out toward the negative substrate potential due to the PN junction. Therefore, since the potential remains almost at the original ground potential, in either case of turning on / off the control transistor 8,
The data “0” retention time is longer than the data “1” retention time.

[0028]

As described above in detail, according to the present invention, since the memory cell charge retention performance at the time of power-off can be improved, the maximum power-off time can be extended, and the standby time can be improved. The average current consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a memory cell array of a DRAM according to an embodiment of the present invention.

FIG. 2 is a diagram showing a change in potential of a storage node and a plate electrode when power is turned off in the same embodiment.

FIG. 3 is a diagram showing potential changes of a storage node and a plate electrode when power is turned off in a conventional 0V plate system.

FIG. 4 is a diagram showing potential changes of a storage node and a plate electrode when power is turned off in a conventional Vcc / 2 plate system.

FIG. 5 is a diagram showing a memory cell array of a conventional DRAM.

FIG. 6 illustrates a DRAM according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating potential changes of a storage node and a plate electrode during power-on / standby.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell capacitor 2 storage node 3 memory cell transistor 4 plate electrode 5 bit line 6 complementary bit line 7 word line 8 control transistor

Claims (4)

[Claims] 1. A memory cell comprising a memory cell capacitor and a memory cell transistor, a source of the memory cell transistor is connected to one electrode of the memory cell capacitor, and a drain of the memory cell transistor is connected to a bit line. In a semiconductor memory device in which a plurality of memory cells are arranged in a matrix by connecting and connecting the gate of the memory cell transistor to a word line, the other electrode of the memory cell capacitor is controlled by a control signal. A semiconductor memory device which is connected to a fixed voltage source having an intermediate potential between a power supply potential and a ground potential via controlled switch means. 2. The switch means is turned on during a read operation, a write operation and a refresh operation, and the switch means is turned off while power is cut off and while power is applied and in a standby state. 2. The semiconductor memory device according to claim 1, wherein: 3. The switch device is turned on during a read operation, a write operation, and a refresh operation, and while power is applied and in a standby state, and the switch device is turned off while the power is turned off. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is made conductive. 4. The semiconductor memory device according to claim 1, wherein said switch means is turned off immediately before power is turned off, and is turned on immediately after power is turned on again. .