JPH10161953A - System and method for communication control, and decoder device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To return a required response in a short time by discriminating code data from each other when these code data are received. SOLUTION: This system is composed of a transmission/reception contorl part 3 for transferring transmission data to a data decode part 4 and for transferring them to a transmission/reception port 2 according to the instruction of CPU 1 or data decode part 4, data decode part 4 for analyzing the received data transferred from this transmission/reception control part 3 and transferring the result to the transmission/reception control part 3, memory control part 5 for writing the data from the CPU 1 or transmission/reception control part 3 to a memory 6 or transferring data written in the memory 6 to the cPU 1 or transmission/reception control part 3, and memory 6 for storing the received code data or the like. Thus, since time for analyzing a firmware is unnecessitated by analyzing the transmitted data from a host device 7 through a hardware and performing processing due to reply through the hardware, at the time of communication with the host device 7, its response can be performed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a communication control system,
The present invention relates to a communication control method and a decoder device, and more particularly to a communication control system, a communication control method, and a decoder device for performing parallel communication.

[0002]

2. Description of the Related Art Conventionally, a communication control system of this kind selects a condition input with a high priority and controls execution of the selected condition input, as disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 3-247055. The processing for generating the execution code for reading the instructions for the execution is performed by the hardware configuration of the priority order determination means and the condition determination means, respectively, so that the execution control of the communication protocol can be performed at a higher speed than when processing is performed by software. it can. This is suitable for high-speed processing of a communication protocol.

FIG. 5 is a block diagram showing an example of a system described in Japanese Patent Application Laid-Open No. Hei 8-247055. When the execution code is given to the index register 110 by the condition determination unit 121 that determines the priority of a plurality of externally applied condition inputs and generates an execution code that is an address for reading a microinstruction to be executed. , Condition inputs are bit-extended and input to the selector 103. When the bit-expanded condition input is selected by the selector 103, the selected condition input is supplied to the ROM 107 via the address register (ADR) 105.
Thereby, the micro instruction is read from the ROM 107. By generating a control signal from the read data, high-speed communication control is enabled.

As another control system, there is a system shown in FIG. In this system, when reception data transferred from a higher-level device is received by the transmission / reception port 202, the reception data is transferred to the transmission / reception control unit 203. The transmission / reception control unit 203 transfers the received data to the memory control unit 204 by DMA (direct memory access) without passing through the CPU 201. Then, the memory control unit 204 writes data to the memory 205.

[0005] By the above operation, after storing a certain amount of received data in the memory, the CPU 201 reads the data and performs analysis and processing. With the above processing, while data is being received from the host device 202, the CPU 201
Can perform other processing, thereby improving the processing performance of the system.

[0006]

However, in this type of communication control system, as a result of analyzing the data transmitted from the host device by a program, a response is returned to the host device. As a result, there is a problem that it takes time until a response is returned, and that extra program processing is required.

[0007] An object of the present invention is to determine the code data for communication with the host device, particularly when code data for returning a response in a short time after reception is received, thereby determining the required response data. To provide a communication control system, a communication control method, and a decoder device for returning a response in a short time.

[0008]

A communication control system, a communication control method, and a decoder device of the present invention use a central processing means for comprehensively managing the system and a transmission / reception port for transmitting / receiving actual data to / from a higher-level device. And receive data from the transmission / reception port, and transfer the received data at that time to the memory without passing through the central processing unit,
At the same time, the transmission / reception control unit transfers the transmission data to the transmission / reception port according to an instruction of the central processing unit or the data decoding unit, and analyzes the reception data transferred from the transmission / reception control unit, and transmits / receives the result. A data decoding unit for transferring the data from the central processing unit and the transmission / reception control unit to the memory; a memory control unit for transferring the data written to the memory to the central processing unit and the transmission / reception control unit; And a memory for storing code data and the like.

As described above, according to the present invention, the transmission data from the host is analyzed by the hardware, and the processing by the reply is performed by the hardware, so that the time for the analysis of the firmware becomes unnecessary. When communicating with a host device, the response can be performed at high speed.

Further, according to the present invention, data to be analyzed is stored in, for example, a ROM and compared hierarchically, and the processing is notified to the CPU by an interrupt signal. Therefore, analysis of complicated code and data can be easily achieved. Thus, communication control can be performed at high speed without analyzing received data.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a decoder device according to an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.

Referring to FIG. 1, the decoder device of this embodiment includes a CPU 1 serving as a bus master, a transmission / reception port 2 for actually transmitting / receiving data to / from a higher-level device, and a DMA (DMA) for transferring data to a memory 6 without passing through the CPU 1. Direct I memory access), the received data is transferred to the data decoding unit 4 and the memory control unit 5, and the data decoding unit 4
A transmission / reception control unit 3 capable of transferring transmission data from the CPU 1 or transmission data from the CPU 1 to the transmission / reception port 2, a data decoding unit 4 for analyzing data from the transmission / reception control unit 3 and returning the response to the transmission / reception control unit 3, It is composed of a memory control unit 5 for writing data from the CPU 1 and the transmission / reception control unit 3 to the memory and for continuing data stored in the memory, and a memory 6 for actually storing data.

Next, the detailed configuration of the data decoding section 4 of FIG. 1 will be described with reference to FIG. FIG. 2 is a block diagram showing the inside of the data decoding unit 4 of FIG. R in which information for analyzing received data is stored in advance.
OM1, a data analysis unit 12 for analyzing data from the ROM 1, an address generation unit 13 for generating an address to the ROM 4A based on information from the data analysis unit 12 and the transfer control unit 14, and a transfer of received data to the address generation unit 13 The transfer control unit 14 operates a control signal to the host device 7 based on an instruction from the data analysis unit 12, sends out transmission data, and indicates to the CPU 1 by an interrupt signal.

Next, an embodiment of the present invention will be described with reference to FIG. FIGS. 3A to 3G show received data, addresses, transmission data interrupt signals, and the like. In the description of FIG. 3, reference is made to FIGS.

First, when the higher-level device in FIG. 1 outputs, for example, 8-bit width parallel data, the transmission / reception port 2 receives the data (FIG. 3A). Transmission / reception port 2
The received data is transferred to the transmission / reception controller 3. The transmission / reception control unit 3 transfers the received data to the memory control unit 5 by DMA, and also transfers the received data to the data decoding unit 4. The memory control unit 5 receiving the received data stores the received data in the memory 6.

When the data decoding unit 4 receives the received data by the transfer control unit 14 shown in FIG. 2, the data decoding unit 4 transfers the received data, that is, 8-bit data, to the address generation unit 13. The address generation unit 13 sets, for example,
0 is output, and the address data "0000h" is stored in "0000h" of the ROM (FIG. 3B).

Here, the address generation unit 13 which has received the 8-bit data from the transfer control unit 7 outputs it as the lower 8-bit address output of the ROM (FIG. 3C). At this time, the upper 8-bit address of the ROM
The lower 8 bits of the data output by 4A are input (FIG. 3D). That is, the upper 8 bits are “00h”,
The lower 8 bits are the address R1. The data for transmission is T1 (FIG. 3E), and the data transfer direction is switched between the reception and transmission cases (FIG. 3F).

As described above, when the code data R1 is received, the address RA1 on the ROM 4A is read. By storing in advance the processing at the time of receiving the code data of R1 in RA1h of the ROM 4A, it is possible to perform communication with the host device 7 by hardware before the software analyzes it.

For example, when the end bit is 1, the decoding of the received data is interrupted and the CPU of FIG.
1, an interrupt signal (notification of the start of communication processing) is asserted (FIG. 3 (G)), and the transmission / reception control unit 3 sends the transmission data (T1) and the control signal level for communication to 6 bits (CT).
Instruct by S). The transmission / reception control unit 3 includes T1, CTS
, The transmission of the transmission data and the control of the control signal are performed.

Next, receiving several bytes of code data
The case of the operation at the time of analysis will be described with reference to FIG. FIG. 4 is a diagram showing an example of using ROM data.

The data decoding of the first byte (8 bits) performs the same processing as described above. However,
"0" is stored in the end bit and "1" is stored in the next code search bit in FIG. The address generator 13 outputs an upper address of 01h from the search bit.

When receiving the next received data R2, the ROM address RS2 of the lower byte R2 and the upper byte 01h is output. Similarly, when the end bit “0” and the next code search bit “1” are stored in RS2, the address generation unit 13 increments the above-mentioned “01h” by one and adds the upper address “02h”. Output. In this way, the code is searched for the third and fourth bytes. Then, on the fourth byte ROM address RS4,
The data is transferred to the transmission / reception control unit 3 based on the end bit = 1, the next code search bit = 0, the transmission bit = 1, and the transmission data = T1.

Also, by storing "0000h" in all addresses not to be searched in the ROM 1, if an untargeted code is transmitted to the third byte, RO
M1 outputs "0000h", the data decoding is reset, and the search from the first byte is started again.

The decoder device of the embodiment described above is
The CPU 1, which performs overall management of the system, transmits / receives actual data to / from a higher-level device through a transmission / reception port, retrieves data from the transmission / reception port, and transfers the received data at that time to the memory without passing through the CPU1. At the same time, the transmission / reception control unit 3 transfers the transmission data to the transmission / reception port in accordance with an instruction from the CPU 1 or the data decoding unit 4, and analyzes the reception data transferred from the transmission / reception control unit 3, A data decoding unit 4 for transferring the result to a transmission / reception control unit 3;
1 and the data from the transmission / reception control unit 3 are written in the memory 6, and the data written in the memory 6 is
It comprises a memory control unit 5 for transferring to the transmission / reception control unit 3, and a memory 6 for storing received code data and the like.

In the above embodiment, the transmission data from the host is analyzed by the hardware, and the processing by the reply is performed by the hardware, so that the time for the analysis of the firmware is not required. During the communication, the response can be performed at high speed. In addition, data to be analyzed is stored in, for example, a ROM, compared hierarchically, and the processing is notified to the CPU by an interrupt signal.
Since the confirmation of the processing can be easily performed by switching the switch, the analysis of complicated code / data can be easily achieved. Thus, communication control can be performed at high speed without analyzing received data.

[0026]

As described above, according to the present invention, the transmission data from the upper layer is analyzed by hardware, and the processing by the reply is performed by hardware, so that the time for analyzing the firmware is not required. Therefore, the response can be performed at high speed when communicating with the host device.

According to the present invention, the data to be analyzed is stored in, for example, a ROM and compared hierarchically, and the processing is notified to the CPU by an interrupt signal. Therefore, analysis of complicated code and data can be easily achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of a communication control system, a communication control method, and a decoder device of the present invention.

FIG. 2 is a block diagram illustrating the inside of a data decoding unit according to the embodiment;

FIGS. 3A to 3G are timing diagrams showing received data, addresses, transmission data interrupt signals, and the like.

FIG. 4 is a diagram showing a usage example of ROM data.

FIG. 5 is a block diagram illustrating a configuration example of a conventional communication control system.

FIG. 6 is a block diagram illustrating a configuration example of a conventional communication control system.

[Explanation of symbols]

 Reference Signs List 1 CPU 2 transmission / reception board 3 transmission / reception control unit 4 data decoding unit 4A ROM 5 memory control unit 6 memory 7 host device 12 data analysis unit 13 address generation unit 14 transfer control unit

Claims (6)

[Claims] 1. A communication control system having data transmission / reception means for performing parallel communication with a higher-level device, a central processing means for comprehensively managing the system, and a real-time data transmission / reception with the higher-level device. Performed by the sending and receiving port, taking data from the sending and receiving port,
Transmission / reception control means for transferring the reception data at that time without passing through the central processing means, a memory control means operated by a control signal from the transmission / reception control means, and a control signal from the transmission / reception control means A communication control system comprising: data decoding means for decoding data; and storage means for storing the data according to a memory control signal from the memory control means. 2. In accordance with an instruction signal from the central processing means or the data decoding means, transmission data is transferred to the transmission / reception port, the transferred reception data is analyzed, and the result is transferred to the transmission / reception control means. The communication control system according to claim 1, wherein: 3. An output data from the data decoding means or the central processing means is written in the storage means, and the data written in the storage means is transferred to the central processing means or the transmission / reception control means. The communication control system according to claim 1 or 2, wherein 4. A communication control system comprising: a data transmission / reception unit for performing parallel communication with a host device; and a control unit for controlling data transmission / reception of the transmission / reception unit. Performed by the sending and receiving port, taking data from the sending and receiving port,
A communication control method, comprising: transferring received data at that time without passing through the control unit; decoding the data; and storing the data. 5. A step of transferring transmission data to the transmission / reception port in response to an instruction signal from the control means, a step of analyzing the transferred reception data, and a step of transferring the result to the transmission / reception means; The communication control method according to claim 4, further comprising: writing a control output from the control unit; and transferring the written data to the control unit. 6. A decoder device having data transmitting / receiving means for performing parallel communication with a higher-level device, a central processing means for comprehensively managing a system, and transmitting and receiving actual data with the higher-level device. Port, take data from the send / receive port,
Transmission / reception control means for transferring the reception data at that time without passing through the central processing means, memory control means operated by a control signal from the transmission / reception control means, and receiving the reception data from the transmission / reception port Transfer means for transferring the received data at that time without passing through the central processing means; and data decoding means for decoding the received data by a control signal from the transmission / reception control means. Decoder device.