JPH10161159A - Production of liquid crystal display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the compatibility of holding of an aperture ratio with the improvement in signal holdability and to improve the display performance of a high-fineness display by forming pixel electrodes in such a manner that these pixels are connected to the exposed parts of semiconductor layers which are source and drains and the exposed parts of first electrodes on second insulating films. SOLUTION: Gate oxidized films 22 and dielectric insulating films 26 are formed on the surface by a thermal oxidation method and the conductive polycrystalline silicon layers existing under the dielectric insulating films 26 are formed as lower electrodes 42. Gate electrodes 8 and upper electrodes 105 are formed thereon. Phosphorus are implanted with the gate electrodes 8 as a mask to form the sources 10 and drains 12 of TFTs. Interlayer insulating films 24 are thereafter deposited, following which the interlayer insulating films 24 are etched away so as to form the exposed parts 12a of the drains 12 and the exposed parts 42a of the lower electrodes 42. Transparent electrodes 20 are deposited inclusive of these opening parts and are formed to the state in conductive contact with both exposed parts 12a, 42a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel comprising a thin film transistor (hereinafter, referred to as TFT) array and a method of manufacturing the same, and more particularly, to a display density and contrast of the display body. The present invention relates to a technique for achieving an improvement in display performance of a display.

[0002]

2. Description of the Related Art An active matrix liquid crystal display panel using a TFT array has a large number of scanning lines due to a large ON / OFF resistance ratio of a TFT and does not require a capacitor for charge storage. Attention has been paid to the fact that large area and mass production are easy, and R & D has been actively carried out.

In this liquid crystal display panel, a gate line for transmitting a scanning signal and a data line for supplying an image signal are arranged in a grid pattern in a horizontal direction and a vertical direction, respectively, and each pixel region is partitioned by these grids. A TFT used as a potential supply switch and a pixel electrode for applying a potential to the liquid crystal are formed. The liquid crystal is provided between the pixel electrode and a common electrode facing the pixel electrode.

Here, the gate electrode of the TFT is connected to the gate line, the source is connected to the data line, and the drain is connected to the pixel electrode. When the TFT is turned on based on a scanning signal input from the gate line. Then, an image signal is introduced from the data line, a predetermined potential is applied to the pixel electrode, and a potential difference is generated between the pixel electrode and the common electrode to drive the liquid crystal.

However, the liquid crystal panel has been increasingly finer in recent years, and the display capacity of the pixel region has been reduced due to the miniaturization of the area of each pixel region. Even so, the display voltage is reduced during the non-selection period (one field period) of the gate line, and the display performance such as the contrast of the liquid crystal panel is deteriorated and the S / N ratio is deteriorated.

[0006] This problem is solved by forming a charge storage capacitor in each pixel region. In a liquid crystal display panel using a TFT array, for example, a conductive layer formed on the front side of a silicon substrate and the conductive layer are formed. Unlike the case of a MOS-FET array in which a charge storage capacitor can be easily formed from an insulating film and a conductive layer formed on the surface of a substrate, a TFT is formed on an insulator such as a glass substrate. The charge storage capacitor cannot be easily formed. Therefore, a MOS structure having the same structure as the TFT is formed in each pixel region, and a high bias is applied thereto to make the surface of the intrinsic silicon layer conductive, thereby forming a MOS capacitor, which is used as a charge storage capacitor. I was

[0007]

However, in the above-mentioned liquid crystal panel, it is necessary to constantly apply a high voltage of about 20 V in order to form a MOS capacitor, and this high electric field causes dielectric breakdown or the like. There is a problem that the reliability is reduced and the leak current is increased, and the effect of the charge storage capacitor formed at an angle is reduced.

The formation of the charge storage capacitor is particularly effective in the case of a TFT array liquid crystal display used as a transmission type display, in which the aperture ratio of the liquid crystal display (the ratio of the area through which light can be transmitted to the entire panel area). ), Which directly leads to a decrease in display performance. In addition, the aperture ratio may be further reduced due to the formation of the high voltage supply line necessary for forming the MOS capacitor. It was a major obstacle to development.

Accordingly, the present invention is to solve the above-mentioned problems, and an object of the present invention is to form a small-area large-capacity charge storage capacitor which does not require a high voltage supply while utilizing a TFT manufacturing process. By achieving a multi-layered structure, it is possible to maintain both the aperture ratio and the signal retention characteristics,
It is to improve the display performance of a high definition display.

[0010]

In order to solve the above problems, a thin film transistor having a source electrically connected to a data line and a gate electrically connected to a gate line, and a pixel electrode electrically connected to a drain of the thin film transistor. And a lower electrode to which a drain potential is applied, an upper electrode to which another potential is applied, and a pixel region including a charge storage capacitor having a dielectric insulating film formed therebetween. The means taken by the invention is that the upper electrode
The potential of the adjacent gate line adjacent to the gate line, that is, the potential of the preceding or subsequent scanning line is applied.

Here, there is a case where the upper electrode is formed as an adjacent gate line itself, the lower electrode is formed directly below the upper electrode via a dielectric insulating film, and a connection portion for applying a drain potential to the lower electrode itself is provided. Yes, this connection is connected to the drain or pixel electrode.

When the connection portion of the lower electrode is connected to the drain, it is desirable to form the lower electrode below the data line or the data line adjacent thereto.

In these means, the lower electrode may be formed of a conductive polycrystalline silicon layer, or may be formed of a metal layer.

Next, as a method of manufacturing the liquid crystal display panel, a step of forming an active layer and a lower electrode of the thin film transistor, a step of simultaneously forming a gate insulating film and a dielectric insulating film of the thin film transistor, And a step of simultaneously forming an upper electrode and a step of forming a source and a drain by making the active layer conductive using the gate as a mask. Here, in the step of forming the active layer and the lower electrode of the thin film transistor, the active layer may be formed of intrinsic polycrystalline silicon, and the lower electrode may be formed of conductive polycrystalline silicon. In this case, the intrinsic polycrystalline silicon layer may be formed. After that, it is preferable that a part of the intrinsic polycrystalline silicon layer be made conductive to form a lower electrode and the remaining part be an active layer. In some cases, the active layer is formed of intrinsic polycrystalline silicon, and the lower electrode is formed of a metal layer.

Further, in the above means, the active layer and the lower electrode are formed apart from each other, the active layer is made conductive using the gate as a mask to form a source and a drain, and then the exposed portion of the drain and the exposed portion of the lower electrode are formed. The pixel electrodes are formed in a conductive contact state thereon.

In each of the above means, the step of simultaneously forming the gate insulating film and the dielectric insulating film of the thin film transistor is preferably performed by a thermal oxidation method.

[0017]

According to this means, since the charge storage capacitor having the lower electrode is formed, it is possible to store an electric charge by applying an arbitrary potential to the upper electrode with respect to the drain potential applied to the lower electrode. Becomes Here, the selection period in which the pulse signal is introduced to the gate potential in the pixel region to which the charge storage capacitor belongs is a non-selection period for the adjacent pixel region, and the reference potential is applied to the adjacent gate line. Therefore, by applying the potential of the adjacent gate line to the upper electrode, charges are accumulated between the upper electrode and the lower electrode,
The retention characteristics of the liquid crystal applied voltage during the non-selection period in the pixel region can be improved.

Since the potential is applied to the upper electrode of the charge storage capacitor by the adjacent gate line, there is no need to provide a separate potential supply line, which contributes to an improvement in the opening ratio of the liquid crystal panel.

When the upper electrode is the adjacent gate line itself and a dielectric insulating film and a lower electrode are formed immediately below the adjacent gate line itself, it is not necessary to newly form a charge storage capacitor forming surface in the pixel region. Can be prevented from decreasing. In this case, however, it is necessary to form a connection portion for applying the drain potential of the TFT to the lower electrode. By forming this connection portion below the data line, the aperture ratio based on the area occupied by the connection portion is reduced. Reduction can be suppressed.

Further, when the connection portion is conductively connected to the pixel electrode, the lower electrode is indirectly connected to the drain of the TFT because a drain potential is applied to the pixel electrode. In this case, since the pixel electrode is formed on the entire surface of the pixel region, the area occupied by the connection portion can be almost eliminated.

Next, as a method of manufacturing a liquid crystal display panel, an active layer and a lower electrode of a thin film transistor are formed, and then a gate insulating film and a dielectric insulating film of the thin film transistor are simultaneously formed, thereby forming a dielectric insulating film of a charge storage capacitor. Can be formed with the same thickness and the same quality as the gate insulating film of the TFT. Normally, the gate insulating film needs to be formed extremely thin and of high quality as compared with the interlayer insulating film and the like. Is thinner, the capacitance value becomes larger, and the high quality thereof can reduce the leak current.

According to the present manufacturing method, the TFT
It is possible to appropriately create charge storage capacitors in a liquid crystal display panel consisting of an array with a minimum number of manufacturing steps. In particular, the lower electrode made of conductive polycrystalline silicon and the active electrode made of intrinsic polycrystalline silicon When the layers are formed separately in advance and the pixel electrodes are formed in a conductive contact state on these exposed portions, lateral diffusion of conductive impurities from the lower electrode to the active layer cannot occur structurally. In addition, it is possible to prevent the off-resistance value from increasing due to the intrusion of impurities into the TFT channel region. This method has a particularly remarkable effect in preventing thermal diffusion due to heating when the gate insulating film is formed by a thermal oxidation method.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view of a liquid crystal display panel according to the present invention.
FIG. 2 is a plan view of the embodiment, FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III of FIG. This embodiment is shown in FIG.
, Vertical data lines 4a, 4b,.
And the gate lines 6a, 6b,... Extending in the horizontal direction are arranged in a grid pattern, and pixel regions 2aa, 2ab,.

The internal structure of the pixel region 2aa will be described below as an example. In the pixel region 2aa, a TF including a gate electrode 8 extending from the gate line 6a, a source 10 connected to the data line 4a, and a drain 12 is provided.
T is formed, a lower electrode 18 is connected to the drain 12 via a connection layer 16, and a gate line 6 b of the previous stage is formed above the lower electrode 18. In addition, over these structures, ITO is formed over almost the entire pixel region 2aa.
Is formed, and this transparent electrode 20 is also connected to the drain 12 of the TFT through the opening.

FIG. 2 shows a cross section of the structure of the TFT. A polycrystalline silicon layer is deposited on the surface of a transparent glass substrate 1 which supports the entire liquid crystal panel. Except for the channel region 14, phosphorus is introduced as an n-type conductivity type impurity into the source 10 and the drain 12. A gate oxide film 22 having a thickness of 1000 to 1500 ° is formed thereon, and a gate electrode 8 is formed of conductive polycrystalline silicon. On these, an interlayer insulating film 24 having a thickness of 0.5 to 1.0 μm is deposited, and the interlayer insulating film 24 is opened to form a data line 4 a connected to the source 10 and a transparent electrode 20 connected to the drain 12.
Are formed. Here, a connection layer 16 made of conductive polycrystalline silicon contacts the lower layer of the drain 12.

On the other hand, the cross section of the charge storage capacitor forming region formed below the gate line 6b is as shown in FIG. On a rectangular lower electrode 18 formed of a conductive type polycrystalline silicon layer on a glass substrate 1, there is a dielectric insulating film 26 formed simultaneously with the gate oxide film 22 of the TFT. Are formed in the same direction as the extension direction of the lower electrode 18. On these, a part of the transparent electrode 20 exists via an interlayer insulating film 24.

Since the liquid crystal display panel has a charge storage capacitor having a lower electrode 18 and an upper electrode formed of conductive polycrystalline silicon, the liquid crystal display panel has a high liquid crystal bias voltage holding capacity during a non-selection period. The display characteristics are improved. Here, the capacitance value of the liquid crystal itself in each pixel region in this embodiment is 14 to 35 × 10 ⁻¹⁵ F, and the value of the charge storage capacitance is 300 × 10 10 ⁻¹⁵ F or more.

In this embodiment, the transmission type (the transmittance of the liquid crystal in each pixel area is changed based on the image signal introduced to the data line, and an image is formed and displayed by the distribution of the amount of transmission of the backlight light. ), The potential supply wiring of the charge storage capacitor is not required, and since the upper electrode is formed by the gate line 6a itself, the transmission area is not reduced by the charge storage capacitor. Only the formation of the connection layer 16 causes a decrease in the aperture ratio as compared with the liquid crystal panel in which the charge storage capacitor is not formed. Therefore, in this embodiment, the aperture ratio with respect to the entire display area could be kept at 36.2%.

Next, a second embodiment of the liquid crystal display panel according to the present invention will be described with reference to FIGS. This embodiment is almost the same as the first embodiment, and the same portions are denoted by the same reference numerals and description thereof will be omitted.

In the planar structure of this liquid crystal display panel, as shown in FIG. 4, a part of a connection layer 16 connecting the drain 12 and the lower electrode 18 is formed below the adjacent data line 4b. The aperture ratio of the liquid crystal panel is higher than in the first embodiment. Note that, as shown in FIG.
b and the data line 4b
The interlayer insulating film 24 which is sufficiently thicker than the dielectric insulating film 26 is formed between the connection layer 16 and the data line 4.
The capacitance between b and n has almost no effect on the charge storage capacitance.

The connection portion between the connection layer 16 and the drain 12 can be formed at any portion on the path from the drain 12 to the lower electrode 18 in FIG.

Another embodiment other than the first and second embodiments will be described with reference to FIGS. 6 to 8, which schematically show cross sections of a TFT structure portion and a charge storage capacitor portion. First, in FIG. 6, a metal electrode 38 is formed in place of the lower electrode 18 and the connection layer 16 and can be made of Al or a high melting point metal. FIG. 7 shows a structure in which the portion from the drain 12 of the TFT to the connection layer 16 and the lower electrode 18 is formed by an integral polycrystalline silicon layer 40. Further, FIG. 8 shows an example in which the lower electrode 42 is directly connected to the transparent electrode 20 which is in conductive contact with the drain 12 of the TFT without forming the connection layer 16. According to this example, the lower electrode 4
It is only necessary to form a portion slightly protruding from immediately below the gate line 6b, which is the upper electrode, so that the connection portion can be made extremely small in area, and the reduction in the aperture ratio can be almost completely eliminated. Can be.

In the embodiments shown in FIGS. 4 and 5, and the embodiment shown in FIG. 6, the drain 12 covers the whole or a part of the connection layer 36, the lower electrode 18 and the metal electrode 38, respectively. It may have a structure.

Next, an embodiment of a method for manufacturing a liquid crystal panel according to the present invention will be described.

FIG. 9 is a process sectional view for explaining the first embodiment of this manufacturing method. First, as shown in FIG. 9A, a polycrystalline silicon layer doped with phosphorus is deposited on the surface of a glass substrate 1 by a CVD method to form a lower electrode 18. Next, as shown in FIG. 9B, an intrinsic polycrystalline silicon layer 103 is deposited so as to be in contact with the connection layer 16 of the lower electrode 18 and, as shown in FIG. These are similarly covered with a silicon oxide film 104 by the CVD method. Here, the polycrystalline silicon layer 103 may be formed so as to cover all or a part of the lower electrode 18. Thereafter, as shown in FIG. 9D, the gate electrode 8 of the TFT and the upper electrode 105 of the charge storage capacitor are formed of phosphorus-doped polycrystalline silicon by the CVD method, and phosphorus or phosphorus is self-aligned using the gate electrode 8 as a mask. Arsenic ions are implanted, and the TFT source 10 and drain l
Form 2 Thereafter, as shown in FIG.
An interlayer insulating film 24 is deposited and formed on the entire surface by the method shown in FIG.
As shown in (f), the drain l of the interlayer insulating film 24 is formed.
An opening is provided at a position above the pixel region 2 so that the I
A transparent electrode 20 made of TO is formed by a sputtering method. Finally, as shown in FIG.
The data line 4a connected to the source 10 of the TFT through the opening 4 is covered with Al.

In this manufacturing method, the lower electrode 18
Can have various planar shapes depending on the position where the charge storage capacitor is formed in the pixel region. Also, the upper electrode 105
Also, various shapes can be taken according to the planar shape of the lower electrode 18. In particular, as in the above-described embodiment of the liquid crystal panel, the upper electrode 105 may be the gate line 6 b itself.

In this embodiment, the gate oxide film 22 and the dielectric insulating film 26 are formed simultaneously, and the gate electrode 8 and the upper electrode 1 are formed.
Since the layers 05 are formed at the same time, an increase in the number of steps can be suppressed to a minimum. Further, since the dielectric insulating film 26 necessarily has the same thickness as the thin gate oxide film, the capacitance value of the charge storage capacitor can be made larger than the occupied area.

Next, a second embodiment of the method for manufacturing a liquid crystal panel will be described with reference to FIG. In this embodiment, first,
As shown in FIG. 10A, an intrinsic polycrystalline silicon layer 106 is formed on a glass substrate 1, and as shown in FIG. 9B, a silicon oxide film 107 is deposited thereon by a CVD method. A part of this is covered with a resist layer 108 and phosphorus ions are implanted to form an intrinsic polycrystalline silicon layer 10.
A part of 6 is a lower electrode 18. Thereafter, as shown in FIG. 9C, a gate electrode 8 and an upper electrode 105 are formed in the same manner as in the first embodiment, and ions are implanted in the same manner as in the first embodiment to form a source 10 and a drain 12. Form. Here, it is also possible to form the silicon oxide layer 107 by a thermal oxidation method. In this case, the boundary between the planned drain region of the TFT and the planned channel region, and the tip of the lower electrode 18 on the planned drain region side. Is required to be at least 10 μm or more in order to prevent lateral diffusion accompanying heating. After this step, the liquid crystal panel is completed by forming the interlayer insulating film 24, the transparent electrode 20, and the data lines 4a as in the first embodiment.

This embodiment is characterized in that an integral polycrystalline silicon layer 106 is formed in advance and then formed on both the lower electrode and the active layer of the TFT, and the number of steps does not change. However, there is no step in the connection between the lower electrode 18 and the drain 12 as in the first embodiment.

Finally, a third embodiment of the manufacturing method according to the present invention will be described with reference to FIG. In this embodiment, first, as shown in FIG. 11 (a), an intrinsic polycrystalline silicon layer 107 separated from each other in advance on the surface of a glass substrate l
And a conductive polycrystalline silicon layer 108 is formed. In this formation method, an intrinsic polycrystalline silicon layer may be formed by separating two by a CVD method and phosphorus may be introduced into only one of them, or an undoped layer and a doped layer may be separately formed by a CVD method. What you do. Next, as shown in FIG. 11 (b),
A gate oxide film 22 and a dielectric insulating film 26 are formed on these surfaces by a thermal oxidation method, and a conductive polycrystalline silicon layer below the dielectric insulating film 26 is used as a lower electrode 42. Further, the l
1C, a gate electrode 8 and an upper electrode 105 are formed thereon, and phosphorus is implanted using the gate electrode 8 as a mask to form a source 10 and a drain 12 of the TFT. Thereafter, after the interlayer insulating film 24 is deposited, the interlayer insulating film 24 is removed by etching so as to form the exposed portion 12a of the drain 12 and the exposed portion 42a of the lower electrode 42, as shown in FIG. The transparent electrode 20 is applied to the exposed portions 12a and 42a in a conductive contact state, including the opening.

In this embodiment, even if heating by thermal oxidation is performed, since the active layer of the TFT and the lower electrode 42 are completely separated from each other, the lateral diffusion from the lower electrode to the TFT active layer is performed. Therefore, the process can be designed without considering deterioration of TFT characteristics (particularly, decrease in off-resistance value) due to diffusion. Therefore, since the film quality of the gate oxide film 22 and the dielectric insulating film 26 can be improved by adopting the thermal oxidation method and performing high-temperature processing, the leakage current of the liquid crystal panel can be reduced. Thus, it can contribute to further improvement of display characteristics.

In each of the embodiments of the liquid crystal panel or the method of manufacturing the same, the gate electrode, the gate line, and the data line may have a polycide structure, or a salicide technique may be employed in these forming steps. Further, the gate electrode and the gate line can be formed in different steps. In particular, the gate electrode can be formed of polycrystalline silicon or polycide, and the gate line can be formed of refractory metal silicide.

[0044]

As described above, the present invention relates to a TFT
A liquid crystal display panel having an array has a charge storage capacitor having an upper electrode to which an adjacent gate line potential is applied. In particular, the liquid crystal display panel is characterized in that the adjacent gate line itself is used as the upper electrode. The method is characterized in that the dielectric insulating film is formed simultaneously with the gate insulating film after the formation of the lower electrode, and the upper electrode is formed simultaneously with the gate electrode, so that the following effects are obtained.

By forming the lower electrode, TF
Even in a liquid crystal panel having a T array, it is possible to operate the charge storage capacitor without applying a high voltage, and it is not necessary to add a potential supply wiring by applying a potential of an adjacent gate line. Therefore, it is possible to cause the charge storage capacitor having a small leak current to function with high reliability while suppressing a decrease in the aperture ratio, and to improve display characteristics of the high definition display panel.

When the upper electrode is the adjacent gate line itself, it is possible to avoid a decrease in aperture ratio due to the area occupied by the charge storage capacitor.

In the case where a connection portion for applying a TFT drain potential to the lower electrode is provided, the lowering of the aperture ratio due to the connection portion can be suppressed by arranging this connection portion below the data line.

When the lower electrode is directly connected to the pixel electrode, the area occupied by the connection portion can be made almost unnecessary, and the decrease in the aperture ratio can be almost completely prevented.

When the gate insulating film and the dielectric insulating film are formed simultaneously after the formation of the lower electrode, and the gate electrode and the upper electrode are simultaneously formed, the TFTs can be formed by a small number of steps.
A charge storage capacitor can be built in a liquid crystal display panel having an array. The charge storage capacitor in the liquid crystal panel formed by this manufacturing method does not require application of a high potential, so that the reliability of driving the liquid crystal can be improved.

In the case where the lower electrode of the charge storage capacitor is formed separately from the active layer of the TFT in advance and the pixel electrode is formed so as to be in contact with the drain of the TFT and the exposed portion of the lower electrode, a heating step is required. Since the lateral diffusion from the lower electrode to the TFT active layer can be completely shut off, deterioration of the TFT characteristics can be prevented, and the process design becomes easy. In particular, the gate insulating film and the dielectric insulating film are formed by the thermal diffusion method. When a is formed, high-temperature processing can be performed, so that a high-quality insulating film can be obtained, and further improvement in display characteristics can be expected.

[Brief description of the drawings]

FIG. 1 is a plan view showing the structure of a first embodiment of a liquid crystal display panel according to the present invention.

FIG. 2 is a cross-sectional view showing a state cut along the line II-II in FIG.

FIG. 3 is a cross-sectional view showing a state cut along the line III-III in FIG. 1;

FIG. 4 is a plan view showing a structure of a second embodiment of the liquid crystal display panel according to the present invention.

FIG. 5 is a cross-sectional view showing a state cut along line VV in FIG. 4;

FIG. 6 is a schematic sectional view showing different embodiments of the liquid crystal display panel according to the present invention.

FIG. 7 is a schematic sectional view showing different embodiments of the liquid crystal display panel according to the present invention.

FIG. 8 is a schematic sectional view showing different embodiments of the liquid crystal display panel according to the present invention.

FIGS. 9A to 9G are cross-sectional views illustrating a first embodiment of a method of manufacturing a liquid crystal display panel according to the present invention.

FIGS. 10A to 10D are process cross-sectional views showing a second embodiment of the method for manufacturing a liquid crystal display panel according to the present invention.

FIGS. 11A to 11D are process cross-sectional views showing a third embodiment of the method for manufacturing a liquid crystal display panel according to the present invention.

[Explanation of symbols]

 1 ... Glass substrate 2aa ... Pixel region 4a, 4b ... Data line 6a, 6b ... Gate line 8 ... Gate electrode 10 ... Source 12 ... Drain 14 ... Channel region 16, 36 connection layer 18, 42 lower electrode 20 transparent electrode 22 gate oxide film 24 interlayer insulating film 26 dielectric insulating film 38 metal electrode 40 , 109: conductive polycrystalline silicon layer 103, 106, 107: intrinsic polycrystalline silicon layer 104: silicon oxide layer 105: upper electrode

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[Procedure amendment]

[Submission date] December 18, 1997

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Patent application title: Method for manufacturing liquid crystal display panel

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[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel comprising a thin film transistor (hereinafter, referred to as TFT) array and a method of manufacturing the same, and more particularly, to a display density and contrast of the display body. The present invention relates to a technique for achieving an improvement in display performance of a display.

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[0010]

In order to solve the above problems, the present invention provides a data line on a substrate, a gate line crossing the data line, and a transistor connected to the data line and the gate line. A method of manufacturing a liquid crystal display panel having a charge storage capacitor electrically connected to the transistor, wherein a semiconductor layer serving as a source / drain of the transistor and a semiconductor layer serving as a first electrode of the charge storage capacitor are the same. Forming a gate insulating film of the transistor and a first insulating film serving as a dielectric film of the charge storage capacitor with the same material; and forming a gate electrode of the transistor and the charge Second of storage capacity
Forming an electrode with the same material; forming a second insulating film on the gate electrode and the second electrode; and forming one of the semiconductor layer serving as the source / drain and the semiconductor layer serving as the first electrode. Exposing a portion, and forming a pixel electrode on the second insulating film so as to be connected to the exposed portion of the semiconductor layer serving as the source / drain and the exposed portion of the first electrode. It is characterized by.

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FIG. 1 is a sectional view of a liquid crystal display panel according to the present invention.
FIG. 2 is a cross-sectional view showing a state cut along the line II-II of FIG. 1, and FIG. 3 is a cross-sectional view showing a state cut along the line III-III of FIG. This reference example is shown in FIG.
, Vertical data lines 4a, 4b,.
And the gate lines 6a, 6b,... Extending in the horizontal direction are arranged in a grid pattern, and pixel regions 2aa, 2ab,.

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In this embodiment, the transmission type (the transmittance of the liquid crystal on each pixel area is changed based on the image signal introduced to the data line, and an image is formed and displayed by the distribution of the amount of transmission of the backlight light. ), The potential supply wiring of the charge storage capacitor is not required, and since the upper electrode is formed by the gate line 6a itself, the transmission area is not reduced by the charge storage capacitor. Only the formation of the connection layer 16 causes a decrease in the aperture ratio as compared with the liquid crystal panel in which the charge storage capacitor is not formed. Therefore, in this reference example, the aperture ratio with respect to the entire display area could be kept at 36.2%.

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Next, a second embodiment of the liquid crystal display panel according to the present invention will be described with reference to FIGS. This reference example is substantially the same as the first reference example, and the same portions are denoted by the same reference numerals and description thereof will be omitted.

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In the planar structure of this liquid crystal display panel, as shown in FIG. 4, a part of a connection layer 16 connecting the drain 12 and the lower electrode 18 is formed below the adjacent data line 4b. l The aperture ratio of the liquid crystal panel is higher than that of the reference example. Note that, as shown in FIG.
b and the data line 4b
The interlayer insulating film 24 which is sufficiently thicker than the dielectric insulating film 26 is formed between the connection layer 16 and the data line 4.
The capacitance between b and n has almost no effect on the charge storage capacitance.

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Another reference example other than the first and second reference examples is shown in FIGS. 6 and 7 which schematically show cross sections of a TFT structure portion and a charge storage capacitor portion. An embodiment of the present invention is shown in FIG. First, FIG. 6 shows the lower electrode 18
In addition, a metal electrode 38 is formed instead of the connection layer 16 and Al or a high melting point metal can be used as a material. FIG. 7 shows a case where the connection layer l is connected to the drain 12 of the TFT.
6, the lower electrode 18 is formed by an integral polycrystalline silicon layer 40. Further, FIG. 8 of this embodiment shows an example in which the lower electrode 42 is directly connected to the transparent electrode 20 that is in conductive contact with the drain 12 of the TFT without forming the connection layer 16. According to this example, it is only necessary to form a portion in which the lower electrode 42 slightly protrudes from immediately below the gate line 6b serving as the upper electrode, so that the connection portion can have an extremely small area, and the aperture ratio can be reduced. The drop can be almost completely eliminated.

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[Correction target item name] 0034

[Correction method] Change

[Correction contents]

In the embodiment shown in FIGS. 4 and 5, and the reference example shown in FIG. 6, the drain 12 covers the whole or a part of the connection layer 36, the lower electrode 18 and the metal electrode 38, respectively. It may have a structure.

[Procedure amendment 23]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction contents]

FIG. 9 is a process sectional view for explaining a first reference example of this manufacturing method. First, as shown in FIG. 9A, a polycrystalline silicon layer doped with phosphorus is deposited on the surface of a glass substrate 1 by a CVD method to form a lower electrode 18. Next, as shown in FIG. 9B, an intrinsic polycrystalline silicon layer 103 is deposited so as to be in contact with the connection layer 16 of the lower electrode 18 and, as shown in FIG. These are similarly covered with a silicon oxide film 104 by the CVD method. Here, the polycrystalline silicon layer 103 may be formed so as to cover all or a part of the lower electrode 18. Thereafter, as shown in FIG. 9D, the gate electrode 8 of the TFT and the upper electrode 105 of the charge storage capacitor are formed of phosphorus-doped polycrystalline silicon by the CVD method, and phosphorus or phosphorus is self-aligned using the gate electrode 8 as a mask. Arsenic ions are implanted, and the TFT source 10 and drain l
Form 2 Thereafter, as shown in FIG.
An interlayer insulating film 24 is deposited and formed on the entire surface by the method shown in FIG.
As shown in (f), the drain l of the interlayer insulating film 24 is formed.
An opening is provided at a position above the pixel region 2 so that the I
A transparent electrode 20 made of TO is formed by a sputtering method. Finally, as shown in FIG.
The data line 4a connected to the source 10 of the TFT through the opening 4 is covered with Al.

[Procedure amendment 24]

[Document name to be amended] Statement

[Correction target item name] 0037

[Correction method] Change

[Correction contents]

In this manufacturing method, the lower electrode 18
Can have various planar shapes depending on the position where the charge storage capacitor is formed in the pixel region. Also, the upper electrode 105
Also, various shapes can be taken according to the planar shape of the lower electrode 18. In particular, as in the above-described reference example of the liquid crystal panel, the upper electrode 105 may be the gate line 6 b itself.

[Procedure amendment 25]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction contents]

In this embodiment, the gate oxide film 22 and the dielectric insulating film 26 are formed simultaneously, and the gate electrode 8 and the upper electrode 1 are formed.
Since the layers 05 are formed at the same time, an increase in the number of steps can be suppressed to a minimum. Further, since the dielectric insulating film 26 necessarily has the same thickness as the thin gate oxide film, the capacitance value of the charge storage capacitor can be made larger than the occupied area.

[Procedure amendment 26]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction contents]

Next, a second reference example of a method for manufacturing a liquid crystal panel will be described with reference to FIG. In this reference example,
As shown in FIG. 10A, an intrinsic polycrystalline silicon layer 106 is formed on a glass substrate 1, and as shown in FIG. 9B, a silicon oxide film 107 is deposited thereon by a CVD method. A part of this is covered with a resist layer 108 and phosphorus ions are implanted to form an intrinsic polycrystalline silicon layer 10.
A part of 6 is a lower electrode 18. Thereafter, as shown in FIG. 9C, a gate electrode 8 and an upper electrode 105 are formed in the same manner as in the first embodiment, and ions are implanted in the same manner as in the first embodiment to form a source 10 and a drain 12. Form. Here, it is also possible to form the silicon oxide layer 107 by a thermal oxidation method. In this case, the boundary between the planned drain region of the TFT and the planned channel region, and the tip of the lower electrode 18 on the planned drain region side. Is required to be at least 10 μm or more in order to prevent lateral diffusion accompanying heating. After this step, the liquid crystal panel is completed by forming the interlayer insulating film 24, the transparent electrode 20, and the data lines 4a as in the first embodiment.

[Procedure amendment 27]

[Document name to be amended] Statement

[Correction target item name] 0040

[Correction method] Change

[Correction contents]

The reference example is characterized in that an integral intrinsic polycrystalline silicon layer 106 is formed in advance and then formed on both the lower electrode and the active layer of the TFT, and the number of steps does not change. However, there is no step at the connection between the lower electrode 18 and the drain 12 as in the first embodiment.

[Procedure amendment 28]

[Document name to be amended] Statement

[Correction target item name] 0041

[Correction method] Change

[Correction contents]

Finally, an embodiment of the manufacturing method according to the present invention will be described with reference to FIG. In this embodiment, first,
As shown in FIG. 11 (a), an intrinsic polycrystalline silicon layer 107 and a conductive polycrystalline silicon layer 108 which are separated from each other in advance are formed on the surface of a glass substrate l. In this formation method, an intrinsic polycrystalline silicon layer is formed by separating the two layers by a CVD method, and phosphorus may be introduced into only one of them.
The undoped layer and the doped layer may be separately formed by the VD method. Next, as shown in FIG. 11B, a gate oxide film 22 and a dielectric insulating film 26 are formed on these surfaces by a thermal oxidation method, and a conductive polycrystalline silicon layer below the dielectric insulating film 26 is formed. The lower electrode 42 is used. Further, as shown in FIG. 11C, a gate electrode 8 and an upper electrode 105 are formed thereon, and phosphorus is implanted using the gate electrode 8 as a mask to form a source 10 and a drain 12 of the TFT.
Thereafter, after depositing the interlayer insulating film 24, FIG.
As shown in FIG. 2, the interlayer insulating film 24 is removed by etching so as to form the exposed portion 12a of the drain 12 and the exposed portion 42a of the lower electrode 42, and the transparent electrode 2 including the opening portion.
0 to form a conductive contact with both exposed portions 12a and 42a.

[Procedure amendment 29]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction contents]

In the embodiments and reference examples of the liquid crystal panel or the method of manufacturing the same, the gate electrode, the gate line, and the data line may have a polycide structure, or a salicide technique may be employed in these forming steps. . Further, the gate electrode and the gate line can be formed in different steps. In particular, the gate electrode can be formed of polycrystalline silicon or polycide, and the gate line can be formed of refractory metal silicide.

[Procedure amendment 30]

[Document name to be amended] Statement

[Correction target item name] 0044

[Correction method] Change

[Correction contents]

[0044]

As described above, according to the present invention, as a liquid crystal display panel having a transistor, a gate insulating film and a dielectric insulating film are simultaneously formed after a lower electrode is formed, and further, a gate electrode and an upper electrode are simultaneously formed. In this case, a charge storage capacitor can be formed in a liquid crystal display panel including a transistor with a small number of steps.

[Procedure amendment 31]

[Document name to be amended] Statement

[Correction target item name] 0045

[Correction method] Deleted

[Procedure amendment 32]

[Document name to be amended] Statement

[Correction target item name] 0046

[Correction method] Deleted

[Procedure amendment 33]

[Document name to be amended] Statement

[Correction target item name] 0047

[Correction method] Deleted

[Procedure amendment 34]

[Document name to be amended] Statement

[Correction target item name] 0048

[Correction method] Deleted

[Procedure amendment 35]

[Document name to be amended] Statement

[Correction target item name] 0049

[Correction method] Deleted

[Procedure amendment 36]

[Document name to be amended] Statement

[Correction target item name] 0050

[Correction method] Deleted

[Procedure amendment 37]

[Document name to be amended] Statement

[Correction target item name] Brief description of drawings

[Correction method] Change

[Correction contents]

[Brief description of the drawings]

FIG. 1 is a plan view showing the structure of a liquid crystal display panel according to a first reference example of the present invention.

FIG. 2 is a cross-sectional view showing a state cut along the line II-II in FIG.

FIG. 3 is a cross-sectional view showing a state cut along the line III-III in FIG. 1;

FIG. 4 is a plan view showing a structure of a second reference example of the liquid crystal display panel according to the present invention.

FIG. 5 is a cross-sectional view showing a state cut along line VV in FIG. 4;

FIG. 6 is a schematic sectional view showing different reference examples of the liquid crystal display panel according to the present invention.

FIG. 7 is a schematic sectional view showing different reference examples of the liquid crystal display panel according to the present invention.

FIG. 8 is a schematic sectional view showing an embodiment of the liquid crystal display panel according to the present invention.

FIGS. 9A to 9G are cross-sectional views showing a process in the first reference example of the method for manufacturing a liquid crystal display panel according to the present invention.

FIGS. 10A to 10D are process cross-sectional views showing a second reference example of the method for manufacturing a liquid crystal display panel according to the present invention.

FIGS. 11A to 11D are process cross-sectional views illustrating an example of a method for manufacturing a liquid crystal display panel according to the present invention.

[Description of Signs] l: Glass substrate 2aa ... Pixel area 4a, 4b ... Data line 6a, 6b ... Gate line 8 ... Gate electrode 10 ... Source 12 ... Drain 14 ... channel regions 16, 36 ... connecting layers 18, 42 ... lower electrode 20 ... transparent electrode 22 ... gate oxide film 24 ... interlayer insulating film 26 ... dielectric insulating film 38 ..Metal electrodes 40, 109: conductive polycrystalline silicon layer 103, 106, 107: intrinsic polycrystalline silicon layer 104: silicon oxide layer 105: upper electrode

Claims (12)

[Claims] A thin film transistor having a source conductively connected to a data line and a gate conductively connected to a gate line;
A pixel electrode conductively connected to the drain of the thin-film transistor, a lower electrode to which the drain potential is applied, an upper electrode to which another potential is applied, and a charge storage capacitor including a dielectric insulating film formed between these electrodes And wherein a potential of an adjacent gate line adjacent to the gate line is applied to the upper electrode. 2. The liquid crystal display panel according to claim 1, wherein said upper electrode is an adjacent gate line itself, and said lower electrode is formed directly below said upper electrode via said dielectric insulating film. A liquid crystal display panel comprising a connection portion to which the drain potential is applied to itself. 3. The liquid crystal display panel according to claim 2, wherein said connection portion is connected to said drain, and at least a part thereof is formed below said data line or a data line adjacent thereto. A liquid crystal display panel. 4. The liquid crystal display panel according to claim 2, wherein said connection portion is connected to said pixel electrode. 5. The liquid crystal display panel according to claim 1, wherein said lower electrode is formed of a conductive polycrystalline silicon layer. panel. 6. The liquid crystal display panel according to claim 1, wherein said lower electrode is formed of a metal layer. 7. A thin film transistor having a source conductively connected to a data line and a gate conductively connected to a gate line;
A pixel electrode conductively connected to the drain of the thin-film transistor, a lower electrode to which the drain potential is applied, an upper electrode to which another potential is applied, and a charge storage capacitor including a dielectric insulating film formed therebetween Forming the active layer and the lower electrode of the thin film transistor, and then simultaneously forming the gate insulating film and the dielectric insulating film of the thin film transistor in the method for manufacturing a liquid crystal display panel having a pixel region comprising A liquid crystal panel comprising: simultaneously forming the gate and the upper electrode; and thereafter, forming the source and the drain by conducting the active layer using the gate as a mask. Manufacturing method. 8. The method of manufacturing a liquid crystal display panel according to claim 7, wherein the step of forming an active layer of the thin film transistor and the lower electrode comprises: forming the active layer from intrinsic polycrystalline silicon; With conductive polycrystalline silicon,
A method for manufacturing a liquid crystal panel, which is a step of forming each. 9. The method of manufacturing a liquid crystal display panel according to claim 7, wherein the step of forming an active layer of the thin film transistor and the lower electrode comprises: forming the active layer of intrinsic polycrystalline silicon; A method for manufacturing a liquid crystal panel, which is a step of forming each of the metal layers. 10. The method for manufacturing a liquid crystal display panel according to claim 8, wherein the step of forming the active layer and the lower electrode of the thin film transistor comprises: forming an intrinsic polycrystalline silicon layer; Converting the part of the intrinsic polycrystalline silicon layer into conductive, forming the lower electrode, and using the remainder as the active layer. 11. The method according to claim 7, wherein
In the method of manufacturing a liquid crystal display panel according to the above item, in the step of forming an active layer of the thin film transistor and the lower electrode, the active layer and the lower electrode are formed apart from each other, and the active layer is formed using the gate as a mask. Forming a source and a drain, and forming a pixel electrode on the exposed part of the drain and the exposed part of the lower electrode in a conductive contact state after the step of forming the source and the drain. 12. The method for manufacturing a liquid crystal panel according to claim 7, wherein the step of simultaneously forming the gate insulating film and the dielectric insulating film of the thin film transistor is performed by thermal oxidation. A method for producing a liquid crystal panel, which is performed by a method.