JPH10154937A - Digital-analog converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain unnecessary current consumption in unneeded output and to reduce power consumption by setting the potential of each of the bit terminals of a ladder resistance network and the potential of a reference voltage to be applied to be equal in a digital-analog(DA) converter using the R-2R ladder resistance network. SOLUTION: When in normal operation, input digital data D0 to D7 are supplied to the input terminals of inverter gates INV0 to INV7 of which the output is connected to the bit terminal of the ladder resistance network, and when in resetting or non-selecting, the reference voltage Vref of U level or Vref of L level is inputted to the all by the switching of switches 12-0 to 12-7. At this time, the levels of the bit terminal and the reference voltage are controlled by inputting digital codes so as to be equal via a control circuit 13. Thus, unnecessary current flows into the ladder resistance network is restrained at the time of nonoperation, and current consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog converter using an R-2R ladder resistor network for inputting a digital signal and converting it to an analog signal, and more particularly to a digital-to-analog converter having a plurality of R-2R ladder resistor networks on one chip. In digital-to-analog converters that require multiple outputs,
The present invention relates to a digital-to-analog converter that suppresses unnecessary circuit current and reduces power consumption as a whole.

[0002]

2. Description of the Related Art First, an R-2R ladder type (R-2R ladder type resistor network) conventional digital-to-analog converter using two types of resistors, R and 2R, will be described.

FIG. 3 is a diagram showing a combination of R-2 and R-2, which outputs a voltage having a binary ratio in accordance with a digital input signal.
1 shows an example of a conventional digital-analog converter using an R ladder. The configuration shown in FIG. 3 is an 8-bit ladder resistor type digital-to-analog converter.
0 to D7 represent the LSB (least significant bit) to the MSB (most significant bit) of the digital input signal, and all the switch units 1 are connected to the first reference potential VrefU.
Is output as the output DACOUT.

Referring to FIG. 3, VrefU, VrefL
Are first and second reference voltages serving as references for analog output, and apply a voltage to the R-2R ladder via the switch unit 1.

Normally, an inverter INV that operates using a reference voltage source as a power supply is used as the switch section 1, as shown in FIG.

When multiple outputs are formed on one chip, as shown in FIG. 5, the first reference voltage Vref is used.
When U is a reference ladder, when the VrefL level is applied to the bit end of the ladder in the initial state when the power is turned on, and as shown in FIG. 6, the second reference voltage VrefL
Is the reference ladder, when the VrefU level is applied to the bit end of the ladder, the current of VrefU is consumed.

[0007] Such a current consumes useless current depending on the input digital code, for example, in the case of a configuration of 36 channels per chip, even when only about 26 channels are actually used. Will be done. This can be said not only at the time of power-on but also at the time of standby.

For the purpose of improving the above-mentioned wasteful current consumption in the conventional R-2R type digital / analog converter, for example, Japanese Unexamined Patent Publication No. Hei 4-170112 discloses that the unused R / R type digital / analog converter is used regardless of the level of the digital signal. R-2R digital-to-analog converter (D / A)
As a configuration of the converter, there has been proposed a configuration in which a switch circuit is provided, the digital signal is not used irrespective of the level of the digital signal, and power is reduced because no digital signal is supplied when the digital signal is not used. FIG. 7 and FIG. 8 are diagrams showing an example of the configuration proposed in the above publication.

Referring to FIG. 7 and FIG. 8, before a switch at each bit end input to the R-2R ladder, an NA is provided.
By adding an ND gate (see FIG. 7) or a NOR gate (see FIG. 8), all bits can be controlled by a PD signal and can be controlled so that no current flows through the R-2R ladder resistor network.

In FIG. 7, the reference voltage of the ladder is the second voltage.
The reference signal VrefU (= VSS) is used. In use, the control signal PD is set to a low level, the control signal PD is inverted by an inverter, and a high level is input to one end of each NAND gate. The output of each NAND gate changes according to the level of each bit D0 to D7 of the signal, is converted into an analog signal by the converter body, and the analog signal voltage is output to the output terminal DACOUT.

On the other hand, when the digital-to-analog converter is not used, the control signal PD is at a high level, the signal inverted by the inverter is at a low level,
A low level is input to one input terminal of each NAND gate, and the output of each NAND gate is output to each of bit terminals D0 to D7.
Of the ladder, which is the output node of the inverter INV, is at the Low level, that is, VSS.
(Lower side power supply voltage), so that no current flows through the ladder resistor.

In FIG. 8, since the reference voltage of the ladder has changed to the first reference voltage VrefU (= VCC),
When not used, the bit end of the ladder is connected to the higher power supply potential VC.
The current in the ladder resistor is set to zero by setting the control signal PD to the high level by the NOR gate in order to make the level the same as C.

[0013]

In the prior art described with reference to FIGS. 7 and 8, a large number of gates corresponding to the number of bits need to be added to each R-2R ladder circuit. In the case of the channel configuration, there is a problem that the number of additional gates is greatly increased.

In addition, the insertion of a NAND gate or a NOR gate in the above-described prior art takes into consideration the on-resistance of the transistor at the bit end, weights the switches of the upper bits, and considers the accuracy of the ladder.
Inadequate chip layout.

Accordingly, the present invention has been made in view of the above problems, and has as its object to provide a digital / analog converter having multiple outputs and a ladder resistor network which consumes a large amount of current of a reference power supply. It is an object of the present invention to provide a digital-analog converter which suppresses useless current consumption at a substantially unnecessary output even when applied to a digital-analog converter and achieves low power consumption of a reference power supply even during standby.

[0016]

In order to achieve the above object, the present invention relates to a digital-analog converter using an R-2R ladder resistor network, which comprises: A ladder resistor network is provided with means for switching so as to make the level of the power supply voltage serving as a reference to be connected equal.

Further, according to the present invention, in a digital-to-analog converter using an R-2R ladder resistor network, a bit signal is supplied to an input terminal of an inverter gate having an output terminal connected to each bit terminal of the ladder resistor network. The reference terminal of the ladder resistor network is connected to the output terminal of the changeover switch for switching between the reference voltage of the ladder resistor network and the reference terminal of the ladder resistor network at the time of reset or standby. Is set to

Further, the present invention relates to a digital-analog converter using an R-2R ladder resistor network, wherein an input terminal of an inverter gate having an output terminal connected to each bit terminal of the ladder resistor network and a bit signal input terminal. The output of the latch circuit is switched to a high potential or a low potential at the time of reset or standby, so that the reference voltage of the ladder resistor network is equal to the potential of each bit end of the ladder resistor network. Setting.

[0019]

Embodiments of the present invention will be described below. In a preferred embodiment of the present invention, the voltage level of the reference voltage connected to the ladder resistor network and the bit end of the ladder resistor network are determined when the R-2R ladder is reset or when any output is selected or deselected. Switch for switching voltage level (12, 12-0 to 1 in FIG. 1)
2-7), and a control circuit (see FIG. 13) for switching and controlling the resistance network according to the state. The control circuit determines the voltage level at the bit end of the ladder resistance network and the reference voltage level directly connected to the ladder resistance network. By making them equal, the current consumption in the ladder resistor network is made to be zero.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain the above-mentioned embodiment in more detail, an embodiment of the present invention will be described below.

FIG. 1 is a diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, one embodiment of the present invention is an R-
In a digital-to-analog converter using 2R,
At the time of reset or standby, and at the time of non-selection state,
Switch circuits 12-0 to 12- that switch the input terminals of the inverter between digital input signals D0 to D7, a high-potential-side reference voltage VrefU, and a low-potential-side reference voltage VrefL in order to suppress current consumption in the ladder resistor. 7 and a switch circuit 12 enabling switching of the reference voltage level
And a control circuit 13 for switching and controlling these switch circuits.

During normal operation, the input digital data D0 to D7 are connected to the input terminals of the inverter gates INV0 to INV7 whose outputs are connected to the bit terminals of the ladder resistor network.
The first reference voltage VrefU level or the second reference voltage VrefL level is input to all the switches 12-0 to 12-7 at the time of reset, standby, or non-selection.

At this time, the bit end 11 of the digital input
When the level of the reference voltage connected to the ladder resistor network is different from that of the ladder resistor network, current is consumed. Therefore, at the time of reset and standby, all the bit ends of the input and the ladder resistor network are connected. The control circuit 13 determines the level of the reference voltage by the input digital code.
, Unnecessary current consumed by the ladder is suppressed. For example, when the reference voltage of the ladder resistor network is VrefU, when the digital input signals D0 and D7 are "1" during standby, and when the others are "0", the switches 12-0 and 12
By switching −7 to the lower voltage VrefL side, the outputs of the inverters INV0 to INV7 are all High.
At this time, the output voltage of the inverters INV0 to INV7 becomes equal to the reference voltage VrefU of the ladder resistor network.

FIG. 2 is a diagram showing the configuration of another embodiment of the present invention. 2, a latch circuit 24 latches a digital code serially or parallelly input from an interface (not shown), and FIG. 2 shows a case of an 8-bit configuration.

The latch circuit 24 is reset by a signal from the interface. At the time of reset, all the 8-bit data is converted to the first reference voltage VrefU.
Alternatively, it is fixed at the level of the second reference voltage VrefL.

The switch circuit 22 and the control circuit 23 for controlling the switch circuit 22 control the supply level of the reference voltage to the ladder with respect to the reset state of all outputs and the reset state of the input level of the unnecessary R-2R resistor network. Is made equal to the bit end of the input to reduce the current consumption to zero.

Multi-output digital-to-analog converter I
C normally receives an external digital input signal through a serial or parallel input. At this time, an analog output is obtained from at least two data of the output selection data and the output level data in terms of which output level of the plurality of outputs is changed.

Normally, after the output selection data is received by a latch or the like, a latch for storing output level data is selected by a decoder or the like, and the output level data is usually written into the latch circuit.

In the above operation, it is easy for the control circuit 23 shown in FIG. 2 to send a control signal to a ladder resistance network of an output which is not selected.

As described below, in the embodiment of the present invention,
This is realized by making the level of the reference power supply of the ladder circuit equal to the level of the bit end of the ladder circuit in order to reduce the current consumed by the ladder circuit at the reset and the unselected output to zero.

[0031]

As described above, according to the present invention,
In a multi-output digital-to-analog converter based on the R-2R ladder, it is possible to easily reduce the current consumption of the ladder resistor in the reset state and unused outputs.

Further, according to the present invention, compared with the prior art,
Since the number of gates can be reduced to a minimum, the circuit size can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of another embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional R-2R digital-to-analog converter.

FIG. 4 is a diagram showing another configuration of a conventional R-2R digital-to-analog converter.

FIG. 5 illustrates a case where a conventional ladder reference voltage is VrefU.
FIG. 2 is a diagram illustrating a configuration of a −2R type digital / analog converter.

FIG. 6 shows a case where a conventional ladder reference voltage is VrefL;
FIG. 2 is a diagram illustrating a configuration of a −2R type digital / analog converter.

FIG. 7 is a diagram showing an example of a circuit configuration proposed in Japanese Patent Application Laid-Open No. 4-170112.

FIG. 8 is a diagram showing another example of a circuit configuration proposed in Japanese Patent Application Laid-Open No. 4-170112.

[Explanation of symbols]

 11 Bit end switch 12 Reference power switch 13, 23 Reference power control circuit 24 Digital data latch circuit

Claims (4)

[Claims] 1. A digital-to-analog converter using an R-2R ladder resistor network, comprising: a level input to each bit end of the ladder resistor network;
A digital-to-analog converter, comprising: means for switching so as to equalize a power supply voltage level serving as a reference to which the ladder resistor network is connected. 2. A digital-to-analog converter using an R-2R ladder resistor network, wherein a bit signal and a higher-level reference voltage or an input signal are connected to an input terminal of an inverter gate having an output terminal connected to each bit terminal of the ladder resistor network. The output terminal of the changeover switch for switching between the lower reference voltage and the switch is connected. At the time of reset or standby, the reference voltage of the ladder resistor network is set to be equal to the potential of each bit terminal of the ladder resistor network. A digital-to-analog converter characterized by the above-mentioned. 3. A digital / analog converter using an R-2R ladder resistor network, wherein a latch circuit is provided between an input terminal of an inverter gate having an output terminal connected to each bit terminal of the ladder resistor network and a bit signal input terminal. Inserting, at the time of reset or standby, switching the output of the latch circuit to a high potential or a low potential, and setting the reference voltage of the ladder resistor network to be equal to the potential of each bit end of the ladder resistor network. A digital-to-analog converter characterized by the following. 4. A digital-to-analog converter using a plurality of R-2R ladder resistor networks, unless a digital input requesting an analog output is provided, input to each bit end of the ladder resistor network. A digital-to-analog converter comprising: a switch unit for making a level equal to a level of a reference power supply voltage to which the ladder resistor network is connected; and a control circuit for controlling the switch unit.