JPH10154794A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to alter the characteristics of a circuit element and to make it possible to evaluate the characteristics of an intrinsic circuit operation without performing a fuse blow treatment by a method wherein the semiconductor integrated circuit device is provided with a single characteristic evaluation adjusting pad, which is used for an evaluation of the characteristics of the circuit element and an adjustment of the characteristics of the intrinsic circuit operation. SOLUTION: The main part of a semiconductor integrated circuit device is constituted of a characteristic evaluation adjusting pad (special pad) 1, inner-element pads 2 and 3, N-MOS and P-MOS transistors 4 and 5 which are elements for characteristics evaluation use, a control circuit 6 and a potential fixing circuit 7. In the state of the normal use of the circuit element, a potential in the pad 1 is fixed on a supply voltage by the circuit 7. When the potential in the pad 1 is fixed on a ground potential, an adjustment of an increase in the pulse width of a reference clock signal at the time when an access operation and a write operation are executed is made possible without cutting a fuse circuit. Moreover, when the potential in the pad 1 is fixed to the ground potential and potentials in the inner-element pads 2 and 3 are fixed to the power potential, the evaluation of the characteristics of the transistor 4 or the like can be made.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device capable of easily evaluating the characteristics of circuit elements formed on a chip and adjusting the characteristics of circuit operation in a wafer state.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit device, it is necessary to perform a fuse blow or an F
IB (Forced Ion Beam) processing was required. In the case where a pad for controlling a circuit element or for evaluating the characteristics of the element is provided, it is necessary to provide a plurality of such pads. FIG.
FIG. 1 is a block diagram showing a main part of a conventional semiconductor integrated circuit device. This semiconductor integrated circuit device includes a special pad 52 for evaluating characteristics of a characteristic evaluation element 51 which is an NMOS transistor, a special pad 54 for supplying information to a control circuit 53, and a characteristic evaluation element 55 which is a PMOS transistor. Special pad 5 for evaluating the characteristics of
A plurality of special pads such as 6 are provided. The element pad 50 is connected to the characteristic evaluation element 51 by the special pad 52.
Used in evaluating the characteristics of the device, pad 5 in the element
Reference numeral 7 denotes a pad used when the characteristic of the characteristic evaluation element 55 is evaluated by the special pad 56. Further, the control circuit 53 outputs an equalize signal, a write signal, and the like according to the information supplied from the special pad 54. In such a conventional semiconductor integrated circuit device,
Some of the special pads may be present only partially or not at all.

[0003]

Since the conventional semiconductor integrated circuit device is configured as described above, the semiconductor integrated circuit device is provided with a plurality of special pads for controlling the circuit device and evaluating the characteristics of the device. In the device, there is a problem that the area of the semiconductor integrated circuit device itself increases. Further, in the fuse blow processing for changing the characteristics of the element or performing the characteristic evaluation, it is difficult to perform a reproduction process for returning the original state once the fuse is cut. There was a problem that the evaluation could not be redone.

Accordingly, an object of the present invention is to change the characteristics of an element by fuse blowing or FIB processing only by adding one pad for changing or evaluating the characteristics of the element.
It is an object of the present invention to provide a semiconductor integrated circuit device that can easily realize the above-described characteristic change and characteristic evaluation equivalent to the characteristic evaluation and can minimize an increase in the area of the semiconductor integrated circuit device itself due to the addition of the pad. It is a further object of the present invention to provide a semiconductor integrated circuit device which enables the characteristic change and the characteristic evaluation to be performed again.

[0005]

In order to achieve the above object, the present invention has a single characteristic evaluation adjustment pad used for evaluating the characteristics of circuit elements and adjusting the characteristics of the original circuit operation. Features.

In the semiconductor integrated circuit device according to the present invention, since only a single characteristic evaluation adjustment pad for evaluating the characteristics of the circuit device and adjusting the characteristics of the original circuit operation is added, a plurality of characteristic evaluation adjustments are performed. The area of the semiconductor integrated circuit element itself does not increase as compared with the configuration in which the pad is added. In particular, the characteristic evaluation element is controlled by a signal supplied from a normal pad, the characteristic of the characteristic evaluation element is evaluated through the characteristic evaluation adjustment pad, and further evaluated by a fuse blow or FIB processing in a characteristic adjustment circuit. The characteristic change and characteristic adjustment of the original circuit operation,
Since the equivalent characteristic adjustment circuit is realized via the characteristic evaluation adjustment pad regardless of the processing, the fuse blow or FIB
The processing may be finally performed after the confirmation of the characteristic change and the characteristic adjustment, and the characteristic change and the characteristic adjustment can be performed again.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a semiconductor integrated circuit device according to the present invention will be described. FIG. 1 is a block diagram showing a main part of a semiconductor integrated circuit device according to the present invention. This semiconductor integrated circuit device includes a characteristic evaluation adjustment pad (hereinafter, referred to as a special pad) 1 that is not wire-bonded and is not used in normal use, a device pad (normal pad) 2 used for signal input / output in normal use, and a device internal pad. The potential of the pad (normal pad) 3, the NMOS transistor 4 and the PMOS transistor 5, which are the elements for evaluating characteristics, the control circuit (characteristic adjusting circuit) 6, and the potential of the special pad 1 can be fixed to any potential including the Vcc potential and the ground potential. A potential fixing circuit (bias circuit) 7 is provided. The NMOS transistor 4 and the PMOS transistor 5, which are the characteristic evaluation elements, are elements in which arbitrary transistors are arbitrarily wired in any combination. Further, the control circuit 6 is a circuit capable of adjusting the characteristic of the original circuit operation by using information supplied through the special pad 1. For example, a circuit or a circuit element configured on a chip The equivalent characteristic adjusting circuit 6a is provided so as to function also according to the information supplied from the special pad 1. The equivalent characteristic adjusting circuit 6a controls the operation timing of the circuit or the circuit element via the control circuit 6 based on the information given to the special pad 1, and evaluates the characteristic of the circuit or the circuit element at a desired timing. Enable.

FIG. 2 is a circuit diagram showing a specific circuit configuration of the semiconductor integrated circuit device shown in FIG. 2, the same or corresponding parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. As shown in FIG. 2, the drains of the NMOS transistor 4 and the PMOS transistor 5, which are the elements for evaluating characteristics, are connected to the Vcc power supply, and the sources are connected to the special pad 1. The gate of the NMOS transistor 4 is connected to the pad 2 in the element and the pad 2 in the element.
Is connected to a normal circuit 21 for inputting and outputting signals. Further, the gate of the PMOS transistor 5 is connected to the in-element pad 3 and the normal circuit 22 for inputting and outputting signals via the in-element pad 3.

The equivalent characteristic adjusting circuit 6a includes an inverter circuit 26 for inverting the binary signal level of the special pad 1, and an output terminal N for supplying the output of the inverter circuit 26 to one input terminal.
An OR circuit 27 is provided. The control circuit 6 includes a fuse circuit 31 having one end connected to the Vcc power supply, a drain connected to the other terminal of the fuse circuit 31, and a source connected to the ground. An NMOS transistor 33; an inverter circuit 34 for inverting the binary signal level of the other terminal of the fuse circuit 31 and supplying the inverted signal level to the gate of the NMOS transistor 33 and supplying the inverted signal level to the other input terminal of the NOR circuit 27; 27, an inverter circuit 36 for delaying and inverting the pulse A, and an AND operation of the output of the inverter circuit 36 and the output of the inverter circuit 35, and inverting the operation result and outputting the result. NAN to do
NA for performing a logical AND operation of the output of the D circuit 37 and the NAND circuit 37 and the pulse A, inverting the operation result, and outputting the inverted result
The ND circuit 38 is provided.

The potential fixing circuits 7 are connected in parallel with each other, have a drain connected to the Vcc power supply, and have a source connected to the special pad 1.
a, 7b and the source-side binary signal levels of the PMOS transistors 7a, 7b,
and an inverter circuit 7c for supplying a gate to the gate of the PMOS transistor 7b.
And an inverter circuit 7d for supplying the gate to the gate.
In this case, the PMOS transistors 7a and 7b have small current capabilities and are equivalently used as load resistors. Even when the special pad 1 is kept in a floating state when assembling from the wafer state to the molded state, the potential fixing circuit 7 always fixes the node of the special pad 1 to the Vcc potential. NMOS transistor 4 and PM
The configuration is such that the OS transistor 5 and the control circuit 6 are not affected at all.

Next, the operation will be described. First, the characteristic evaluation of the current Ids and the threshold voltage Vth of the NMOS transistor 4 and the PMOS transistor 5 by the special pad 1 will be described. In the characteristic evaluation of the NMOS transistor 4 using the special pad 1, for example, the special pad 1
And to the ground via a Vth measuring device. In the evaluation of the characteristics of Ids, the NMO
The Vcc voltage is applied to the gate of the S transistor 4, and the current Ids flowing from the drain to the source at this time can be measured by the measuring device. Also, Vth
In the characteristic evaluation, the Vcc voltage can be applied from the in-element pad 2 to the gate of the NMOS transistor 4, and Vth at this time can be measured by the measuring device. In the characteristic evaluation of the PMOS transistor 5 by the special pad 1, for example, the special pad 1 is connected to the ground via a measuring device for Ids or Vth. In the evaluation of the characteristics of Ids, the pad 2 in the element was set to the ground potential and the PM
Apply a ground voltage to the gate of the OS transistor 5,
At this time, the current Ids flowing from the drain to the source can be measured by the measuring device. Vt
In the characteristic evaluation of h, it is possible to apply the ground voltage to the gate of the PMOS transistor 5 by setting the in-element pad 2 to the ground potential, and measure the Vth at this time by the measuring device.

Next, the pulse width of the reference clock signal when an access operation, a write operation, or the like is performed, for example, is adjusted using the special pad 1 to adjust the characteristics of the original circuit operation such as the access time and the write parameters. Will be described with reference to FIG. The characteristic adjustment of the original circuit operation is performed by cutting the fuse circuit 31, and it is difficult to change the characteristic or perform the characteristic evaluation again when performing the characteristic change or the characteristic evaluation. The operation can be performed by the voltage level applied to the special pad 1 without disconnecting the circuit 31, and when the characteristics are changed or the characteristics are evaluated, the characteristics can be changed or the characteristics can be evaluated again. In this characteristic adjustment, when the special pad 1 is connected to the ground, the equivalent characteristic adjustment circuit 6a
Of the inverter circuit 26 attains a high level. As a result, the output of the NOR circuit 27 becomes low level and the output of the inverter circuit 35 becomes high level, and this high level signal is supplied to one input terminal of the NAND circuit 37. At this time, the other input terminal of the NAND circuit 37 is
A high-level signal obtained by inverting the pulse A to which the delay time has been given in each inverter circuit element constituting the inverter circuit 36 is supplied. As a result, a low-level signal obtained by inverting the high-level signal is output from the NAND circuit 37 and supplied to one input terminal of the NAND circuit 38. Since the pulse A is supplied to the other input terminal of the NAND circuit 38 at this time, the pulse width of the pulse A to which the delay time is not given is extended by the delay time, and the pulse A is changed to the high-level pulse B. 38.

In other words, the pulse width of the reference clock signal at the time of executing the access operation, the write operation, etc., which is conventionally realized by cutting the fuse circuit 31 to make the output of the inverter circuit 34 high, is increased. This adjustment is realized by applying a ground potential to the special pad 1 without cutting the fuse circuit 31. Therefore, the operation of changing the pulse width of the reference clock signal to change the characteristics of the semiconductor integrated circuit element when the access operation, the write operation, or the like is performed, and the evaluation of the characteristics of Ids and Vth to the special pad 1 are performed on the special pad 1. It can be easily performed simply by applying a potential. Further, an increase in the element area can be suppressed to a minimum as compared with a conventional semiconductor integrated circuit element in which the above-mentioned characteristics are changed or characteristics are evaluated using a plurality of special pads.

FIG. 4 shows a special pad 1, an element pad 2,
FIG. 6 is an explanatory diagram showing the potential state of No. 3 and the contents of a property change and a property evaluation realized thereby. According to this, in the normal use state where the special pad 1 is set to the floating state,
The potential of the special pad 1 is fixed to Vcc by the potential fixing circuit 7. When the special pad 1 is fixed to the ground potential, the pulse A whose pulse width is increased as described above is output from the control circuit 6 as the pulse B. When the special pad 1 is fixed to the ground potential and the pads 2 and 3 in the device are fixed to the Vcc potential, the Ids and Vth of the NMOS transistor 4 serving as a device for evaluating characteristics can be measured, and the characteristics can be evaluated. Becomes Further, when the special pad 1 is fixed to the ground potential and the pads 2 and 3 in the device are fixed to the ground potential, the Ids and Vth of the PMOS transistor 5, which is a device for evaluating characteristics, can be measured, and the characteristics can be evaluated. Becomes

In the above embodiment, the description is made on the assumption that the characteristic change and the characteristic evaluation of the semiconductor integrated circuit element are performed by fixing the special pad 1 to the ground potential.
The content of the characteristic evaluation is the measurement of Ids and Vth of the NMOS transistor 4 and the PMOS transistor 5, and the content of the characteristic change is a semiconductor used when the access operation and the write operation are performed by changing the pulse width of the reference clock signal. Although the description has been made on the assumption that the characteristics of the integrated circuit element are changed, the contents of the characteristics change and the characteristics evaluation are not limited thereto, and may be the characteristics changes and the characteristics evaluation as required. Further, the fixed potential of the special pad 1 is not limited to the ground potential, and the fixed potential of the in-element pads 2 and 3 may be an arbitrary potential as needed. In the normal use state, it has been described that the special pad 1 is fixed to the Vcc potential by the potential fixing circuit 7;
Depending on the connection configuration of the OS transistor 4 and the PMOS transistor 5 and the circuit configuration of the control circuit 6, the special pad 1 may be fixed to the ground potential by the potential fixing circuit 7.

[0016]

As described above, the semiconductor integrated circuit device according to the present invention has a single characteristic evaluation adjustment pad used for evaluating the characteristics of the circuit device and adjusting the characteristics of the original circuit operation. Therefore, there is an effect that the increase in the area of the semiconductor integrated circuit element itself can be suppressed to a minimum. Also, the semiconductor integrated circuit device of the present invention is connected to a bias circuit for biasing the characteristic evaluation adjustment pad, and to the characteristic evaluation adjustment pad and a normal pad used for the original circuit operation,
A characteristic evaluation element whose characteristic is evaluated via the characteristic evaluation adjustment pad, a characteristic adjustment circuit for adjusting the characteristic of the original circuit operation, and a characteristic adjustment performed by the characteristic adjustment circuit via the characteristic evaluation adjustment pad. Since the configuration is provided with an equivalent characteristic adjustment circuit realized by performing, the characteristic evaluation of the element for characteristic evaluation and the characteristic adjustment of the original circuit operation can be performed by sharing the characteristic evaluation adjustment pad, There is an effect that the increase in the area of the semiconductor integrated circuit element itself can be suppressed to a minimum by eliminating the need for additional characteristic evaluation adjustment pads. In the semiconductor integrated circuit device according to the present invention, the characteristic evaluation adjustment pad is connected to a high-potential-side power supply based on a pulse signal generated at power-on, and the characteristic evaluation adjustment pad is connected to the high-potential-side power supply voltage. Is configured to include a bias circuit that maintains a biased state, so that the characteristic evaluation adjustment pad is biased to the power supply voltage on the high potential side at the same time as power is turned on. By connecting to a potential level different from the power supply voltage on the high potential side, there is an effect that the characteristic evaluation of the characteristic evaluation element and the characteristic adjustment of the original circuit operation can be performed via the characteristic evaluation adjustment pad.

Further, the semiconductor integrated circuit device of the present invention is connected between the power supply on the high potential side and the characteristic evaluation adjustment pad, and supplied from the characteristic evaluation adjustment pad connected to the reference potential side and the normal pad. A transistor whose characteristics are controlled by a signal to be performed and characteristics of which are evaluated with respect to a current capacity and a threshold voltage is provided as a characteristic evaluation element, so that a signal supplied from the normal pad is fixed to the high potential side. Alternatively, it is possible to evaluate characteristics of the transistor having a different configuration depending on whether the transistor is fixed to the reference potential side. Further, a semiconductor integrated circuit element of the present invention has a cuttable fuse connected between circuits, and a characteristic adjustment circuit for adjusting characteristics of an original circuit operation by cutting the fuse. And an equivalent characteristic adjustment circuit that realizes the characteristic adjustment to be performed through a characteristic evaluation adjustment pad.Thus, the characteristic adjustment of the original circuit operation can be performed without cutting the fuse by the equivalent characteristic adjustment circuit. There is an effect that the characteristic adjustment can be performed again. In addition, the semiconductor integrated circuit device of the present invention is configured to include a characteristic adjustment circuit that adjusts the characteristics of the original circuit operation such as the access time and the write parameter, so that the access time and the write parameter can be set without cutting the fuse. The characteristic adjustment of the original circuit operation can be performed, and the effect of the characteristic adjustment can be redone. Also, the semiconductor integrated circuit device of the present invention adjusts the pulse width of the reference clock signal when an access operation, a write operation, or the like is performed, thereby achieving the characteristics of the original circuit operation such as the access time and the write parameter. Since the characteristic adjustment circuit for performing the adjustment is provided, the pulse width of the reference clock signal can be adjusted without cutting the fuse, and the characteristic adjustment of the original circuit operation such as the access time and the write parameter can be performed. ,
There is an effect that the characteristic adjustment can be performed again. Further, in the semiconductor integrated circuit device of the present invention, the characteristic adjustment equivalent to the characteristic adjustment of the original circuit operation performed by cutting the fuse of the characteristic adjustment circuit is performed by connecting the characteristic evaluation adjustment pad to a power supply on the low potential side. Since the equivalent characteristic adjustment circuit realized by the characteristic adjustment circuit is provided, the characteristic adjustment of the original circuit operation can be performed by the characteristic evaluation adjustment pad connected to the power supply on the low potential side without cutting the fuse. Thus, there is an effect that the characteristic adjustment can be performed again.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of an example of a semiconductor integrated circuit device of the present invention.

FIG. 3 is a timing chart showing the operation of one example of the semiconductor integrated circuit device of the present invention.

FIG. 4 is an explanatory diagram showing potential states of special pads and pads in the device in one example of the semiconductor integrated circuit device of the present invention, and the contents of characteristic changes and characteristic evaluations realized thereby.

FIG. 5 is a block diagram showing a configuration of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 ... Special pad (characteristic evaluation adjustment pad), 2,3 element pad (normal pad), 4,5 ... Characteristic evaluation element (transistor), 6 ... Control circuit (characteristic adjustment circuit), 6a ... Equivalent characteristic adjustment circuit, 7... Potential fixing circuit (bias circuit).

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/66 H01L 27/04 E

Claims (8)

[Claims] 1. A semiconductor integrated circuit device comprising a single characteristic evaluation adjustment pad used for evaluating characteristics of a circuit element and adjusting characteristics of an original circuit operation. 2. A bias circuit for biasing the characteristic evaluation adjustment pad, and a bias circuit connected to the characteristic evaluation adjustment pad and a normal pad used for the original circuit operation, wherein the characteristic evaluation is performed via the characteristic evaluation adjustment pad. A characteristic evaluation element, a characteristic adjustment circuit for adjusting the characteristic of the original circuit operation, and an equivalent characteristic adjustment circuit for realizing the characteristic adjustment performed by the characteristic adjustment circuit through the characteristic evaluation adjustment pad. 2. The semiconductor integrated circuit device according to claim 1, wherein: 3. The bias circuit connects the characteristic evaluation adjustment pad to a high-potential-side power supply based on a pulse signal generated when power is turned on, and the characteristic evaluation adjustment pad is connected to the high-potential-side power supply voltage. 3. The semiconductor integrated circuit device according to claim 2, wherein a biased state is maintained. 4. The characteristic evaluation element is connected between the power supply on the high potential side and the characteristic evaluation adjustment pad, and supplied from the characteristic evaluation adjustment pad and the normal pad connected to a reference potential side. 4. The semiconductor integrated circuit device according to claim 3, wherein the transistor is a transistor whose characteristics are controlled with respect to a current capacity and a threshold voltage, the characteristics of which are controlled by a signal. 5. The characteristic adjustment circuit according to claim 2, wherein the characteristic adjustment circuit has a cuttable fuse connected between the circuits, and adjusts the characteristic of the original circuit operation by cutting the fuse. Semiconductor integrated circuit device. 6. The semiconductor integrated circuit device according to claim 5, wherein the characteristic adjustment circuit adjusts characteristics of the original circuit operation such as an access time and a write parameter. 7. The characteristic adjustment circuit adjusts a pulse width of a reference clock signal when an access operation, a write operation, or the like is performed, so that the original circuit operation such as the access time or the write parameter is adjusted. 7. The semiconductor integrated circuit device according to claim 6, wherein characteristic adjustment is performed. 8. The equivalent characteristic adjustment circuit performs a characteristic adjustment equivalent to the characteristic adjustment of the original circuit operation performed by cutting a fuse of the characteristic adjustment circuit. 6. The semiconductor integrated circuit device according to claim 5, wherein the characteristic adjustment circuit is realized by connecting to the semiconductor integrated circuit device.