JPH10154382A - Information recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the detection of digital information at the high probability in the high speed search reproduction of a tape whereon many informations are recorded, by providing a means for processing the reproduced digital information in accordance with clocks of 1st and 2nd reproduction modes. SOLUTION: This device is provided with the 1st reproduction mode for reproducing the digital information at a transfer rate substantially equal to that of the recording time and the 2nd reproduction mode for reproducing the digital information at a transfer rate different from that of the recording time. By a digital information process means consisting of an A/D 5, D/A 20, PCM Processor 11, etc., a reproduced digital signal is processed in accordance with the 1st clock of a specific frequency at the 1st reproduction mode, and at the 2nd mode, the reproduced digital information is processed in accordance with the 2nd clock synchronized to the reproduced digital signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a helical scan type digital information recording / reproducing apparatus, and more particularly to information recording suitable for detecting digital information at the time of variable speed reproduction in which a tape traveling speed is reproduced at a speed different from a normal speed. It relates to a playback device.

[0002]

2. Description of the Related Art In recent helical scan type VTRs,
There is a tendency to improve the quality of reproduced audio. One of the concrete means is to convert an audio signal into a digital signal,
PCM recording is performed in a track section formed by extending at least two rotary heads simultaneously on the tape (overlap period) on the extension of the video signal recording track by compressing the time axis every one field period. There are known ways to do this.

[0003] In such a VTR compatible with time-axis compression PCM recording of audio signals, for example, Japanese Patent Application Laid-Open No. 58-2224.
As described in No. 02, there has been proposed a method of recording a time-axis compressed PCM audio signal also on a track where a video signal is originally recorded. (Hereinafter, this method will be referred to as a PCM multi-track recording method.) This proposal divides a video signal recording track into, for example, five equal parts, and respectively divides the video signal recording track by a time axis compression P.
By recording the CM audio signal, a total of six PCM audio tracks including the overlap period are formed. Therefore, when this VTR is used as an audio-only device, the recording time is six times as long as when it is used for normal video, and high-quality PCM audio can be recorded and reproduced for a long time.

[0004]

However, when a tape having a recording time of 2 hours is used in this system, for example, the recording time is 6 times, that is, 12 hours. Becomes possible. For this reason, it is very troublesome and time-consuming to search for a song to be reproduced by repeating "reproduction", "rewinding", and "fast-forwarding", that is, so-called cueing, as in a conventional VTR during reproduction. .

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to enable digital information to be detected with a high probability even in a high-speed search reproduction in which a tape speed is significantly higher than a normal speed, and a large amount of information is recorded. It is an object of the present invention to provide an information recording / reproducing apparatus capable of quickly and accurately retrieving arbitrary information required at the time of reproduction on a tape.

[0006]

In order to achieve the above object, the present invention has the following configuration. That is, an information recording / reproducing apparatus for recording or reproducing digital information, comprising: a first reproduction mode for reproducing digital information at a transfer rate substantially equal to that at the time of recording; A second reproduction mode for reproducing at a rate, wherein in the first reproduction mode, the reproduction digital signal is processed based on a first clock having a predetermined frequency, and in the second reproduction mode, the reproduction digital signal is processed. Digital information processing means for processing reproduced digital information based on a second clock synchronized with the second clock.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

In this embodiment, a case will be described as an example in which an audio signal converted into a digital signal is recorded and reproduced as recording information.

FIG. 1 is an overall block diagram of an audio recording / reproducing apparatus using the present invention and capable of automatically locating an arbitrary tune during reproduction. In FIG. 1, reference numerals 1 and 2 denote input / output terminals for audio signals, and reference numeral 3 denotes a low-pass filter (LP) for preventing aliasing noise.
F), 4 is a dynamic range compression circuit for an input audio signal, 5 is an analog / digital conversion circuit (A / D converter), 6 is a system controller for controlling modes such as "recording", "playback", "search", and "stop". , 7 is a circuit for generating an ID signal having information such as recorded contents, a program number, a tape count, etc., 8 is a decoder for the ID signal,
27 is an ID information display circuit, 9 is a control circuit of a clock changeover switch built in the PCM processor, 10 is a digital audio memory for one field period, 11 is an error detection / correction at the time of modulation / demodulation or reproduction of a digital audio signal. PCM processor 12 for performing recording, 12 for a recording amplifier, 13 for a multi-controller for selecting and controlling recording / reproducing tracks on the tape 26, 14 for a servo circuit for controlling cylinder rotation and tape running during recording and reproduction, and 15
Is the master clock MCK that is the reference for PCM signal processing
, A preamplifier 16, a reproduction PCM signal equalization circuit 17, a clock reproduced from the equalized reproduction PCM signal, and “1” and “0” data discrimination to the PCM processor 11 A data strobe circuit for supplying data PBD and a reproduction clock PBCK, 20 a digital / analog conversion circuit (D / A converter),
Reference numeral 21 denotes an LPF that attenuates unnecessary high-frequency components generated by sampling, 22 denotes a dynamic range expansion circuit of a reproduced audio signal, 23 denotes a recording / reproduction switch, 24 denotes a cylinder, 25 denotes a rotary head, and 26 denotes a magnetic tape. The dynamic range compression circuit 4 and the dynamic range expansion circuit 20 together constitute a noise reduction system.

In FIG. 1, an audio signal RA input from an input terminal 1 is sufficiently attenuated by a LPF in a high frequency component causing aliasing noise, and then input to a dynamic range compression circuit 4 to reduce the dynamic range. Logarithmic compression to 1/2. The audio signal whose dynamic range has been compressed is converted into a 10-bit digital signal by the A / D converter 5 and supplied to the PCM processor 11. The PCM processor 11 first converts a 10-bit digital audio signal into an 8-bit transmission bit number. This 10-bit / 8-bit compression removes the high-order 2 bits from a small-amplitude signal and maintains the 10-bit precision with 8 bits.
The data is transmitted in bits, and as the amplitude increases, it is transmitted as 8-bit data with 9-bit accuracy, 8-bit accuracy, and 7-bit accuracy near the maximum amplitude. This makes use of the characteristic that quantization noise becomes inconspicuous as the amplitude increases, and therefore, a dynamic range equivalent to 10 bits is secured with the number of transmission bits of 8 bits. The bit-compressed digital audio data is stored in the memory 10 every field period. Then, after being interleaved, for example, 132
, And the error detection / correction code and I
The ID bit supplied from the D signal generation circuit 7 is added, and the time axis is compressed to about 1/6. This time-compressed digital audio signal is suitable for magnetic recording.
After being modulated into the phase mark signal, 5.79 according to the PCM timing signal PCM30 synchronized with the rotation phase of the cylinder 24 supplied from the multi-controller 13.
The data is supplied to the recording amplifier 12 intermittently at a transmission rate of Mbps, and is recorded on the magnetic tape 26 via the switch 23 closed on the REC terminal side during recording.

The PCM timing signal PCM30 and the time-base compressed PCM audio signal will now be described with reference to FIGS. 2, 3, and 4. FIG.

FIG. 2A shows a state of loading a magnetic tape onto a cylinder, and FIG. 2B shows a tape pattern recorded by a PCM multi-track recording method. As can be seen from this figure, in the PCM multi-track recording method, tracks to be recorded or reproduced ( _{Tr 1} , _{Tr 2} ... In FIG. 2).
.. _Tr6 ), a timing signal PCM30 synchronized with the rotational phase of the heads 25a and 25b is required. This timing signal PCM30 is generated by the multi-controller 13 shown in FIG. The multi-controller 13 sets the phase of the signal SW30 to 36 ° × (N−1) [N = 1, based on the head rotation phase detection signal SW30 supplied from the servo circuit 14 via the input terminal 40.
2, ... 6] 6-phase S that generates 6 types of signals delayed by
One signal PCM 30 is selected according to the track to be recorded or reproduced from the W30 generation circuit 44 and the six-phase timing signal, and the time axis compression P at that time is selected.
A track select circuit 45 generates a gate signal SGT representing a CM signal period. FIG.
In the timing chart of (B), (1) is a head phase detection signal SW30, (2) is a PCM timing signal PCM30, and (3) is a gate signal SGT representing a time axis compressed PCM signal period. PC of (2) above
M timing signal PCM30 and gate signal SG of (3)
The subscripts 1, 2, ... 6 of T correspond to the numbers of the tracks selected at the time of recording / reproduction.

The above-described head phase detection signal SW30
Is the tack pulse T generated by the rotation of the cylinder 24.
A signal generated by the servo circuit 14 based on P,
2A is a low level signal during a period when the head 25a scans the 180 ° region of the tape 26 and a high level signal during a period when the head 25b scans the 180 ° region of the tape 26.

FIG. 4 shows the generation timing of the time axis compressed PCM signal RD for the selected track number and the data structure of one track. In FIG. 4, (1) indicates the head phase detection signal SW30, and (2) indicates the input audio signal R.
A, (3) is a time axis compressed PCM signal RD (4) generated corresponding to each selected track (T _r1 , _{Tr 2} ... _{Tr 6} ), and data of 132 blocks constituting one track, and (5) ) Is the format of audio data and other additional data that make up one of the 132 blocks. In the data format of the above (5), S is a block synchronization signal (corresponding to 3 bits), Ad is an address (8 bits), and Q and P are error correction parity words (16 bits).
Bit), ID is an ID signal bit (8 bits), D1,
D2 ... D7 is audio data (56 bits) and CR
CC is an error detection bit (16 bits). In addition,
The ID signal bit is not included in every block. In this embodiment, B0 and B1 of the first and second blocks of the 132 blocks and B44 and B4 of the forty-sixth block in the present embodiment.
5, and the 89th and 90th blocks are included in a total of 6 blocks B88 and B89, and an ID signal of 6 words is added per track.

Here, an ID signal that plays an important role in cueing during reproduction will be described. As described above, the ID signal is given 6 words (48 bits) per track (hereinafter referred to as ID0, ID1,... ID5 to distinguish the 6-word ID signal) during reproduction. As information necessary for cueing, for example, the program number (song number) is set to ID1, and the elapsed time from the beginning of each program (song) is set to ID2 (minutes), ID3.
(Seconds). The information of the ID signal is generated by the ID generation circuit 7 shown in FIG. At the time of reproduction, the ID signals ID1, ID2, and ID3 are detected, the tape is sent by high-speed search until the elapsed time of the program number to be reproduced reaches 0 minutes and 0 seconds, and reproduction is performed from there. The method of detecting the ID signal at the time of high-speed search, which is the most important point in cueing at the time of reproduction, will be described later in detail after the description of normal reproduction using FIG.

Now, the reproduction system will be described. In FIG. 1, a time axis compressed PCM audio signal reproduced from a tape 26 by a head 25 is sufficiently amplified by a preamplifier 16 and then supplied to an equalization circuit 17. Equalization circuit 17
Supplies the reproduced PCM signal PBS to the data strobe circuit after compensating for the intersymbol interference of the reproduced PCM signal due to the differential characteristics and the band limiting characteristics of the head / tape system. The data strobe circuit 18 generates a reproduction clock PBCK from the reproduction PCM signal PBS by using a phase locked loop (PLL), and latches the reproduction PCM signal by the reproduction clock PBCK (“1” of the reproduction PCM signal,
("0" data identification), and supplies the PCM data PBD and the reproduction clock PBCK to the PCM processor 11. In the case of this normal reproduction, the transmission rate of the reproduced PCM signal PBS is 5.79 Mbps, which is the same as that at the time of recording.
A voltage-controlled oscillator (VC
Center frequency f _o of the O) is twice the transmission rate 11.
It is controlled by the f _o control circuit 19 so as to be 58MHz. P supplied from the data strobe circuit 18
The CM data PBD is demodulated by the PCM processor 11,
After error detection / correction, time axis expansion, and deinterleaving, the audio data is bit expanded to 10-bit data and supplied to the D / A converter 20. The ID signal is separated by the PCM processor 11 and supplied to the ID signal decoding circuit 8. The ID signal decoding circuit 8 supplies the ID information to the display circuit 27 and the system controller 6. The 10-bit reproduced digital audio signal is converted into an analog signal by the D / A converter 20 and then the LPF sufficiently attenuates unnecessary high-frequency components generated by sampling, and is supplied to the dynamic range expansion circuit 22. The reproduced audio signal PA expanded to the original dynamic range by the dynamic range expansion circuit 22 is output from the output terminal 2.

Next, a method of detecting an ID signal at the time of high-speed search, which is the most important in the present invention, will be described.

At the time of high-speed search, the biggest problem is that the frequency of the reproduced PCM signal PBS fluctuates with respect to the frequency at the time of normal reproduction. This is because the relative speed between the tape and the head changes because the tape travels at a high speed. As a result, the frequency of the reproduced PCM signal decreases in the forward search and increases in the reverse search. For example, in the case of an 8 mm video standard VTR, this amount of frequency variation is about -1 in a forward 30 × speed search.
1.0%, and about 11.8% in a 30 × speed search in the reverse direction. When the search speed is increased, the frequency variation increases. Therefore, in these states, the reproduced clock PBCK in the data strobe circuit 18
Of the master clock MCK generated on the basis of the head phase detection signal SW30 fluctuates about 11%, so that accurate processing of PCM data cannot be performed. Therefore, in the present invention, a clock changeover switch 59 is provided in the reproduction data processing system, and has a configuration shown in FIG. The portion surrounded by the broken line 11 in FIG. 5 is the PCM processor 11 shown in FIG.

In FIG. 5, a PCM signal reproduced from a tape head system is amplified and equalized, and then supplied to a data strobe circuit 18. The data strobe circuit 18 generates a clock PBCK synchronized with the reproduced PCM signal, and strobes the reproduced PCM signal by the clock PBCK. Then, the reproduction clock PBCK and the strobe data are supplied to the PCM processor 11. P
In the CM processor 11, first, the strobe data of only the selected track section is obtained by the switch 53 and supplied to the adjusting circuit 54. This is because when a PCM signal is also recorded on a track other than the selected track, for example, FIG.
As shown in, you select the first track T _r1, the case of reproduction, even if it is recorded in the other second track T _r2 and the third track T _r3, etc., and demodulates only the first track Tr1 That's why. The window pulse Wi for controlling the switch 53 is generated by a window pulse generation circuit 60.
Is generated by counting the internal clock CK from the edge of the PCM timing signal PCM30. WA of (3) in FIG. 6 is a window pulse. The strobe data output from the switch 53 is supplied to a synchronization detection circuit 54 and a demodulation circuit 55. For example, in the above-described block 132, the synchronization detection circuit 54
The detection of the synchronization signal S determines the boundaries between the blocks. The detection of the synchronization signal S, in other words, the performance of discriminating the block boundary is extremely important for data demodulation and error detection / correction. Therefore, the synchronization detection circuit 54 has a synchronization signal protection function. FIG. 7 shows a specific configuration example of the synchronization detection circuit. In FIG. 7A, reference numeral 71 denotes strobe data P
An input terminal for the BD, an input terminal for the internal clock CK,
73 is a pattern comparison circuit, 74 is a synchronization signal pattern generation circuit, 75 is a counter, 76 is a decoder, 77 is a gate circuit, 78 is a pseudo synchronization detection signal generation circuit, 79 is a select circuit, and 80 is a synchronization detection signal output terminal. It is. FIG.
7A, the strobe data PBD input from the input terminal 71 is supplied to a pattern comparison circuit 73, and is compared with a synchronization signal pattern sent from a synchronization signal pattern generation circuit 74. Then, the pattern comparison circuit 73
In FIG. 7, when the signal patterns match, it is determined that the signal is a synchronization signal.
The synchronization detection signal Sφ as shown in (1) of (B) is supplied to the select circuit 79 and the gate circuit 77. The gate circuit 77 detects the same detection signal S1 only during the gate period (high period) of the synchronization gate pulse GAT as shown in (2) of FIG. 7B sent from the decoder 76 ((3) of FIG. 7B). )
Is supplied to the select circuit 79.

On the other hand, the counter 75 uses the synchronization detection signal BS supplied from the selection circuit 79 as a reset signal.
The internal clock CK input from the input terminal 72 is counted. The count output is supplied to the decoder, detects the count value in one block period, and supplies a synchronization gate pulse GAT to the gate circuit 77 near the detection timing of the next synchronization signal. This is because, for example, when a signal is erroneously detected by a pattern comparison circuit and a signal of erroneous detection is generated as shown in (1) of FIG. 7B, the strobe data can be correctly demodulated by treating this signal as a synchronization detection signal. It is because it disappears. The pseudo synchronization detection signal generation circuit 78 supplies a pseudo synchronization detection signal S2 as shown in (4) of FIG. 7B to the selection circuit 79 according to the timing signal ST1 supplied from the decoder 76. This pseudo synchronization detection signal S2 is, for example, when the synchronization detection signal Sφ or S1 is lost due to a strobe error or the like where the synchronization signal should be originally detected, as shown in the erroneous detection of (1) in FIG. This is to ensure the synchronization detection timing thereafter. The select circuit 79 selects and outputs the above-described synchronization detection signal Sφ, the synchronization detection signal S1 via the gate circuit 77, and the pseudo synchronization detection signal S2. In this selection, the strobe data PBD is a signal whose time axis is compressed and is supplied intermittently as shown in (3) of FIG. 4, so that the synchronization detection signal Sφ is first selected for each field period. ,
Thereafter, the synchronization detection signal S1 via the gate circuit 77 is selected. When the synchronization detection signal S1 via the gate circuit 77 is lost, the pseudo synchronization detection signal S2
Select However, if the synchronization detection signal S1 via the gate circuit 77 is lost a plurality of times in succession, the timing of the gate is expected to be shifted, so that the synchronization detection signal Sφ is selected to return to the initial state. .

The internal clock CK in the synchronization detection circuit 54 shown in FIG. 7 is important in determining the timing of synchronization detection. In the case of normal reproduction, the PCM formed from the head phase detection signal SW30 is used. Master clock generation circuit 1 based on timing signal PCM30
5, the master clock MCK generated at step 5 is used, and at the time of high-speed search, a switch 59 is used to switch the reproduction clock PB generated at the data strobe circuit 18.
CK is used. This is because during normal reproduction, the frequency of the strobe data PBD is constant and equal to that during recording.
Master clock MC unaffected by playback data disturbance
As described above, the frequency of the strobe data PBD fluctuates depending on the tape running direction and the tape speed during the high-speed search as described above. Therefore, the reproduction clock PBCK whose frequency changes in accordance with the frequency fluctuation of the strobe data is used. . The master clock MCK and the reproduction clock P
The switching of BCK is performed using the switch 59 shown in FIG. Clock switch 5 described above
9 is controlled by a control signal SC supplied from the switch control circuit 9. FIG. 8 is a time chart of the control signal SC.
Shown in In FIG. 8, (1) shows the strobe data PBD of the selected track, and (2) shows the time-axis-compressed PC.
Gate signal SG indicating generation and reproduction timing of M signal
T, (3), and (4) are a control signal Sr supplied from the system controller that goes high during a high-speed reverse search and a control signal Sf that goes high during a high-speed forward search. (5) is a switching control signal SC of the switch 59,
(6) and f _o control signal f _c, the VCO in the clock reproducing PLL data strobe circuit (7) is above V
CO is the oscillation center frequency VCOf _o. The clock changeover switch 59 is closed to the A side during a period when the changeover control signal SC is high (during a high-speed search and a time-axis compressed PCM signal is being reproduced), and outputs a reproduced clock PBCK. While the signal SC is low, B
Side and outputs the master clock MCK. Here, the reason why the internal clock CK is used as the reproduction clock PBCK only during the reproduction period of the time-axis compressed PCM signal during the high-speed search is, for example, that the internal clock CK is always used during the high-speed search.
Is used as the reproduction clock PBCK, the pulse width of the window pulse Wi generated by the window pulse generation circuit 60 shown in FIG. 5 increases in the case of the reverse high-speed search as shown in FIG. 6 (FIG. 6 (3)). Wi-B). Signals on tracks other than the selected track are passed, and conversely, in the case of a high-speed forward search, the pulse width becomes narrow (FIG. 6).
(3) Wi-C) This is because the signal of the selected track cannot be sufficiently passed. In addition, the reproduction clock PBCK is output from the PLL of the data strobe circuit 18.
This is even more so because the VCO of the PLL oscillates free and the frequency is not determined during periods other than the reproduction period of the time-axis compressed PCM signal.

Here, the data strobe circuit 18 will be described. FIG. 9 shows a configuration example of the data strobe circuit 18. A portion surrounded by a dotted line 18 is a data strobe circuit. In FIG. 9, reference numeral 81 denotes an equalized reproduction P
CM signal input terminal, 82 is a limiter, 83 is a D-type flip-flop for data strobe, 84 is a phase detection circuit, 85 is a low-pass filter (LPF), 86 is a voltage controlled pressure oscillator (VCO), 87 is A limiter 88 is an output terminal for strobe data, and 89 is an output terminal for a reproduced clock. Numerals 90 and 91 are input terminals for control signals Sf and Sr representing high-speed search in the forward and reverse directions, respectively. The phase detection circuit 84, the LPF 85 and the VCO 86 constitute a clock recovery PLL. In the clock reproducing PLL in the data strobe circuit, and varying the oscillation center frequency f _o of the VCO86 in the normal high-speed search during playback and forward and reverse. This is the playback P
This is because the frequency of the CM signal changes greatly between normal reproduction and high-speed search. If an attempt is made to cope with the frequency fluctuation of the reproduced PCM signal by extending the holding / pulling-in range of the PLL circuit, a so-called pseudo-lock phenomenon occurs, ie, a pull-in phenomenon occurs, or data identification at the time of strobe. Stationary position errors that increase errors will increase. Where the control signal Sf supplied via the data strobe circuit 18 of the clock recovery PLL in the input from the system controller terminals 90 and 91 shown in FIG. 9, it is generated by f _o control circuit 19 by Sr f _o control signal f The center frequency of the VCO is changed depending on the reproduction mode according to _c . Control signals Sr and Sf and f
The _o control signal reproduction mode by the waveform of f _c is shown in FIG. The control signal Sr of (3) in FIG. 8 becomes high level only at the time of the backward high-speed search, and the control signal Sf of (4) becomes high level only at the time of the forward high-speed search. And (6)
F _o control signals the control signal Sr, reverse high-speed search at a high potential E as compared to the potential En of the normal reproduction in accordance with Sf of
r during normal high-speed search, the potential En during normal reproduction.
Becomes lower than the potential Ef. Center frequency and pull-in range of the clock reproducing PLL by the f _o control signal f _c is as shown in FIG. 10. In FIG. 10, f _o is the center frequency during normal playback, _fr is the center frequency during reverse high-speed search, and
The f _f is the center frequency of the forward high-speed search. (For 30 mm speed search with 8mm video standard VTR, f _o =
_{11.58MHz, f f = 12.94MHz, f} f = 1
0.31 MHz. ) Shown in the above f _o control signal f 11 a specific configuration example of a VCO for varying the oscillation center frequency in accordance with _c. Figure 11 (A) is a VCO using LC tank circuit, 100 denotes an input terminal for f _o control signal f _c,
Reference numeral 101 denotes an input terminal of a phase detection output via the LPF 85 in FIG. 9, and reference numeral 102 denotes an output terminal of a VCO output signal.
3 is a tank circuit, 104 is an amplifier for obtaining a loop gain, 105 is a buffer, and 106 is a phase shift circuit. FIG. 11B shows frequency characteristics of the amplitude and the phase of the tank circuit 103. Then Figure 11
The principle of the frequency control of the VCO shown in FIG. The VCO is phase shift amount of the phase shift circuit 106 in the case of zero oscillation center frequency f _o is the resonant frequency of the tank circuit 103.

[0023]

(Equation 1)

## EQU1 ## In this case, the capacitor C1 is, for example, using a variable capacitance diode, the capacitance to vary with f _o control signal f _c supplied via the input terminal 100, the oscillation center frequency varies according to f _o control signal f _c I do. On the other hand, when the phase is delayed by, for example, φ in the phase shift circuit 106 by the phase detection output supplied from the input terminal 101, the tank circuit 10
3, the phase must advance by φ, and the oscillation frequency is
The frequency f becomes lower than the center frequency as shown in FIG.

The data strobe circuit 1 described above
5 is used as the internal clock CK at the time of high-speed search, and the demodulation circuit 55 demodulates the reproduction PCM data for which the block synchronization has been accurately detected by the synchronization detection circuit of FIG. The demodulated reproduced data is detected for each block by an error detection circuit 58. If the block has an error, it is replaced with a data pattern representing the error. The reproduction data in which the error is detected is written to the internal memory 57 in accordance with the write control signal WE synchronized with the reproduction clock PBCK supplied from the memory control circuit 58. After data for one block is written, the data is read out and supplied to the external memory 10 in accordance with a read control signal RE synchronized with the internal clock CK supplied from the memory control circuit 58. The internal memory 57 has a data capacity of two blocks, and during the reproduction period of PCM data, writing and reading are simultaneously performed for each block as needed. The internal memory 57 reads out the reproduction data having the time axis fluctuation in synchronization with the internal clock CK so that the internal clock CK can be used in the subsequent digital processing. The internal clock CK in this case is switched by the switch 59, and is a master clock MCK having a stable frequency during normal reproduction, and a reproduction clock PBCK matching the transmission frequency of the reproduction data during high-speed search.

The reproduced data read from the internal memory 57 is controlled by a control signal R supplied from a memory control circuit 61.
The data is written to the external memory 10 by the AC. When data for one field is written to the external memory 10, error correction using the parity word is performed between the external memory 10 and the error correction circuit 62, and the error data and the corrected data are rewritten. When the error correction is completed, in order to restore the time axis, the data is read at a frequency lower than that at the time of writing, the audio data is supplied to the 8-bit / 10-bit expansion circuit 63, and the ID signal is supplied to the ID separation circuit 64. You. However, in the case of high-speed search reproduction, signals of a plurality of tracks are reproduced by one scan of the head, and the reproduced data covers several tracks as shown in FIG. 12, for example. Therefore, correct error correction may not be performed and erroneous correction may be performed. . Therefore, in this embodiment, error correction is stopped during high-speed search.
This is performed by the memory control circuit 61 inhibiting the rewriting of the error data and the correction data by the control signal SER indicating the high-speed search mode supplied from the system controller 6.

The 8-bit audio data supplied to the 8-bit / 10-bit decompression circuit is converted into 10-bit audio data, and is output via the output terminal 51 to the DA converter 20 shown in FIG.
Supplied to On the other hand, the I output from the ID separation circuit 64
The D data PID is transmitted through the output terminal 52 to the ID shown in FIG.
The data is supplied to the decoder 8. The ID decoder 8 decodes the reproduced ID signal PID and supplies information such as a program number and an elapsed time to the display circuit 27 and the system controller 6.

Now, a specific method of searching for a head by a high-speed search using an ID signal will be described.

FIG. 13 is a flowchart showing an example of the cueing process by the high-speed search. In FIG. 13, first, the number (hereinafter referred to as SNo) of a tune to be searched for is input to the system controller 6 from outside. Next, the music number (hereinafter referred to as PBNo) at the time of starting the cueing is detected by normal reproduction, and SNo and PBNo are compared. If SNo> PBNo, high-speed search detection is performed in the forward direction. During the high-speed search detection, SN
Compare the magnitude relationship between o and PBNo, and SNo = P
The forward high-speed search is performed up to the point where BNo is reached. This time, the elapsed time from the beginning of each song is detected and this is 0 minutes 0
Send the tape by low-speed search until it reaches seconds. This is because, in the case of a high-speed search, even if SNo = PBNo is detected, it is difficult to instantaneously stop the tape running there, resulting in "excessive". On the other hand, when SNo ≦ PBNo, SNo = PBNo, and the reverse high-speed search is performed until, for example, the elapsed time becomes 0 minutes and 30 seconds or less. Then, low-speed search detection is performed until the elapsed time becomes 0 minutes and 0 seconds. The reason why the low-speed search is performed when the elapsed time is 0 minutes and 30 seconds or less is to prevent the elapsed time 0 minutes and 0 seconds from being passed due to the “excessive travel”. Note that the "overrun" is determined by the speed of the high-speed search and the time difference from the detection of the ID signal to the actual stop of the tape running system. For example, if the high-speed search speed is 30 times and the time difference is 0.5 seconds, " The "overshoot" amount corresponds to 15 seconds of normal playback.

FIG. 14 schematically shows the cueing process by the above-described high-speed search based on a tape.

In the above cueing by the high-speed search, I
As the D signal, the song number (program number) and the elapsed time from the beginning of each song were used. In addition, for example, the interval between each song is detected at the time of recording and recorded as an ID signal. The cueing may be performed by detecting an ID signal indicating.

As described above, according to the present embodiment, the frequency of the reproduced PCM signal is changed by changing the oscillation center frequency of the VCO in the clock reproducing PLL according to the tape running speed and the tape running direction during the high-speed search. An accurate clock can be reproduced even when it fluctuates. The clock used as the reference for digital signal processing in the PCM processor is normally reproduced using the master clock generated in synchronization with the rotation phase of the cylinder, and during the high-speed search, the reproduction period of the PCM signal is reproduced by the PLL. By using the reproduction clock synchronized with the reproduced PCM signal and using the master clock during other periods, it is possible to reproduce high-quality sound with extremely small time-axis fluctuation during normal reproduction. At this time, the ID signal can be detected even if the frequency of the reproduced PCM signal varies greatly. In addition, at the time of high-speed search, by stopping the error correction function in the PCM processor, detection of an erroneous ID signal can be prevented, which is effective in performing accurate and quick cueing during reproduction.

[0033]

As described above, according to the present invention, digital information can be detected with a high probability even in a high-speed search reproduction in which the tape speed is significantly higher than the normal speed, and a large amount of information is recorded. In a tape, any information required for reproduction can be searched at high speed and accurately, and the effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram of a system showing an embodiment of the present invention.

FIG. 2 is a schematic diagram and a tape pattern diagram showing a loading state of a tape.

FIG. 3 is a block diagram of a multi-controller and a timing chart of control signals.

FIG. 4 is a diagram showing the generation timing and data pattern of a time-axis compressed PCM signal.

FIG. 5 is a block diagram of a PCM processor.

FIG. 6 is a generation timing chart of a window pulse.

FIG. 7 is a block diagram of a synchronization detection circuit and a timing chart of main signals.

FIG. 8 is a timing chart.

FIG. 9 is a block diagram of a data strobe circuit.

FIG. 10 is a diagram showing a center frequency and a pull-in range of a PLL circuit.

FIG. 11A is a block diagram illustrating a configuration example of a VCO. (B) is a diagram showing a frequency characteristic of the tank circuit.

FIG. 12 is a diagram illustrating a tape pattern and a head scanning trajectory during a high-speed search.

FIG. 13 is a flowchart of a system when performing high-speed cueing.

FIG. 14 is a diagram showing the progress at the time of high-speed cueing.

[Explanation of symbols]

 6: System controller, 7: ID generation circuit, 8: ID decoder, 9: Switch control circuit, 10: Memory, 11: PCM processor, 13: Multi-controller

 ──────────────────────────────────────────────────続 き Continued from the front page (72) Inventor Yuzumi Watani 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture

Claims (1)

[Claims] An information recording / reproducing apparatus for recording or reproducing digital information, comprising: a first reproduction mode for reproducing digital information at a transfer rate substantially equal to that at the time of recording; And a second reproduction mode for reproducing at a different transfer rate. In the first reproduction mode, the reproduction digital signal is processed based on a first clock of a predetermined frequency, and in the second reproduction mode, An information recording / reproducing apparatus comprising digital information processing means for processing reproduced digital information based on a second clock synchronized with a reproduced digital signal.