JPH10154067A - Multiplication circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To input data of a next operation without waiting for the decision of an operation result and to realize a pipeline processing by inputting a multiplicand to respective operation means in synchronizing with the delay time of the respective buts of a multiplier. SOLUTION: A first delay circuit 41 individually delays the respective bits of the multilayer. Adders 21-23 as the operation means whose inputs are connected to gates 11-14 selectively add the respective bits of the multiplier P and the multiplicand Q. A second delay circuit 42 individually delays lower bits outputted from the gate 12 and the adders 21 and 22. A delay circuit 43 delays a flag showing the validity of the multiplier and the multiplicand in an equal way as the maximum delay cycle at the time of the operation. Latches 31-36 input the multiplicand Q inputted to the respective adders in synchronizing with the delay time of the respective bits of the multiplier. Thus, the respective operation means are synchronized and the pipeline processing can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplying circuit, and more particularly, to a multiplying circuit capable of performing pipeline processing.

[0002]

2. Description of the Related Art "Digital signal processing" published by the Institute of Electronics, Information and Communication Engineers, 1975, is known as a document relating to a conventional multiplying circuit.
Shows a carry-save adder structure and a Wallace tree adder structure, and describes a Booth algorithm or the like as a multiplication circuit.

A configuration of the multiplier is such that the input of each adder is simply shifted one bit at a time, and the value of 2 ⁿ of the multiplicand is obtained at each gate so that each bit of the multiplier can be selectively added. General.

FIG. 3 is a block diagram showing a conventional multiplier for performing a multiplication of 4 bits × 4 bits. In the figure, the thin solid line is each bit of the multiplier, and the thick solid line is 4 for the multiplicand.
Bits, hollow lines are addition results including carry bits,
The alternate long and short dash line indicates the least significant bit after addition, the alternate long and two short dashes line indicates the upper 3 bits of the multiplicand, and the broken line indicates 4 bits obtained by adding the carry bit to the upper 3 bits after addition.

Each of the gates 11 to 14 receives the data of the multiplier divided for each bit and the 4-bit multiplicand, and performs a 4-bit × 1-bit operation. Each of the adders 21 to 23 has two gates. The output from is input and the addition is performed.
The sum of the least significant data of the gate that has computed the least significant bit of the multiplier, the least significant data of the adders 21 and 22, and the output data of the adder 23 is output as the computation result.

[0006] Japanese Patent Application Laid-Open No. 4-10028 discloses that
As shown in FIG. 4, a latch 31 is provided between each of the arithmetic units 21 to 23.
And 32 to latch all bits of the partial product,
There is disclosed an arithmetic circuit configured to add the partial products and configured to allow the next value to be input before the operation result is output, thereby increasing the operation speed. In the figure, a thick solid line indicates the 4-bit multiplicand, and a hollow line indicates the addition result including the carry bit or the data after latching.

However, when multiplication is performed by the arithmetic circuit, it is not specified how the multiplier is given or how the multiplier is processed when data advances in the pipeline.

[0008]

In the conventional multiplication circuit shown in FIG. 3, the addition is performed in the adder 21 to the adder 23, and the multiplier and the multiplier are output until the final operation result is output. Since the value of the multiplicand must be stable, the configuration of the multiplier cannot be a pipeline type.

FIG. 2A is a timing chart showing the processing of the multiplication circuit shown in FIG. When P1 is input as a multiplier of the first operation and Q1 is input as a multiplicand at time a, the first operation result is determined at time d and the second operation result is determined at time d.
The multiplier P2 and the multiplicand Q2 for the calculation of
Is the time e after the result of the calculation is output. The time required for each gate and adder to actually perform the operation is short for the operation time from time a to time e, and the other time is waiting for input or holding output data. Is a wasteful time that is not related to the actual operation.

Further, when the second multiplication is performed subsequently,
Until the result of the second multiplication is determined, the same time as the time required for the first multiplication is required. As in the case of the first multiplication, each gate and adder have no relation to the actual operation. Wasteful time.

When the time during which the values of the multiplier and the multiplicand are stable is reduced to be shorter than the total multiplication time in order to eliminate the time irrelevant to the actual operation and to effectively use each gate and the adder. After the operation in the first stage, it is necessary to make the multiplicand stable even if the operation result proceeds to the next stage.

The arithmetic circuit disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 4-10028 merely latches the result of each adder. It is not specified whether or not to perform the calculation, and the configuration is not such that the multiplier can be sequentially changed for each cycle.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and reduces unnecessary time unrelated to actual operation in each operation element, and allows the next operation to be performed without waiting for the finalization of the operation result. It is an object of the present invention to provide a multiplication circuit capable of performing pipeline processing by inputting data.

[0014]

According to the present invention, there is provided, in accordance with the present invention, a plurality of arithmetic means for obtaining a partial product of each bit of a multiplier and a multiplicand, and the multiplication result is obtained by combining the outputs of the respective arithmetic means. A first delay circuit for individually delaying each bit of the multiplier, a second delay circuit for individually delaying lower bits output from each arithmetic means, and And a synchronizing means for synchronizing the multiplicand with the delay time of each bit of the multiplier and inputting it to each arithmetic means.

In the multiplying circuit according to the present invention, one of the calculating means may be configured to be able to input a multiplier and a multiplicand of the next multiplication every time required for the calculation.

In the multiplication circuit according to the present invention, the first and second delay circuits may include a shift register, and the synchronization means may include a plurality of latches connected in series.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a multiplying circuit according to the present invention configured to perform 4 × 4 bit multiplication.

The multiplication circuit according to the present embodiment includes a first delay circuit 41 for individually delaying each bit of a multiplier,
Adders 21 to 23 as operation means whose inputs are connected to gates 11 to 14 so as to selectively add each bit of multiplier P and multiplicand Q; gate 12, adders 21 and 2
And a second delay circuit 42 for individually delaying the lower bits output from 2 and a flag indicating the validity of the operation result from the logical product of the flags indicating the validity of the multiplier and the multiplicand. A delay circuit 43 for performing the same delay and latches 31 to 36 as synchronization means connected to input the multiplicand Q input to each adder in synchronization with the delay time of each bit of the multiplier are configured. I have.

In the figure, similar to FIG. 3 described above, the thin solid line indicates each bit of the multiplier, the thick solid line indicates the addition result including the multiplicand 4 bits, the hollow line indicates the addition result including the carry bit, and the one-dot chain line indicates the least significant bit after the addition. Bit, the two-dot chain line indicates the upper 3 bits of the multiplicand, and the broken line indicates the upper 3 bits after addition plus the carry bit.
Each bit is shown.

The multiplication circuit according to the present embodiment includes latches 31 to 35 between the adders and before input to the gates of the conventional multiplication circuit shown in FIG. It has delay circuits 41 and 42 that delay each output to the result from one to three cycles.

The delay circuits 41 to 43 are, for example, 3, 2,
The upper bit of the multiplier and the lower bit after the operation are configured to be delayed by a 1-bit shift register or a latch connected in series, and the timing can be adjusted to the delay by the latch of the multiplicand. The delay circuits 41 to 43 and the latches 31 to 36 operate with synchronized clocks and have a common reset signal.

This delay circuit can realize a delay of one to three cycles by using a standard TTL by connecting D latches composed of a plurality of bits in series using the same clock as many as necessary for the delay.

Each gate 11-14 has a known standard T
It can be realized by a 4BUSAND circuit using TL or the like.

Next, the operation of the multiplying circuit according to the present embodiment will be described.

FIG. 2B is a timing chart showing the processing of the multiplying circuit of this embodiment shown in FIG.

First, in the first cycle from time a to time b, the multiplier P1 of the first multiplication is set in the delay circuit 41 for each bit, and the multiplicand Q1 is set in the latch A31. At this time, the opening / closing of the gate A11 and the gate B12 is specified by the multiplier registered in the delay circuit, and the adder A
The calculation at 21 is performed.

In the first cycle and the respective operation cycles to be performed thereafter, the least significant bit of the operation result is registered in the delay circuit 42 for obtaining the output result and is delayed by a necessary number of cycles. Further, while the operation in each cycle is being performed, the multiplier and the multiplicand are latched, so that even if the input values of the multiplier and the multiplicand are unstable or change, the processing is not hindered. .

In the second cycle from the time b to the time c, the operation result of the adder A21 is set in the latch D34, and the multiplicand set in the latch A31 is transferred to the latch B32, and is delayed by the delay circuit 41. The higher order bits of the multiplier move. Then, the upper bit delayed for the next operation operates the gate C13. As a result, the adder B is determined by the contents of the latch D34 and the gate C13.
22 performs an operation.

At the same time, the multiplier P2 and the multiplicand Q2 of the second multiplication are input to the delay circuit 41 and the latch A31, respectively.

In the third cycle from time c to time d, the operation result of the adder B22 is set in the latch E35, and the multiplicand set in the latch B32 is transferred to the latch C33 and recorded in the delay circuit 41. The upper bits of the given multiplier move. Then, the upper bit delayed for the next operation operates the gate D14. As a result, the adder C is determined by the contents of the latch E35 and the gate D14.
23 performs the operation.

At the same time, the multiplier P3 and the multiplicand Q3 of the third multiplication are input to the delay circuit 41 and the latch A31, respectively. Further, the adder B22 performs an operation related to the second multiplication based on the contents of the latch D34 and the gate C13.

In the fourth cycle from time d to time e, by combining the operation result of the adder C23 with the lower bits delayed by the delay circuit 42, the multiplication of the multiplier P1 and the multiplicand Q1 is performed. An operation result can be obtained.

At the same time, the adder B22 performs an operation related to the third multiplication based on the contents of the latch D34 and the gate C13, and the adder C22 based on the contents of the latch E35 and the gate D14.
23 performs an operation relating to the third multiplication.

The above processing is repeated, the result of the second multiplication is output in the fifth cycle from time e to time f, and the result of the third multiplication is output in the sixth cycle from time f. Output in the cycle.

When comparing the processing of the conventional multiplication circuit shown in FIG. 2A with the processing of the multiplication circuit of the present invention, the time required until the operation result of the first multiplication is determined is the same.
In the multiplication circuit of the present invention, the time required until the operation result of the second and subsequent multiplications is determined is one cycle,
The apparent multiplication speed is greatly improved.

As described above, under the condition that the operation in each adder is completed in each cycle, the multiplier and the multiplicand can be updated in each cycle, and the pipeline processing for operating the adders in parallel. Becomes possible.

At this time, when setting the multiplier and the multiplicand, a flag indicating the validity of each variable is set. Then, a flag indicating the validity of the operation result is generated by the logical product of the flags, and a flag indicating the validity of the value of the operation result can be generated by performing a delay equivalent to the maximum delay cycle during the operation. .

In the above-mentioned multiplying circuit, a carry-save adder method can be used. In this case, it is necessary to latch the value of the carry output to the next-stage adder, so that the total number of latch circuits is reduced. Need to increase.

In the multiplication circuit according to the above-described embodiment, a circuit for multiplying 4 bits × 4 bits has a four-stage pipeline configuration, but a circuit for multiplication of m bits × n bits is configured. In this case, similarly, the configuration of m stages or the configuration of m / 4 stages is appropriately selected according to the performance of the arithmetic element to be used.

[0041]

According to the multiplication circuit of the present invention, it is possible to perform pipeline processing in synchronization with each operation means, and it is possible to perform conventional multiplication in which either the multiplier or the multiplicand can be changed until the operation result is determined. Compared with the circuit, it is possible to greatly improve the operation speed when performing the multiplication continuously.

Each time one of the calculating means takes a calculation,
When the multiplier and the multiplicand of the next multiplication are configured to be able to be input, the apparent multiplication speed after the second multiplication becomes equal to the time required for the addition by one adder.

When the first and second delay circuits include a shift register and the synchronization means includes a plurality of latches connected in series, the pipeline processing can be performed only by adding a simple configuration to the conventional multiplication circuit. Can be constructed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a multiplication circuit according to the present invention.

FIG. 2 is a timing chart showing each process of the multiplication circuit.

FIG. 3 is a block diagram illustrating a configuration of a conventional multiplication circuit.

FIG. 4 is a block diagram showing another configuration of the conventional multiplication circuit.

[Explanation of symbols]

 11-14 Gate 21-23 Adder 31-35 Latch 41, 42 Delay circuit

Claims (3)

[Claims] 1. A multiplication circuit having a plurality of operation means for obtaining a partial product of each bit of a multiplier and a multiplicand, and outputting a multiplication result by combining outputs of the respective operation means. A first delay circuit for individually delaying each of them; a second delay circuit for individually delaying lower bits output from each of the arithmetic means; and a delay circuit for synchronizing the multiplicand with a delay time of each bit of the multiplier. And a synchronizing means for inputting to the calculating means. 2. The multiplication circuit according to claim 1, wherein one of said calculation means is configured to be able to input a multiplier and a multiplicand of the next multiplication every time required for calculation. 3. The multiplying circuit according to claim 1, wherein said first and second delay circuits include a shift register, and said synchronization means includes a plurality of latches connected in series.