JPH10150145A - Multilayer board and its continuity testing method and work sheet - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a continuity testing method and work sheet capable of judging the fitness of signal wiring and capacitor with a high precision by the continuity testing method. SOLUTION: In the stage of a work sheet 10, the ground layers 22a of individual multilayer board are connected by a connecting wiring layer 22b so that the capacity of a ground layer 22 (the capacity between the ground layers 22a and a stage 50) may be increased. Accordingly, even if the work sheet 10 is warped so as to make a gap S between the bottom face of the work sheet 10 and the stage 10 to reduce the capacity value between the ground layer 22 and the stage 50, the change in the measured value may be a little due to the absolute capacity value. Thus, the fitness of the signal wiring of the multilayer board can be judged with high precision by the measurement of this capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer substrate, a method for inspecting the conduction of a multi-layer substrate, and a work sheet. The present invention relates to a method for inspecting the conduction of a capacitor.

[0002]

2. Description of the Related Art A conventional method for inspecting the conduction of a multilayer substrate will be described with reference to FIG. The energization test is performed by placing a worksheet 210 from which a number of multilayer substrates are taken on a stage (reference electrode) 50 of a capacitance meter (C meter). Here, the measurement of the left signal line L1 in the figure on the worksheet 210 is performed by applying a probe of a C meter to the signal line L1 and measuring the capacitance value of the signal line L1. This measured value is the capacitance C between the signal line L1 and the ground layer 22a of the worksheet 210.
sg and the capacitance Cg (the capacitance of the ceramic substrate 20) between the ground layer 22a and the stage 50.

[0003]

The worksheet has some warpage, and it is difficult to place the worksheet on the stage 50 of the C meter without generating a gap. here,
The right side of the worksheet 210 in the figure is warped, and a gap S exists between the worksheet 210 and the stage 50. For this reason, when measuring the capacitance value of the signal line L1 ′ in which the gap S is generated between the gap 50 and the stage 50,
This measured value is obtained by measuring the capacitance Csg between the signal line L1 'and the ground layer 22a, the capacitance between the ground layer 22a and the stage 5
The capacitance value Cg 'is a sum of the capacitance value of the ceramic substrate 20 and the capacitance value of the gap S. Since the dielectric constant of the gap S is ten times or more that of ceramics or the like, the capacitance Cg ′ is reduced by the gap S between the ground layer 22 a where the gap S does not exist and the stage 50. Significantly lower than For this reason, due to the presence of the gap S, the capacitance value to be measured is significantly reduced, and it may be determined that the signal line L1 'is abnormal even though it is normal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a multi-layer board / multi-layer board with which the quality of wiring and capacitors can be determined with high accuracy by a current test. It is to provide a method and a worksheet.

[0005]

In order to achieve the above object, a multi-layer substrate according to claim 1 is a multi-layer substrate obtained by cutting a work sheet, wherein each multi-layer substrate is disposed on an inner layer or a back surface. It is a technical feature that a work sheet in which a ground layer or a power supply layer is connected to each other by connection wiring is cut.

In order to achieve the above object, a method for inspecting the conduction of a multilayer substrate according to a second aspect of the present invention is directed to a worksheet for forming individual multilayer substrates by cutting, wherein each individual multilayer substrate is disposed on an inner layer or a back surface. A worksheet in which a ground layer or a power supply layer for a substrate is connected to each other by a connection wiring is placed on a reference electrode of a capacitance meter, and a wiring or an electrode of a capacitor formed on the worksheet and the reference electrode The technical feature is to measure the capacitance between the two and to determine the quality of the wiring or the capacitor based on the measured value.

In order to achieve the above object, a worksheet according to a third aspect is a worksheet which is cut into individual multi-layer boards, and is a ground layer or a multi-layer board for an individual multi-layer board disposed on an inner layer or a back surface. A technical feature is that the power supply layers are mutually connected by connection wiring.

According to a fourth aspect of the present invention, there is provided a worksheet according to the fourth aspect, wherein when the worksheet is placed on a reference electrode of a capacitance meter, a ground layer or a power supply connected to each other by the connection wiring. The capacitance between the layer and the reference electrode is 9 times the capacitance between the wiring or capacitor electrode to be inspected on the multilayer substrate and the ground layer or the power supply layer.
It is a technical feature that the number is twice or more.

[0009]

In the multi-layer board according to the first aspect, a work sheet in which a ground layer or a power supply layer (hereinafter, also referred to as a ground layer) for each multi-layer board is connected to each other by connection wiring is cut. That is, at the stage of the worksheet before cutting, by connecting the ground layers and the like for the individual multilayer boards by connection wiring, the capacitance between the ground layers and the like and the reference electrode (measurement mounting table) is increased. . When the capacitance of the wiring of the multilayer substrate is measured, the measured value is obtained by adding the capacitance between the wiring and the ground layer and the like and the capacitance between the ground layer and the reference electrode. Here, the worksheet is warped and the bottom surface of the worksheet and the reference electrode (the mounting table for measurement)
Even if a gap is formed between the ground layer and the reference electrode, the capacitance between the ground layer and the reference electrode is small, but the absolute value of the capacitance between the ground layer and the reference electrode is large. Is small. For this reason, even if the worksheet is warped, the quality of the wiring and the capacitor of the multilayer substrate can be accurately determined by measuring the capacitance.

According to a second aspect of the present invention, at the worksheet stage, the ground layers and the like for the individual multilayer boards are connected to each other by connection wiring at the stage of the worksheet, so that the ground layers and the like-reference electrode (measurement). Capacitance between the mounting table). For this reason, even if the worksheet is warped and a gap is formed between the bottom surface of the worksheet and the reference electrode (measurement mounting table), even if the capacitance value between the ground layer and the reference electrode is reduced, the ground layer and the like are not affected. -The change in the measured value is small because the absolute value of the capacitance value between the reference electrodes is large. For this reason, even if the worksheet is warped, the quality of the wiring and the capacitor of the multilayer substrate can be accurately determined by measuring the capacitance.

In the worksheet according to the third aspect, by connecting the ground layers and the like for the individual multi-layer boards to each other by connection wiring, the electrostatic capacity between the ground layer and the reference electrode (measurement mounting table) is increased. doing. For this reason, even if the worksheet is warped and a gap is formed between the bottom surface of the worksheet and the reference electrode (measurement mounting table), even if the capacitance value between the ground layer and the reference electrode is reduced, the ground layer and the like are not affected. -The change in the measured value is small because the absolute value of the capacitance value between the reference electrodes is large. For this reason, even if the worksheet is warped, the quality of the wiring and the capacitor of the multilayer substrate can be accurately determined by measuring the capacitance.

In the worksheet according to the fourth aspect, the capacitance between the ground layer and the reference electrode mutually connected by the connection wiring of the worksheet and the capacitance of the wiring to be inspected on the multilayer substrate or the electrode of the capacitor and the ground layer are determined. Since the capacitance is at least 9 times the capacitance between the two, the change in the measured value can be reduced to 10% or less, and the quality of the wiring and the capacitor of the multilayer substrate can be appropriately determined.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below with reference to the drawings. FIG. 4J shows a plan view of a worksheet 10 for taking a plurality of multilayer substrates 12 according to one embodiment of the present invention. In this embodiment,
The work sheet 10 is cut along a dotted line in the figure to form a multilayer substrate 12. On each multilayer substrate 12, signal lines L1 to L4 and capacitors C1, C2
Are formed.

A method of manufacturing the multilayer substrate 12 will be described with reference to FIGS. As shown in FIG.
A sputtering layer (Ti layer (0.2 μm) was formed on the upper surface of the ceramic substrate (110 mm × 110 mm) 20 by sputtering.
m) -Cu layer (0.5 μm)).

Next, a resist is uniformly coated on the sputtered layer, exposed and developed, and a current is passed through the opening through the sputtered layer, and electrolytic plating (Cu plating (5 μm) -Ni
After plating (1 μm)) and removing the resist, the exposed sputtered layer is removed by etching, so that the plan view of the ceramic substrate 20 is as shown in FIG. 2B.

Ground layers 2 for 10.times.10 multilayer substrates
2a and a connection wiring layer 22b for connecting the ground layers 22a to each other. Here, the ground layer and the connection wiring layer are provided by plating, but the ground layer and the connection wiring layer can be formed on the ceramic substrate 20 by applying metallization on the green sheet and firing them simultaneously.

FIG. 3C is a sectional view of the ceramic substrate 20 shown in FIG. After an interlayer material (polyimide precursor) is uniformly applied to the ceramic substrate 20 and dried, a photomask film printed with a black circle of 100 μmφ is brought into close contact with the ceramic substrate 20 to form a via, and is exposed with a high-pressure mercury lamp. . This is spray-developed with a solution to form an opening serving as a via having a diameter of 100 μmφ in the interlayer material. After that, a heat treatment is further performed to form a polyimide interlayer insulating layer 26 having an opening 26a serving as a via, as shown in FIG.

Thereafter, Cr (0.
025 .mu.m) -Cu (0.1 .mu.m), a resist is uniformly applied and dried, and then the signal lines L1 to L4 and the capacitors C1 and C2 shown in FIG. Exposure and development are performed to form a lower electrode, and a resist pattern 28 having a predetermined pattern is formed as shown in FIG. And, on the ceramic substrate 20,
A current is passed through the sputtered layer, and by electrolytic plating,
Cu plating (5 μm) and Ni plating (1 μm) are deposited on the non-resist forming portions, and as shown in FIG. 3F, signal lines L1 to L4 (only L1 and L2 are shown in the figure) and capacitors C1, After forming the lower electrode 30 of C2, FIG.
The resist layer 28 is removed as shown in FIG.
The exposed Cr-Cu sputtered layer is removed by etching.

Subsequently, as shown in FIG. 4H, a Ta layer 32 is formed on the lower electrodes 30 of the capacitors C1 and C2 by sputtering, and a resist is formed so as to provide an opening at a predetermined portion of the sputtering. To form Thereafter, the ceramic substrate 20 is immersed in a chemical conversion solution containing about 0.01% of citric acid, a current is applied so that the Ta layer 32 becomes positive, and the Ta layer 32 exposed from the opening of the resist is exposed. among predetermined thickness by anodic oxidation to tantalum oxide (TaO, Ta ₂ O ₅₎ is changed to, the dielectric layer 34
To form

Thereafter, as shown in FIG. 4I, an upper electrode layer 36 is formed on the dielectric layer 34 to form a capacitor C.
The worksheet 10 is completed by setting 1, C2. FIG. 4 (J) shows the worksheet 10 shown in FIG. 4 (I).
FIG. That is, FIG.
(J) shows an II cross section. Thereafter, after inspection of signal lines and capacitors, which will be described later, is performed, the work sheet 10 is cut along the chain lines in the drawing to obtain individual multilayer substrates (10.4 mm × 10.4 mm) 12.

Prior to the cutting, the signal lines L1 to L4 and the capacitors C1,
An inspection is performed using a C meter to determine whether a short circuit or disconnection has occurred with C2. As a C meter used in the present embodiment, for example, Substra manufactured by Teledyne TAC
te Continuity Tester SCT-
1212 is used. This configuration will be briefly described with reference to FIG.

The C meter includes a stage 50 on which the worksheet 10 is placed, a connector blanket 110 connected to the stage 50, a probe needle P pressed against a measurement site of the worksheet 10, and a probe needle P. A probe 100 to be supported and an LCR meter 120 for measuring L, C and R components are provided. From the connector blanket 110 to the LCR meter 120, an HCUR cable for transmitting an H-side current value and an HPOT cable for transmitting an H-side potential value are connected. Also, the LCU that sends the current value on the L side from the probe 100 to the LCR meter 120
The cable and the LPOT cable for transmitting the L-side potential value are connected.

Next, the measurement of the worksheet 10 placed on the stage 50 will be described with reference to FIG. FIG. 6A shows the ground layer 2 on the upper side of the ceramic substrate 20 according to the manufacturing method described above with reference to FIGS.
2 shows a worksheet 10 on which a copper plating layer 22 composed of 2a and a connection wiring layer 22b is formed. On the other hand, FIG.
(B) shows the work sheet 10B in which the copper plating layer 23 including the ground layer 23a and the connection wiring layer 23b is formed not only on the upper side but also on the lower side of the ceramic substrate 20. The upper ground layer 22 a and the lower ground layer 23 a of the ceramic substrate 20
6. Hereinafter, the type shown in FIG. 6A is referred to as an (A) type, and the type shown in FIG. 6B is referred to as a (B) type. The stage 50
An insulating coating 52 is provided on the upper surface of the.

Next, the signal line L1 shown on the left in FIG.
The measurement of the capacitance value will be described with reference to an example. The measurement is performed by applying a probe of a C meter to the signal line L1 and measuring the capacitance value. The measured value Csig is calculated based on the capacitance Csg between the signal line L1 and the ground layer 22a of the worksheet 10, and the capacitance Csg between the ground layer 22a and the stage 5
It is a total value of the capacitance value Cg (the capacitance value of the ceramic substrate 20) between 0 and 0. That is, the measured value Csig can be represented by the following equation 1.

(Equation 1)

Here, when the signal line L1 is disconnected, for example, when the signal line L1 is disconnected at the center, the distance between the ground layer 22a and the stage 50 is reduced. Although the capacitance value Cg is unchanged, the capacitance value Csg between the signal line L1 and the ground layer 22a becomes half since the length of the signal line L1 is halved due to the disconnection. That is, the measured value Csigop at the time of disconnection can be expressed by the following equation (2).

(Equation 2)

On the other hand, when the signal line L1 is short-circuited, for example, when the signal line L1 is short-circuited with the adjacent signal line L2, the distance between the ground layer 22a and the stage 50 is reduced. Although the capacitance value Cg is unchanged, the capacitance value Csg between the signal line L1 and the ground layer 22a is doubled because the signal line L2 is added to the signal line L1 due to the short circuit. That is, the measured value Csigsh at the time of short circuit can be expressed by the following equation (3).

(Equation 3)

Next, a description will be given of the measurement of the capacitance value in which the probe P is applied to the upper electrode of the capacitor C1 shown on the left side in FIG. 6A. Measured value Ccc of capacitor C1
Is the capacitance value Ccg of the capacitor and the ground layer 2
This is the sum of the capacitance value Cg between the stage 2a and the stage 50. That is, the measured value Ccc can be expressed by the following equation (4).

(Equation 4)

When the capacitor C1 is short-circuited, the measured value Cccsh at the time of the short-circuit becomes the capacitance value Cg between the ground layer 22a and the stage 50.

Here, as described above with reference to FIG. 10A, if the value of Cg is small as in the prior art worksheet 210, even if the value of Csg is halved due to disconnection,
Conversely, even if the value doubles due to a short circuit, the amount of change in the measured value Csig is small. In the determination of the quality of the signal line, the measurement error range is set to a predetermined range centered on the reference value when the signal line is normal (no short circuit or disconnection occurs) as shown in Equation 1 above. In some cases, a signal line that has been disconnected is determined to be appropriate, and conversely, a signal line in which no short circuit or disconnection has occurred is determined to be defective.

Further, as described above with reference to FIG. 10A, when the worksheet is warped and a gap S exists between the worksheet 10 and the stage 50, the ground layer 22a and the stage The capacitance value Cg 'between 50 and 50 is
The capacitance value Cg of the ceramic substrate 20 is combined with the capacitance value of the gap S. Since the dielectric constant of the gap S is ten times or more that of ceramics or the like, the capacitance Cg ′ is smaller than the capacitance Cg between the ground layer 22 a having no gap S and the stage 50 due to the gap S. Significantly lower than in comparison. For this reason, the capacitance value to be measured is significantly reduced due to the existence of the gap S, and the signal line L
In some cases, it was determined that 1 ′ was abnormal although it was normal.

In this embodiment, as described above with reference to FIG. 2, the ground layer 22a has a size of 10 × 10,
These are connected to each other by the connection wiring layer 22b.
That is, since the capacitance value Cg between the ground layer 22a and the stage 50 is set to be 100 times as large as that of the unconnected one, the quality of the signal line and the capacitor can be accurately determined. Here, the capacitance value Cg is set to 100 times, but the capacitance value Cg is the capacitance at the measurement point (the above-mentioned Cg).
By making it 9 times or more of sg or Cc), the change of the measured value can be made 10% or less, and the quality of the signal line and the capacitor of the multilayer substrate can be properly judged.

Here, work sheet 1 shown in FIG.
The results of simulation of the measurement of the worksheet 10B shown in FIG. 6 and FIG. 6B will be described with reference to the tables in FIGS. In the diagram, FIG.
(A) and a simulation result of the configuration of the prior art shown in FIG. 10 (B) are shown for comparison. In the configurations of FIGS. 10A and 10B, the ground layers 22a are not connected to each other. Note that FIG.
FIG. 10 shows the A-type worksheet 210 shown in FIG.
(B) shows the B type worksheet 210B.

First, referring to FIG. 7, a description will be given of a simulation result relating to the measurement of a signal line. here,
It is assumed that the signal lines L1 and L3 of the worksheet 10 shown in FIG. In the chart, FIG.
10A and the prior art B type shown in FIG. 10B are displayed as "before connection of power supply, ground, etc.". On the other hand, the worksheet 10 shown in FIG.
And, the worksheet 10B shown in FIG.
After connection of ground etc. ". Here, the signal line L3 has a signal line width W of 0.1 mm and a signal line length L of 10 mm.
It is. On the other hand, the signal line L1 has a signal line width W of 0.1 mm.
And the signal line length L is 100 mm.

First, the signal line L1 (signal line length L: 100 mm) when the substrate of the conventional type A substrate shown in FIG. 10A has no warpage will be described. The measured value Csig of the signal line L1 includes a capacitance value Csg (12.04 pF) between the signal line L1 and the ground layer 22a and a capacitance value Cg (8. 0
6pF) (4.83 pF).

When the signal line L1 is disconnected, as described above, the capacitance value Csg between the signal line and the ground layer is halved, and the measured value Csigop becomes 3.45 pF (Equation 2).
), Which is about 71% of the normal value (4.83 pF). In this embodiment, the error of the measured value is set to ± 30%. Here, since only 29% has changed from the normal state, the signal line L1 in which the disconnection has occurred is determined to be appropriate.

Conversely, when a short circuit occurs in the signal line L1, the capacitance value Csg between the signal line and the ground layer doubles as described above (see Equation 3), and the measured value Csigsh becomes 6.
04 pF, which is about 125% of the normal value (4.83 pF). As described above, the error of the measured value is ± 3.
If it is set to 0%, it is determined that the signal line L1 in which the short circuit has occurred is appropriate.

On the other hand, in the worksheet 10 of the present embodiment shown in FIG.
The capacitance Cg between the stage and the stage 50 is 100 times (8
05.71 pF). Therefore, FIG.
The measured value Csi of the signal line L1 of the A type substrate shown in FIG.
g is 11.86 pF, and the measured value Csigop when a disconnection occurs is 5.98 pF, which is 5 times the normal value.
0%. On the other hand, the measured value Csigsh
Is 23.38 pF, which is 197% of the normal value. For this reason, when a disconnection or short circuit occurs, it can be reliably detected.

Subsequently, the signal line L1 '(FIG. 10) when the conventional type A substrate shown in FIG. 10A is warped and a gap S (0.2 mm) exists between the substrate and the stage.
The right signal line L1 ') in (A) will be described. The measured value Csig ′ of the signal line L1 ′ is determined by the capacitance Csg (12.
04pF) and the capacitance value Cg '(2.86 pF) between the ground layer and the stage affected by the gap S (2.31 pF). That is, the capacitance value Cg 'between the signal line and the ground layer becomes small due to the gap S, and the measured value Csig' becomes approximately 48% of the value without the gap S (4.83 pF). It is determined that a short circuit has occurred in spite of the above.

On the other hand, in the worksheet 10 of this embodiment shown in FIG. 6A, the capacitance Cg between the ground layer and the stage is set to 805.71 pF. The signal line L1 'of the type substrate (FIG. 6)
The capacitance value Cg 'between the ground layer and the stage of the right signal line L1' in (A) decreases only to 285.71 pF, and the measured value Csig 'of this signal line L1 becomes 11.55 pF. Here, the value when there is no gap S (11.86p
Since it corresponds to about 97% of F), it can be determined that it is normal. That is, a normal signal line is not determined to be disconnected or short-circuited.

Further, with reference to FIG. 8, a simulation result regarding the measurement of the capacitor will be described. Here, the capacitor C of the worksheet 10 shown in FIG.
1, C2 shall be measured. In the table, the capacitor C1 has an electrode size W of 0.2 mm ² and a capacitor capacitance Ccg of 16.00 pF. On the other hand, the capacitor C2 is 0.5 mm ² and the capacitor capacitance Ccg is 100.00 pF.

First, the result of simulating the capacitor C2 in the case where the substrate of the conventional type A substrate shown in FIG. The measured value Cc of the capacitor C2 is the capacitance Ccg (1
00.00 pF) and the capacitance Cg (8.06 pF) between the ground layer and the stage (7.46 pF). Here, when a short circuit occurs in the capacitor, the measured value Ccsh becomes only the capacitance value Cg (8.06 pF) between the ground layer and the stage, and changes only up to about 108% of the normal value (7.46 pF). do not do.
If the measurement error is in the range of ± 30%, the short-circuited capacitor C2 is determined to be normal.

On the other hand, when the substrate of the type A substrate of the present embodiment shown in FIG. 6A has no warpage, the capacitor Cc of the capacitor C2 in the normal state is the capacitor Ccg (10
0.00pF) and the total capacitance Cg (805.71 pF) between the ground layer and the stage, 88.86p
It becomes F. Here, when a short circuit occurs in the capacitor C2, the measured value Ccsh becomes 805.71 pF, which changes to about 906% of the normal value. For this reason, a short circuit can be reliably detected.

Subsequently, the A-type substrate of the prior art has a warp and a gap S (0.2 mm) between the substrate and the stage.
The following describes the capacitor C1 '(the right capacitor C1' in FIG. 10A) in the case where there is. The measured value Cc 'of this capacitor C1' is 2.78 pF. In other words, the capacitance Cc between the signal line and the ground layer is reduced by the gap S, and the measured value Cc 'becomes approximately 38% of the value without the gap S (7.46 pF). It is determined that a short circuit has occurred despite the presence.

Here, in the worksheet 10 of this embodiment, the capacitance value Cg between the ground layer and the stage is 80.
Since the capacitance is set to 5.71 pF, the capacitance value between the ground layer and the stage is not affected by the capacitor C1 'of the A type substrate (the capacitor C1' on the right side in FIG. 6A) even if the air gap S exists. Cg drops only to 285.71 pF, and the measured value Cc 'of this capacitor C1 is 74.07 pF.
Becomes Here, the value when there is no gap S (88.96)
pF), which is about 83%, so that it can be determined to be normal. That is, a normal capacitor is not determined to be short-circuited.

In this embodiment, the ground layer 22a
Are connected by a thin connection wiring layer 22b to increase the capacitance of the ground layer. Here, the capacitance can be increased by providing the ground layer on one surface of the ceramic substrate 20 without dividing the ground layer without connecting the ground layer with the connection wiring. However, in this way, metallization (copper plating layer 2
2), the copper plating layer 2 at the time of cutting as shown in FIG.
2 becomes burrs 22v, which causes lifting during mounting, and also removes burrs and becomes metal scraps, which may cause a short circuit. Furthermore, peeling off on the interlayer insulating layer (polyimide layer) 26
6h occurs. For this reason, in this embodiment, the ground layers 22a are connected to each other by the thin connection wiring layers 22b.

Although the signal lines and capacitors on the A type substrate (worksheet) have been described in detail here, as shown in the tables of FIGS. 7 and 8, the B type shown in FIG. By connecting the ground layer also to the substrate (worksheet), it is possible to appropriately determine a short circuit / disconnection. In the above embodiment, the method of increasing the capacitance value by connecting the ground layer has been described. However, it is also possible to increase the capacitance value by connecting the power supply layer.

[Brief description of the drawings]

FIG. 1 is a side view of a ceramic substrate for multi-layering a multilayer substrate according to a first embodiment of the present invention.

FIG. 2 is a plan view of a ceramic substrate on which a ground layer is formed.

FIGS. 3 (C), 3 (D), 3 (E), 3
(F) and FIG. 3 (G) are step diagrams showing the steps of manufacturing the multilayer substrate.

4 (H) and 4 (I) are process diagrams showing a manufacturing process of a multilayer substrate, and FIG. 4 (J) is a plan view of a completed worksheet shown in FIG. 4 (I). It is.

FIG. 5 is a configuration diagram showing a configuration of a C meter.

6A is a cross-sectional view of an A-type worksheet, and FIG. 6B is a cross-sectional view of a B-type worksheet.

FIG. 7 is a table showing simulation results regarding measurement of signal lines.

FIG. 8 is a table showing simulation results regarding measurement of a capacitor.

FIG. 9 is a cross-sectional view of the multilayer substrate when a work sheet in which a ground layer is solid-coated is cut.

FIG. 10A is a cross-sectional view of an A-type worksheet according to the related art, and FIG. 10B is a cross-sectional view of a B-type worksheet according to the related art.

[Explanation of symbols]

 10, 10A Worksheet 12 Multilayer substrate 20 Ceramic substrate 22 Copper plating layer 22a Ground layer 22b Connection wiring layer 23 Copper plating layer 50 Stage L1, L2, L3, L4 Signal line C1, C2 Capacitor P Probe

Continued on the front page (72) Inventor Takashi Kanamori 14-18 Takatsuji-cho, Mizuho-ku Nagoya-shi Inside Japan Specialty Ceramics Co., Ltd. (72) Inventor Tomomi Sonoda 14-18 Takatsuji-cho, Mizuho-ku Nagoya

Claims (4)

[Claims] 1. A multi-layer board formed by cutting a work sheet, wherein a work sheet is formed by connecting ground layers or power supply layers for individual multi-layer boards provided on an inner layer or a back surface to each other by connection wiring. A multilayer substrate, comprising: 2. A worksheet for cutting into individual multi-layer boards, which is formed by connecting ground layers or power supply layers for individual multi-layer boards provided on the inner layer or the rear face with connection wiring. A worksheet is placed on a reference electrode of a capacitance meter, and the capacitance between the wiring or capacitor electrode formed on the worksheet and the reference electrode is measured. Based on the measured value, the wiring or the capacitor is measured. A method for inspecting a multilayer substrate, comprising: judging the quality of a substrate. 3. A worksheet that becomes individual multilayer substrates by cutting, wherein ground layers or power supply layers for individual multilayer substrates disposed on the inner layer or the rear surface are connected to each other by connection wiring. And worksheet. 4. When the worksheet is placed on a reference electrode of a capacitance meter, a capacitance between a reference layer and a ground layer or a power supply layer interconnected by the connection wiring is a multilayer substrate. 4. The worksheet according to claim 3, wherein the capacitance is at least 9 times the capacitance between the wiring or the electrode of the capacitor to be inspected and the ground layer or the power supply layer.