JPH10149942A - Multilayered ceramic capacitor and manufacture of multilayered chip inductor - Google Patents

Multilayered ceramic capacitor and manufacture of multilayered chip inductor

Info

Publication number
JPH10149942A
JPH10149942A JP8325992A JP32599296A JPH10149942A JP H10149942 A JPH10149942 A JP H10149942A JP 8325992 A JP8325992 A JP 8325992A JP 32599296 A JP32599296 A JP 32599296A JP H10149942 A JPH10149942 A JP H10149942A
Authority
JP
Japan
Prior art keywords
external electrode
paste
ceramic capacitor
resistance metal
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8325992A
Other languages
Japanese (ja)
Inventor
Yukio Nishinomiya
幸雄 西宮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokin Corp
Original Assignee
Tokin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokin Corp filed Critical Tokin Corp
Priority to JP8325992A priority Critical patent/JPH10149942A/en
Publication of JPH10149942A publication Critical patent/JPH10149942A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Manufacturing Cores, Coils, And Magnets (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the occurrence of voids in an external electrode by forming the electrode by spraying metal powder-containing paste prepared by scattering low-resistance metal powder in an organic vehicle and drying and baking the paste. SOLUTION: Paste prepared by mixing low-resistance metal powder in a organic vehicle and kneading the vehicle after adding glass frit to the vehicle is used for the formation of an external electrode. The external electrode paste is jetted into the output port of an internal electrode layer masked with a masking jig 6 from the spray nozzle 5 of a spraying device. After the paste is sprayed, the past is dried and baked and a multilayered ceramic capacitor element 7 is obtained through a plating process. Therefore, the reliability of the element can be improved by reducing the occurrence of delamination troubles in the element by suppressing the occurrence of pores in the external electrode.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、積層セラミックコ
ンデンサ及び積層チップインダクタの製造方法に係り、
特に外部電極の形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer ceramic capacitor and a multilayer chip inductor,
In particular, the present invention relates to a method for forming an external electrode.

【0002】[0002]

【従来の技術】従来の技術について下記にセラミックコ
ンデンサを例に述べる。
2. Description of the Related Art A conventional technique will be described below using a ceramic capacitor as an example.

【0003】図2に示すように、内部に金属導体からな
る内部電極層2と誘電体セラミック層1とが交互に積層
された構造をもつ積層セラミックコンデンサは、従来、
その製造方法として、セラミック粉末を有機バインダと
有機溶剤を用いてスラリーとした後、ドクターブレード
法等で剥離処理を施したフィルム上に一定の厚さのシー
ト、つまりグリーンシートを形成する。
As shown in FIG. 2, a multilayer ceramic capacitor having a structure in which an internal electrode layer 2 made of a metal conductor and a dielectric ceramic layer 1 are alternately laminated inside is conventionally known.
As a manufacturing method, a ceramic powder is formed into a slurry using an organic binder and an organic solvent, and then a sheet having a constant thickness, that is, a green sheet is formed on a film subjected to a release treatment by a doctor blade method or the like.

【0004】そのグリーンシート上に、パラジウム(P
d)、銀(Ag)等の低抵抗金属を有機ビヒクルに分散
させた金属粉入りペーストを、ある一定の形状で外部電
極3に接続する取り出し口7aを得られるようにスクリ
ーン印刷し、そのグリーンシートを打ち抜き、複数枚重
ねあわせ、熱プレス成形することにより積層体を得る。
又、誘電体セラミック層もスクリーン印刷で行い、印刷
のみで積層体を得る方法もある。
On the green sheet, palladium (P
d) A paste containing a metal powder in which a low-resistance metal such as silver (Ag) is dispersed in an organic vehicle is screen-printed so as to obtain an outlet 7a for connection to the external electrode 3 in a certain shape, and its green color is obtained. A laminate is obtained by punching out sheets, stacking a plurality of sheets, and performing hot press molding.
There is also a method in which the dielectric ceramic layer is also subjected to screen printing, and a laminate is obtained only by printing.

【0005】その後、脱バインダを行い、焼成して、内
部電極層2に接続する外部電極3をディップ法により塗
布し、乾燥、焼き付けをする。そして、外部電極3を半
田めっき端子とするために、ニッケルめっき、半田めっ
きの順でめっきを施す。
After that, the binder is removed, baked, and the external electrode 3 connected to the internal electrode layer 2 is applied by dipping, dried and baked. Then, in order to use the external electrode 3 as a solder plating terminal, plating is performed in the order of nickel plating and solder plating.

【0006】一方、積層チップインダクタは、磁性層に
印刷された導体パターンを前記磁性層に設けられたスル
ホールを介して接続し、前記磁性層に積層して螺旋状コ
イルと磁性体内部に導体パターンの最上層が最下層の先
端を前記磁性体の対向する側面に露出し、ディップ法に
より塗布し、乾燥、焼付けし、外部電極を半田めっき端
子とするために、ニッケルめっき、半田めっきの順でめ
っきを施し、外部電極端子を形成したものである。
On the other hand, a multilayer chip inductor connects a conductor pattern printed on a magnetic layer via a through hole provided in the magnetic layer, and laminates the conductor pattern on the magnetic layer to form a spiral coil and a conductor pattern inside the magnetic body. The uppermost layer exposes the tip of the lowermost layer to the opposite side surface of the magnetic body, is applied by a dipping method, dried and baked, and in order of nickel plating and solder plating in order to make the external electrode a solder plated terminal. The external electrode terminals are formed by plating.

【0007】[0007]

【発明が解決しようとする課題】しかし、外部電極3を
形成するにあたり、ディップ法で形成した場合、外部電
極3に空気の巻き込みによる空孔4が発生してしまい、
後のめっき工程の際に、その空孔4のある外部電極3の
厚みの薄い箇所により、めっき液が浸透し、めっき液が
内部電極層2の内部まで侵入し、結果としてデラミネー
ション(層間剥離)を発生させてしまうという問題点が
あった。
However, when the external electrodes 3 are formed by the dipping method, the holes 4 are generated in the external electrodes 3 due to entrainment of air.
In the later plating step, the plating solution penetrates through the thin portion of the external electrode 3 having the holes 4 and the plating solution penetrates into the internal electrode layer 2, resulting in delamination (delamination). ) Is caused.

【0008】本発明の目的は、積層セラミックコンデン
サ及び積層チップインダクタの外部電極に生ずる空孔の
発生を改善し、素子のデラミネーション不良を少なく
し、信頼性に優れた外部電極を形成する積層セラミック
コンデンサ及び積層チップインダクタの製造方法を提供
することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to improve the generation of voids in the external electrodes of a multilayer ceramic capacitor and a multilayer chip inductor, to reduce the occurrence of delamination of the element, and to form a highly reliable external electrode. An object of the present invention is to provide a method for manufacturing a capacitor and a multilayer chip inductor.

【0009】[0009]

【課題を解決するための手段】本発明は、上述の問題点
を解決するため、低抵抗金属を有機ビヒクルに分散させ
た金属粉入りペーストをスプレー状に吹き付け、乾燥、
焼き付けすることで外部電極を形成することを特徴とす
る積層セラミックコンデンサ及び積層チップインダクタ
の製造方法である。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems by spraying a paste containing metal powder in which a low-resistance metal is dispersed in an organic vehicle in the form of a spray, drying, and drying the paste.
A method for manufacturing a multilayer ceramic capacitor and a multilayer chip inductor, wherein an external electrode is formed by baking.

【0010】本発明は、誘電体セラミック層と低抵抗金
属からなる内部電極層とを交互に積層し、さらに積層方
向上下に保護層を形成した積層体に低抵抗金属からなる
外部電極を設けてなる積層セラミックコンデンサの製造
方法であって、内部電極層の取り出し口端面に低抵抗金
属ペーストをスプレー状に吹きつけ、乾燥、焼き付けを
行い外部電極を形成することを特徴とする積層セラミッ
クコンデンサの製造方法である。
According to the present invention, a dielectric ceramic layer and an internal electrode layer made of a low-resistance metal are alternately laminated, and an external electrode made of a low-resistance metal is provided on a laminate in which protective layers are formed above and below in the laminating direction. A method of manufacturing a multilayer ceramic capacitor, comprising: spraying a low-resistance metal paste on an end face of an outlet of an internal electrode layer in a spray form, drying and baking to form an external electrode. Is the way.

【0011】又、本発明は、磁性層に印刷された導体パ
ターンを接続し前記磁性層を積層して螺旋状コイルを磁
性体内部に形成し、前記導体パターンの先端を磁性層の
側面に露出し、外部電極端子に接続した積層チップイン
ダクタにおいて、前記導体パターンの取り出し口端面に
低抵抗金属ペーストをスプレー状に吹きつけ、乾燥、焼
き付けて外部電極端子を形成することを特徴とする積層
チップインダクタの製造方法である。
[0011] The present invention also provides a method for connecting a conductor pattern printed on a magnetic layer, laminating the magnetic layer to form a helical coil inside the magnetic body, and exposing the tip of the conductor pattern to the side surface of the magnetic layer. A multilayer chip inductor connected to an external electrode terminal, wherein a low-resistance metal paste is sprayed on the end face of the opening of the conductor pattern in a spray shape, and dried and baked to form an external electrode terminal. It is a manufacturing method of.

【0012】本発明による積層セラミックコンデンサ及
び積層チップインダクタの製造方法によれば、外部電極
に空孔による欠陥が解消され、後のめっき工程の際にめ
っき液が内部に侵入することがないため、デラミネーシ
ョン不良の低減が図られ、信頼性の高い積層セラミック
コンデンサ及び積層チップインダクタを得ることができ
る。
According to the method for manufacturing a multilayer ceramic capacitor and a multilayer chip inductor of the present invention, defects due to voids in external electrodes are eliminated, and a plating solution does not enter inside during a later plating step. Delamination failure can be reduced, and a highly reliable multilayer ceramic capacitor and multilayer chip inductor can be obtained.

【0013】[0013]

【発明の実施の形態】本発明を積層セラミックコンデン
サ及び積層チップインダクタの製造方法を詳細に述べ
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with respect to a method for manufacturing a multilayer ceramic capacitor and a multilayer chip inductor.

【0014】(発明の実施の形態1)本発明の実施の形
態1では、積層セラミックコンデンサについて説明す
る。まず、コンデンサの母材となる強誘電体セラミック
に、鉛(Pb)系ペロブスカイト構造を持つ粒径が1ミ
クロン以下の粉末を使用し、内部電極層には銀(Ag)
とパラジウム(Pd)が70:30の割合の合金粉末を
用いた。
(Embodiment 1) In Embodiment 1 of the present invention, a multilayer ceramic capacitor will be described. First, a powder having a lead (Pb) -based perovskite structure and a particle diameter of 1 micron or less is used for a ferroelectric ceramic serving as a base material of a capacitor, and silver (Ag) is used for an internal electrode layer.
An alloy powder having a ratio of palladium (Pd) of 70:30 was used.

【0015】前記誘電体セラミックの粉末に、ポリビニ
ルブチラールの有機バインダ、及びエチルセロソルブ、
ブチルカルビトールの有機溶剤を混合分散してセラミッ
クスラリーとした。
An organic binder of polyvinyl butyral and ethyl cellosolve are added to the dielectric ceramic powder.
An organic solvent of butyl carbitol was mixed and dispersed to obtain a ceramic slurry.

【0016】また、内部電極ペーストには、前記配合比
率の混合粉末を有機バインダとしてエチルセルロースと
有機溶剤としてα−テルピネオール、ステアリン酸を用
いた有機ビヒクルに投入し、3本ロールにて混練したも
のを使用した。
The internal electrode paste is prepared by adding the mixed powder having the above-mentioned mixing ratio to an organic vehicle using ethyl cellulose as an organic binder and α-terpineol and stearic acid as an organic solvent, and kneading with a three-roll mill. used.

【0017】成膜は、ドクターブレード法にて乾燥上が
りでキャリアフィルム上に18μmの厚さになるように
調整した。そして、そのグリーンシート上に内部電極ペ
ーストを10mm×3mmの短冊状のパターンに2μm
厚みに印刷した。
The film was adjusted by a doctor blade method so as to have a thickness of 18 μm on the carrier film after drying. Then, on the green sheet, the internal electrode paste was formed into a strip pattern of 10 mm × 3 mm by 2 μm.
Printed to thickness.

【0018】こうして作製したグリーンシートを切断
後、コンデンサの対向電極構造をなすように75層積層
して、その上下に250μmの厚みをもつ保護膜を挟
み、熱プレスにて熱圧着後に個々の素子形状に切断し
た。
After the green sheet thus produced is cut, 75 layers are laminated so as to form a counter electrode structure of a capacitor, a protective film having a thickness of 250 μm is sandwiched between the layers, and after thermocompression bonding with a hot press, individual elements are formed. Cut into shapes.

【0019】400℃で7時間バインダを除去した後、
900時間で4時間焼成し、焼結体を得た。
After removing the binder at 400 ° C. for 7 hours,
It was fired at 900 hours for 4 hours to obtain a sintered body.

【0020】一方、外部電極には金属として銀100%
の粉末を、有機バインダとしてエチルセルロース、有機
溶剤としてα−テルピネオール、ケロシンを用いた有機
ビヒクルに投入し、ガラスフリットを添加し3本ロール
にて混練したものを使用した。
On the other hand, the external electrode is made of 100% silver as a metal.
Was added to an organic vehicle using ethyl cellulose as an organic binder and α-terpineol and kerosene as an organic solvent, a glass frit was added, and the mixture was kneaded with three rolls.

【0021】そして、図1に示すように、この焼結体の
内部電極層の取り出し口7aの端面に外部電極ペースト
をスプレー装置のスプレーノズル5にて厚さ150μm
を目標に噴射圧力、距離、及びペースト粘度を調整し、
外部電極ペーストの噴射を行った。
Then, as shown in FIG. 1, an external electrode paste was applied to the end face of the outlet 7a of the internal electrode layer of this sintered body by a spray nozzle 5 of a spray device to a thickness of 150 μm.
Adjust the injection pressure, distance, and paste viscosity with the goal of
External electrode paste was sprayed.

【0022】その際、内部電極層の取り出し口7aの端
面以外の側面は、図1のようなマスキング治具6により
マスキングを施した。スプレー塗布後、乾燥、焼き付け
をして、めっき工程を経て本発明の積層セラミックコン
デンサ素子7を得た。
At this time, the side faces other than the end face of the outlet 7a for the internal electrode layer were masked by a masking jig 6 as shown in FIG. After spray coating, drying and baking were performed, and a multilayer ceramic capacitor element 7 of the present invention was obtained through a plating step.

【0023】本発明による積層セラミックコンデンサと
比較するため、外部電極を従来法のディッピングにて作
製したものも用意し、研磨により、それぞれ100個を
断面観察を行い、外部電極の空孔の発生率の検査を行っ
た。また、それぞれ10000個ずつ用意して、めっき
液中に任意の時間浸漬し、デラミネーション発生を加速
させることで、その効果を比較した。それぞれの結果を
表1に示す。
For comparison with the monolithic ceramic capacitor according to the present invention, an external electrode prepared by dipping according to a conventional method was also prepared, and 100 sections were observed by polishing, and the porosity of the external electrode was calculated. Was inspected. In addition, 10,000 samples were prepared and immersed in a plating solution for an arbitrary time to accelerate the occurrence of delamination, thereby comparing the effects. Table 1 shows the results.

【0024】 [0024]

【0025】表1からわかるように、従来品に比べて、
本発明品がセラミックコンデンサのデラミネーション発
生率が改善されていることがわかる。
As can be seen from Table 1, compared to the conventional product,
It can be seen that the product of the present invention improves the delamination occurrence rate of the ceramic capacitor.

【0026】(発明の実施の形態2)本発明の実施の形
態2を積層チップインダクタの製造を例にあげて、詳細
に述べる。
(Embodiment 2) Embodiment 2 of the present invention will be described in detail with reference to an example of manufacturing a multilayer chip inductor.

【0027】まず、絶縁性の磁性粉末と、この磁性粉末
に対してポリビニルブチラールの有機バインダ、及びエ
チルセロソルブ、ブチルカルビトールの有機溶剤を混合
分散してスラリー化した。
First, an insulating magnetic powder and an organic binder of polyvinyl butyral and an organic solvent of ethyl cellosolve and butyl carbitol were mixed and dispersed with the magnetic powder to form a slurry.

【0028】このスラリーをドクターブレード法にて乾
燥上がりでキャリアフィルム上に200〜600μmの
厚さになるように調整し、長尺な絶縁性磁性体のグリー
ンシートを作り、所定の寸法に切断する。
The slurry is dried by a doctor blade method and adjusted to a thickness of 200 to 600 μm on a carrier film to form a long green sheet of an insulating magnetic material, which is cut into a predetermined size. .

【0029】以下、図3の工程図に示すように、得られ
たグリーンシート11の上に内部導体21をAgペース
トにて所定のパターンにスクリーン印刷し、乾燥させ、
前記内部導体2の次層との接続部分を窓状のスルーホー
ル41に残し、内部導体21が露出するように、前記絶
縁性磁性スラリーをスクリーン印刷法により磁性層12
を印刷し、乾燥させる。
Hereinafter, as shown in the process diagram of FIG. 3, the internal conductor 21 is screen-printed in a predetermined pattern with an Ag paste on the obtained green sheet 11, and dried.
The insulating magnetic slurry is screen-printed on the magnetic layer 12 so that the internal conductor 21 is exposed, leaving a portion of the internal conductor 2 connected to the next layer in the window-like through hole 41.
Print and dry.

【0030】次に、前記内部導体の接続部分と接続する
ようにして、内部導体21を所定のパターンに印刷し、
乾燥させる。
Next, the internal conductor 21 is printed in a predetermined pattern so as to be connected to the connection portion of the internal conductor.
dry.

【0031】同様にして、次々と積層印刷を所定数、繰
り返し、内部導体で螺旋状のコイルを形成し、また、形
成されたコイルの両端は外部に露出するように形成す
る。
Similarly, lamination printing is repeated one after another by a predetermined number to form a spiral coil with the internal conductor, and both ends of the formed coil are formed so as to be exposed to the outside.

【0032】このようにして、積層印刷された積層体の
上に上部絶縁性磁性層としてのグリーンシート11をホ
ットプレスにより圧着し、未焼成積層体を形成する。
The green sheet 11 as the upper insulating magnetic layer is pressed on the laminated printed body by hot pressing to form an unfired laminated body.

【0033】こうして作製した前記積層体をチップ形状
に切断した。
The laminate thus manufactured was cut into a chip shape.

【0034】これらの未焼成チップ所定の温度と所定の
時間バインダーを除去した後、600℃で所定時間焼成
し、焼結体を得た。
After removing the binder at a predetermined temperature and for a predetermined time, the unfired chips were fired at 600 ° C. for a predetermined time to obtain a sintered body.

【0035】一方、外部電極には、金属として銀100
%の粉末を、有機バインダとしてエチルセルロース、有
機溶剤としてα−テルピネオール、ケロシンを用いた有
機ビヒクルに投入し、ガラスフリットを添加し3本ロー
ルにて混練したものを使用した。
On the other hand, silver is used as a metal for the external electrode.
% Powder was put into an organic vehicle using ethyl cellulose as an organic binder and α-terpineol and kerosene as an organic solvent, and a glass frit was added thereto and kneaded with a three-roll mill.

【0036】そして、この焼結体の内部導体取り出し口
である端面に、外部電極ペーストをスプレー装置にて厚
さ150μmを目標に噴射圧力、距離、及びペースト粘
度を調整し、外部電極ペーストの噴射を行った。
The injection pressure, distance, and paste viscosity of the external electrode paste were adjusted to a thickness of 150 μm with a spray device on the end surface of the sintered body, which was the internal conductor outlet, to spray the external electrode paste. Was done.

【0037】その際、内部電極取り出し口端面以外の側
面は、図1のようなマスキングを施した。
At this time, masking as shown in FIG. 1 was applied to the side surfaces other than the end surface of the internal electrode outlet.

【0038】スプレー塗布後、乾燥、焼き付けをして、
めっき工程を経て本発明による積層チップインダクタを
得た。
After spray coating, drying and baking,
Through a plating process, a multilayer chip inductor according to the present invention was obtained.

【0039】本発明の実施の形態による積層チップイン
ダクタと比較するため、外部電極を従来法のディッピン
グにて作製したものも用意し、研磨により、それぞれ1
00個を断面観察を行い、外部電極の空孔の発生率の検
査を行った。また、それぞれ10000個ずつ用意し
て、Niめっき液中に任意の時間浸漬し、デラミネーシ
ョン発生を加速させることで、その効果を比較した。そ
れぞれの結果を表2に示す。
For comparison with the multilayer chip inductor according to the embodiment of the present invention, an external electrode manufactured by dipping according to a conventional method is also prepared, and each of the external electrodes is polished.
A cross section of 00 pieces was observed, and the occurrence rate of voids in the external electrode was inspected. In addition, 10,000 samples were prepared and immersed in a Ni plating solution for an arbitrary period of time to accelerate the occurrence of delamination, thereby comparing the effects. Table 2 shows the results.

【0040】 [0040]

【0041】[0041]

【発明の効果】以上、述べたように、積層セラミックコ
ンデンサ及び積層チップインダクタの外部電極に生ずる
空孔の発生を抑制し、素子のデラミネーション不良を少
なくし、信頼性に優れた外部電極を形成する積層セラミ
ックコンデンサ及び積層チップインダクタの製造方法を
提供することができる。
As described above, the generation of voids in the external electrodes of the multilayer ceramic capacitor and the multilayer chip inductor is suppressed, the delamination failure of the element is reduced, and the external electrodes having excellent reliability are formed. To provide a method for manufacturing a multilayer ceramic capacitor and a multilayer chip inductor.

【図面の簡単な説明】[Brief description of the drawings]

【図1】スプレー吹き付けをした際のマスキングを示し
た斜視図。
FIG. 1 is a perspective view showing masking when spraying is performed.

【図2】ディップ法により形成された外部電極の空気巻
き込みによる空孔を示した説明図。図2(a)は、中に
閉じ込められた空孔を示す説明図。図2(b)は、外部
に穴となった空孔を示す説明図。
FIG. 2 is an explanatory diagram showing holes formed by entrainment of air in external electrodes formed by a dipping method. FIG. 2A is an explanatory view showing holes confined therein. FIG. 2B is an explanatory diagram illustrating holes that are holes on the outside.

【図3】積層チップインダクタの積層工程図。FIG. 3 is a view showing a stacking process of the multilayer chip inductor.

【符号の説明】[Explanation of symbols]

1 誘電体セラミック層 2 内部電極層 3 外部電極 4 空孔 5 スプレーノズル 6 マスキング冶具 7 セラミックコンデンサ素子 7a 取り出し口 11 グリーンシート 12 磁性層 21 内部導体 41 スルーホール DESCRIPTION OF SYMBOLS 1 Dielectric ceramic layer 2 Internal electrode layer 3 External electrode 4 Void 5 Spray nozzle 6 Masking jig 7 Ceramic capacitor element 7a Outlet 11 Green sheet 12 Magnetic layer 21 Inner conductor 41 Through hole

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 誘電体セラミック層と低抵抗金属からな
る内部電極層とを交互に積層し、さらに積層方向上下に
保護層を形成した積層体に低抵抗金属からなる外部電極
を設けてなる積層セラミックコンデンサの製造方法であ
って、内部電極層の取り出し口端面に低抵抗金属ペース
トをスプレー状に吹きつけ、乾燥、焼き付けを行い外部
電極を形成することを特徴とする積層セラミックコンデ
ンサの製造方法。
1. A laminated structure in which dielectric ceramic layers and internal electrode layers made of a low-resistance metal are alternately laminated, and an external electrode made of a low-resistance metal is provided on a laminated body in which protective layers are formed above and below in the laminating direction. What is claimed is: 1. A method for manufacturing a ceramic capacitor, comprising spraying a low-resistance metal paste onto an end face of an outlet of an internal electrode layer, drying and baking to form external electrodes.
【請求項2】 磁性層に印刷された導体パターンを接続
し前記磁性層を積層して螺旋状コイルを磁性体内部に形
成し、前記導体パターンの先端を磁性層の側面に露出
し、外部電極端子に接続した積層チップインダクタにお
いて、前記導体パターンの取り出し口端面に低抵抗金属
ペーストをスプレー状に吹きつけ、乾燥、焼き付けて外
部電極端子を形成することを特徴とする積層チップイン
ダクタの製造方法。
2. A conductor pattern printed on a magnetic layer is connected, the magnetic layers are stacked to form a spiral coil inside the magnetic body, and a tip of the conductor pattern is exposed on a side surface of the magnetic layer. In a multilayer chip inductor connected to a terminal, a low-resistance metal paste is sprayed on an end face of an outlet of the conductor pattern in a spray shape, and dried and baked to form an external electrode terminal.
JP8325992A 1996-11-20 1996-11-20 Multilayered ceramic capacitor and manufacture of multilayered chip inductor Pending JPH10149942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8325992A JPH10149942A (en) 1996-11-20 1996-11-20 Multilayered ceramic capacitor and manufacture of multilayered chip inductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8325992A JPH10149942A (en) 1996-11-20 1996-11-20 Multilayered ceramic capacitor and manufacture of multilayered chip inductor

Publications (1)

Publication Number Publication Date
JPH10149942A true JPH10149942A (en) 1998-06-02

Family

ID=18182899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8325992A Pending JPH10149942A (en) 1996-11-20 1996-11-20 Multilayered ceramic capacitor and manufacture of multilayered chip inductor

Country Status (1)

Country Link
JP (1) JPH10149942A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006012889A1 (en) * 2004-08-03 2006-02-09 Epcos Ag Electric component comprising external electrodes and method for the production of an electric component comprising external electrodes

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006012889A1 (en) * 2004-08-03 2006-02-09 Epcos Ag Electric component comprising external electrodes and method for the production of an electric component comprising external electrodes
US8194388B2 (en) 2004-08-03 2012-06-05 Epcos Ag Electric component comprising external electrodes and method for the production of an electric component comprising external electrodes

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