JPH10145338A - Command processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute a command without errors, even when SEA(single event upset) is generated by storing an error correcting code added to a command from the ground in a memory, so as to correct the error at the time of executing the command. SOLUTION: At the time of receiving a delaying command 6 added with an error-correcting code and a command executing time from a command transmission source, a command-receiving circuit 1 stores the received command 6 in a memory 2. A command-managing part 3 periodically compares the present time and time information in the command 6 stored in the memory 2 with each other, and when a command executing time designated by time information within the delaying command comes, the part 3 reads the delaying command from the memory to send the delaying command to an error-correcting code decoding circuit. An error correcting code decoding circuit 4 corrects the error of command data by decoding, based on the error-correcting code and sends the correct command data to a command executing part 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a command processing device mounted on a satellite, for example.

[0002]

2. Description of the Related Art FIGS. 27 and 28 show a command processing device for mounting on a satellite based on a conventional technology. FIG. 27 is a configuration diagram showing a configuration of a command processing device in a conventional example. In FIG. 27, 1 is a command receiving circuit, 2 is a memory, 3 is a command management unit, 5 is a command execution unit, 32 is a delay command,
8 is command data. FIG. 28 shows the delay command 32
FIG. 28 is a format diagram showing a format of a delay command.
8 is command data.

Next, the operation will be described. When receiving the delay command 32 from the command source on the ground, the command receiving circuit 1 writes the received delay command 32 into the memory 2. The command management unit 3 periodically compares the current time with the time information 7 in the delay command 6 stored in the memory 2 and, when the command execution time specified by the time information 7 in the delay command is reached, the command management unit 3 3 reads a command from the memory 2 and sends command data 8 to the command execution unit 5. The command execution unit 5 executes a process based on the contents specified by the command data 8.

[0004]

Since the conventional command processing device mounted on a satellite is configured as described above, it is a phenomenon that 0/1 of memory data and the like generated by radiation in a space environment is inverted. SEU (Single
(Event Upset) occurs on the memory in which the command is stored, the content of the command data changes. Alternatively, the content of the command data also changes when an SEU occurs in the processor of the command processing device during the reception processing of the command or the writing or reading to or from the memory. Therefore, the content of the command sent from the command source and the content of the command read when the execution time is reached are different,
There has been a problem that erroneous processing may be executed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has a satellite-mounted command processing for executing a command without error even when an SEU occurs in a memory storing a command or in a processor. The aim is to obtain a device.

[0006]

According to a first aspect of the present invention, there is provided a command processing apparatus mounted on a satellite, which stores an error correction code added to a command from the ground in a memory, and performs error correction when the command is executed.

[0007] A command processing device for mounting on a satellite according to a second aspect of the present invention includes a BCH for error correction added to a command from the ground.
The code is stored in a memory, and error correction is performed when a command is executed.

[0008] A third aspect of the present invention is a command processing apparatus for mounting on a satellite, which comprises an error correction Ree added to a command from the ground.
The d-Solomon code is stored in a memory, and error correction is performed when a command is executed.

A command processing device for mounting on a satellite according to a fourth aspect of the present invention is to add an error correction code to a command from the ground, store the command in a memory, and correct the error when executing the command.

A command processing device for a satellite according to a fifth aspect of the present invention adds a BCH code for error correction to a command from the ground and stores it in a memory, and performs error correction when the command is executed.

A sixth aspect of the present invention provides a command processing device for mounting on a satellite, in which a command from the ground is used for error correction Reed-Sol.
An omon code is added and stored in a memory, and error correction is performed when a command is executed.

A command processing device for onboard satellite according to a seventh invention is a command processing device for transmitting a command from the ground to which an error correction code is added.
Once the error correction code is decoded to correct the error, the error correction code is added and stored in the memory, and the error is corrected again when the command is executed.

The command processing device for mounting on a satellite according to an eighth aspect of the present invention provides a command from the ground to which the BCH code for error correction is added, decodes the BCH code for error correction once, corrects the error, and executes the BCH code for error correction. A code is added and stored in the memory, and error correction is performed again when the command is executed.

A ninth aspect of the present invention provides a command processing apparatus for mounting on a satellite, in which a command from the ground to which an error correction Reed-Solomon code is added is temporarily converted to an error correction Ree-Solomon code.
The error correction is performed by decoding the d-Solomon code, adding the error correction Reed-Solomon code to the memory, and performing the error correction again when the command is executed.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1, 2 and 3 show a first embodiment of a command processing device according to the present invention. FIG. 1 is a block diagram showing a first embodiment. In FIG. 1, 1 is a command receiving circuit,
2 is a memory, 3 is a command management unit, 4 is an error correction code decoding circuit, 5 is a command execution unit, 6 is a delay command, and 8 is command data. FIG. 2 is a format diagram showing the format of the delay command 6. In FIG.
Is time information indicating the execution time of the delay command, 8 is command data, and 9 is an error correction code. FIG. 3 is an explanatory view showing the principle of the error correction code. In the figure, reference numeral 10 denotes an error correction code encoding circuit, 11 denotes input data, 12 denotes input data added with an error correction code, and 12 ′ denotes an error including an error. This is input data to which a correction code has been added.

Next, the operation will be described. When receiving the delay command 6 with the error correction code added from the command source, the command receiving circuit 1 writes the received delay command into the memory 2. The command management unit 3 periodically compares the current time with the time information 7 in the delay command 6 stored in the memory 2 and, when the command execution time specified by the time information 7 in the delay command is reached, the command management unit 3 Reference numeral 3 reads the delay command from the memory and sends the delay command to the error correction code decoding circuit 4. The error correction code decoding circuit decodes based on the error correction code 9, corrects the error of the command data, and transmits the correct command data to the command execution unit 5. The command execution unit 5 executes a process based on the contents specified by the command data 8. Next, error correction using an error correction code will be described. In FIG. 3, when input data 11 is input to an error correction code encoding circuit 10, the error correction code encoding circuit calculates an error correction code 9 from the value of the input data, adds the error correction code 9 to the input data, and outputs the result. When the input data 12 to which the error correction code is added is transmitted on a communication channel, an error may occur in the data due to noise. When the input data 12 'to which the error correction code is added, including the error, is input to the error correction code decoding circuit 4, the error correction code decoding circuit calculates the position where the error has occurred, and corrects the error of the error-containing data 12'. Then, correct data 11 is output. The error correction code is used in various fields such as a compact disc in addition to a communication field. Various coding methods, such as a BCH code and a Reed-Solomon code, are known as coding methods for generating such an error-correctable code.

Since the command processing device according to the first embodiment is configured as described above, it is possible to correct an error generated by the SEU in the memory while the command is being stored at the time of executing the command.

Embodiment 2 FIG. 4, 5, 6, and 7 show a second embodiment of the command processing device of the present invention. FIG. 4 is a block diagram showing an embodiment. In FIG. 4, 1 is a command receiving circuit, 2 is a memory, 3 is a command management unit, 13
Is a BCH code decoding circuit, 5 is a command execution unit, 14 is a delay command, and 8 is command data. FIG. 5 is a format diagram showing the format of the delay command 14. In FIG. 5, 7 is time information indicating the execution time of the delay command, 8 is command data, and 15 is a BCH code. The BCH code is Bose, Chaudhuri, Ho
This is a bit error correction code devised by cquenghem. FIG. 6 shows an example of a BCH (63, 56) code encoding circuit when the code length n = 63 and the information length k = 56. In the figure, 16 and 17 are switches. B in FIG.
An example of a decoding circuit for a CH (63, 56) code is shown. BCH
The code can be configured in a wide range of code length and information length such as code length n = 31 and information length k = 26.

Next, the operation will be described. When receiving the delay command 14 with the BCH code added from the command source, the command receiving circuit 1 writes the received delay command into the memory 2. The command management unit periodically compares the current time with the time information 7 in the delay command 14 stored in the memory 2, and when the command execution time specified by the time information 7 in the delay command is reached, the command management unit 3 Reads the delay command from the memory,
The signal is transmitted to the CH code decoding circuit 13. The BCH code decoding circuit decodes the BCH code, corrects an error in the command data, and transmits correct command data to the command execution unit 5. The command execution unit 5 executes a process based on the contents specified by the command data. Next, the operation of generating a BCH code by the BCH encoding circuit will be described. While input data is being input to the BCH encoding circuit shown in FIG. 6, the switches 16 and 17 are at the position (1), and the input data is output as it is and an error correction code is calculated at the same time. When the input of the input data is completed, the switches 16 and 17 become (2)
And the calculated error correction code is output.
Next, an error correction operation by the BCH decoding circuit will be described. When input to the BCH decoding circuit shown in FIG. 7, the data part containing the error is written into the delay buffer and the intermediate data for error correction called a syndrome is calculated. Next, the presence or absence of an error and the position where the error occurred are determined from the value of the syndrome, and the data is corrected and output. BCH (6
In the (3, 56) code, error correction of 1 bit out of 63 bits is possible.

Since the command processing device according to the second embodiment is configured as described above, even when a random bit error occurs in the memory by the SEU during storage of the command, it can be corrected at the time of executing the command. .

Embodiment 3 8, 9, 10, and 11 show a third embodiment of the command processing device of the present invention. FIG.
FIG. 8 is a configuration diagram showing an embodiment. In FIG. 8, 1 is a command receiving circuit, 2 is a memory, 3 is a command management unit,
18 is a Reed-Solomon encoding / decoding circuit, 5 is a command execution unit, 19 is a delay command, and 8 is command data. FIG. 9 is a format diagram showing the format of the delay command 19. In FIG. 9, 7 is time information indicating the execution time of the delay command, 8 is command data,
20 is a Reed-Solomon code. Reed
-Solomon code is a symbol error correction code devised by Reed and Solomon. In FIG. 10, one symbol = 8 bits, code length n = 255, information length k =
Reed-Solomon (255, 2
23) An example of an encoding circuit is shown. In FIG.
2 is a switch. FIG. 11 shows Reed-Solomo.
An example of a decoding circuit for an n (255, 223) code is shown. Re
The ed-Solomon code also has a symbol length,
It can be configured in a wide range of code length and information length.

Next, the operation will be described. When receiving the delayed command 19 to which the Reed-Solomon code is added from the command source, the command receiving circuit 1 writes the received delayed command into the memory 2. The command management unit 3 periodically compares the current time with the time information 7 in the delay command 19 stored in the memory 2, and when the command execution time specified by the delay command time information 7 is reached, the command management unit 3. Reference numeral 3 reads the delay command from the memory and transmits the delay command to the Reed-Solomon encoding / decoding circuit 18. The Reed-Solomon code decoding circuit decodes the Reed-Solomon code, corrects an error in the command data, and transmits correct command data to the command execution unit 5. Command execution unit 5
Then, the processing is executed based on the contents specified by the command data. Next, an operation of generating a Reed-Solomon code by the Reed-Solomon encoding circuit will be described. Reed-Solomon (25 shown in FIG. 10)
5,223) The encoding circuit inputs and processes 8-bit (1 symbol) data in parallel. Reed-Solom
While input data is being input to the on-encoding circuit, switch 2
Reference numerals 1 and 22 are located at the position (1), and the input data is output as it is, and the error correction code is calculated at the same time. When the input of the input data is completed, the switches 21 and 22 are at the position (2), and the calculated error correction code of 32 symbols is output. Next, an error correction operation by the Reed-Solomon decoding circuit will be described. Re shown in FIG.
When input to the ed-Solomon decoding circuit, the data part containing the error is written into the delay buffer and the intermediate data for error correction called a syndrome is calculated. Next, the presence or absence of an error, the position of the symbol in which the error occurred, and the magnitude of the symbol error are obtained from the syndrome value, and the data is corrected and output. Reed-Solomon
With the (255, 223) code, error correction of 16 symbols out of 255 symbols is possible.

Since the command processing device according to the third embodiment is configured as described above, even when a continuous burst error is generated by the SEU in the memory while the command is being stored, it can be corrected at the time of executing the command. it can.

Embodiment 4 12, 13, and 14 show a fourth embodiment of the command processing device of the present invention. FIG.
FIG. 12 is a configuration diagram showing an embodiment. In FIG.
3 is a command receiving circuit, 24 is an error correction code coding circuit, 2 is a memory, 3 is a command management unit, 4 is an error correction code decoding circuit, 5 is a command execution unit, 25 is a delay command, 6 is a coding delay command. , 8 are command data. FIG. 13 is a format diagram showing the format of the delay command 25. In FIG. 13, reference numeral 7 denotes time information indicating the execution time of the delay command, and reference numeral 8 denotes command data. FIG. 14 is a format diagram showing the format of the encoding delay command 6. In FIG. 14, reference numeral 7 denotes time information indicating the execution time of the delay command, 8 denotes command data, and 9 denotes an error correction code.

Next, the operation will be described. When receiving the delay command 25 from the command source, the command receiving circuit 23 transmits the received delay command 25 to the error correction code encoding circuit 24. Error correction code coding circuit 24
Encodes the delay command 25 and writes the encoded delay command 6 with the error correction code 9 added to the memory 2. The command management unit 3 periodically stores the current time and the memory 2
The command management unit 3 reads the command from the memory when the command execution time specified by the time information 7 in the delayed command is compared with the time information 7 in the encoded delay command 6 stored in the The command 6 is transmitted to the error correction code decoding circuit 4. The error correction code decoding circuit decodes based on the error correction code 9, corrects the error of the command data, and outputs the correct command data to the command execution unit 5.
Send to The command execution unit 5 executes a process based on the contents specified by the command data 8. The operations of the error correction code encoding circuit and the error correction code decoding circuit are the same as in the first embodiment.

Since the command processing device according to the fourth embodiment is configured as described above, even when no error correction code is added to a command from the ground, the command is generated by the SEU in the memory during command storage. The error can be corrected when the command is executed.

Embodiment 5 FIG. FIGS. 15, 16, and 17 show a fifth embodiment of the command processing device of the present invention. FIG.
FIG. 15 is a configuration diagram showing an embodiment. In FIG.
3 is a command receiving circuit, 26 is a BCH encoding circuit,
2 is a memory, 3 is a command management unit, 13 is a BCH code decoding circuit, 5 is a command execution unit, 25 is a delay command, 1
4 is an encoding delay command, 8 is command data.
FIG. 16 is a format diagram showing the format of the delay command 25. In FIG. 16, reference numeral 7 denotes time information indicating the execution time of the delay command, and reference numeral 8 denotes command data.
FIG. 17 is a format diagram showing the format of the encoding delay command 14. In FIG. 17, 7 is time information indicating the execution time of the delay command, 8 is command data,
Reference numeral 15 denotes an error correction BCH code.

Next, the operation will be described. When receiving the delay command 25 from the command source, the command receiving circuit 23 transmits the received delay command 25 to the BCH code encoder 26. The BCH code encoding circuit 26 encodes the delay command 25 and outputs the BCH code 15
Is written to the memory 2. The command management unit 3 periodically compares the current time with the time information 7 in the encoded delay command 14 stored in the memory 2, and when the command execution time specified by the time information 7 in the delay command is reached, the command management unit 3 The management unit 3 reads the command from the memory and sets the encoding delay command 14 to BCH
The data is transmitted to the code decoding circuit 13. BCH code decoding circuit 13
Performs decoding based on the BCH code 15, corrects the error of the command data, and transmits the correct command data to the command execution unit 5. The command execution unit 5 executes a process based on the contents specified by the command data 8. The operations of the BCH code encoding circuit and the BCH code decoding circuit are the same as in the second embodiment.

Since the command processing device according to the fifth embodiment is configured as described above, even if an error correction code is not added to a command from the ground, a random number is stored in the memory by the SEU during storage of the command. Even when a serious bit error occurs, it can be corrected at the time of command execution.

Embodiment 6 FIG. FIGS. 18, 19 and 20 show a sixth embodiment of the command processing device of the present invention. FIG.
FIG. 18 is a configuration diagram showing an embodiment. In FIG.
3 is a command receiving circuit, 27 is a Reed-Solomo
n code encoding circuit, 2 is a memory, 3 is a command management unit,
18 is a Reed-Solomon encoding / decoding circuit, 5 is a command execution unit, 25 is a delay command, 19 is an encoding delay command, and 8 is command data. FIG. 19 is a format diagram showing the format of the delay command 23. In FIG. 19, reference numeral 7 denotes time information indicating the execution time of the delay command, and reference numeral 8 denotes command data. FIG. 20 is a format diagram showing the format of the encoding delay command 19. In FIG. 20, 7 is time information indicating the execution time of the delay command, 8 is command data, and 20 is Ree.
d-Solomon code.

Next, the operation will be described. When receiving the delay command 25 from the command source, the command receiving circuit 23 converts the received delay command 25 into Reed-So
The signal is transmitted to the lomon encoding circuit 27. Reed-
The Solomon encoding circuit 27 has a delay command 25
, And writes an encoding delay command 19 to the memory 2 to which the Reed-Solomon code 20 is added. The command management unit 3 periodically compares the current time with the time information 7 in the coded delay command 19 stored in the memory 2, and when the command execution time specified by the time information 7 in the delay command is reached, the command management unit 3 The management unit 3 reads the command from the memory and sets the encoding delay command 19 to R
The signal is transmitted to the seed-Solomon code decoding circuit 18.
The Reed-Solomon encoding / decoding circuit 18
Decoding is performed based on the Solomon code 20, the error of the command data is corrected, and the correct command data is transmitted to the command execution unit 5. The command execution unit 5 executes a process based on the contents specified by the command data 8.
Reed-Solomon code encoder, Reed-
The operation of the Solomon code decoding circuit is the same as that of the third embodiment.

Since the command processing device according to the sixth embodiment is configured as described above, even if no error correction code is added to a command from the ground, the command processing device continuously executes SEU on the memory during command storage. Even when a temporary burst error occurs, it can be corrected at the time of command execution.

Embodiment 7 FIGS. 21 and 22 show a command processing apparatus according to a seventh embodiment of the present invention. FIG. 21 is a block diagram showing an embodiment. In FIG. 21, reference numeral 28 denotes a command receiving circuit, 29 denotes an error correction code decoding circuit A, 2 denotes a memory, 3 denotes a command management unit, and 4 denotes an error correction code decoding circuit B. 5, a command execution unit; 6, a delay command; and 8, command data. FIG. 22 is a format diagram showing the format of the delay command 6. In FIG.
Reference numeral 7 denotes time information indicating the execution time of the delay command, 8 denotes command data, and 9 denotes an error correction code.

Next, the operation will be described. Upon receiving the delay command 6 with the error correction code 9 added from the command source, the command receiving circuit 28 transmits the received delay command 6 to the error correction code decoding circuit A29. The error correction code decoding circuit A29 performs decoding based on the error correction code 9, corrects the error of the delay command 6, and writes the correct delay command 6 to the memory 2. The command management unit 3 periodically updates the current time and the delay command 6 stored in the memory 2.
Are compared, and the time information 7 in the delayed command is compared.
When the command execution time specified by (1) is reached, the command management unit 3 reads the delay command from the memory and transmits the delay command to the error correction code decoding circuit B4. The error correction code decoding circuit B4 decodes again based on the error correction code 9, corrects the error of the command data, and transmits the correct command data to the command execution unit 5. The command execution unit 5 executes a process based on the contents specified by the command data 8.

Since the command processing device according to the seventh embodiment is configured as described above, even if an error occurs during transmission and an error occurs in the memory during storage of a command by the SEU, the command is executed at the time of command execution. Can be corrected.

Embodiment 8 FIG. 23 and 24 show a command processing apparatus according to an eighth embodiment of the present invention. FIG. 23 is a block diagram showing an embodiment. In FIG. 23, 28 is a command receiving circuit, 30 is a BCH code decoding circuit A, 2 is a memory, 3 is a command management unit, and 13 is a BCH code decoding circuit B, 5 Is a command execution unit, 14 is a delay command, and 8 is command data. FIG. 24 is a format diagram showing the format of the delay command 14. In FIG. 24, 7 is time information indicating the execution time of the delay command, 8 is command data, and 15 is a BCH code.

Next, the operation will be described. When receiving the delay command 14 with the BCH code 15 added from the command source, the command receiving circuit 28 transmits the received delay command to the BCH code decoding circuit A30. BCH
The code decoding circuit A30 performs decoding based on the BCH code 15, corrects the error of the delay command 14, and writes the correct delay command 14 to the memory 2. The command management unit 3 periodically stores the current time and the delay command 1 stored in the memory 2.
4, the command management unit 3 reads out the delay command 14 from the memory and, when the command execution time specified by the time information 7 in the delay command is reached, reads the delay command 14 from the BCH code decoding circuit B13. Send to The BCH code decoding circuit B13 performs decoding based on the BCH code 15, corrects command data errors, and transmits correct command data to the command execution unit 5. The command execution unit 5 executes a process based on the contents specified by the command data 8.

Since the command processing apparatus according to the eighth embodiment is configured as described above, even if an error occurs during transmission and a random bit error occurs in the memory by the SEU during storage of the command, Can be corrected at command execution.

Embodiment 9 FIGS. 25 and 26 show a ninth embodiment of the command processing device of the present invention. FIG. 25 is a block diagram showing an embodiment. In FIG. 25, 28 is a command receiving circuit, 31 is a Reed-Solomon code decoding circuit A, 2 is a memory, 3 is a command management unit, and 18 is a Reed-Solomon code decoding. Circuits B and 5 are command execution units, 19 is a delay command, and 8 is command data. FIG. 26 is a format diagram showing the format of the delay command 19. In FIG. 26, 7 is time information indicating the execution time of the delay command, 8 is command data,
20 is a Reed-Solomon code.

Next, the operation will be described. When receiving the delayed command 19 with the Reed-Solomon code 20 added from the command source, the command receiving circuit 28
Converts the received delay command 28 into a Reed-Solom.
The signal is transmitted to the on-code decoding circuit A31. Reed-Sol
The omon code decoding circuit A31 is a Reed-Solomo.
The decoding is performed based on the n code 20, the error of the delay command 19 is corrected, and the correct delay command 19 is written in the memory 2. The command management unit 3 periodically stores the current time and the memory 2
Is compared with the time information 7 in the delay command 19 stored in the delay command 19, and when the command execution time specified by the delay command time information 7 is reached, the command management unit 3 reads the delay command from the memory, and reads the delay command. -Sol
The signal is transmitted to the omon code decoding circuit B18. Reed-S
The solo code decoding circuit B18 is a Reed-Solo
The decoding is performed based on the mon code 20, the error of the command data is corrected, and the correct command data is transmitted to the command execution unit 5. In the command execution unit 5, the command data 8
Executes processing based on the content specified in.

Since the command processing device according to the ninth embodiment is configured as described above, it is possible to reduce the possibility that an error occurs during transmission and a continuous burst error occurs in the memory during storage of a command by the SEU. Can be corrected when the command is executed.

[0042]

The command processing apparatus according to the first invention has an error correction code decoding circuit, and even when an error occurs in the memory during storage of a command by the SEU, the generated error is corrected at the time of executing the command. This has the effect of executing the command without error.

The command processing device of the second invention has an error BCH code decoding circuit, and when a random bit error occurs in the memory by the SEU during storage of the command, the generated error is corrected at the time of executing the command. This has the effect of executing the command without error.

The command processing device according to the third aspect of the present invention has an error correcting Reed-Solomon code decoding circuit. Even when a continuous burst error is generated by the SEU on the memory while the command is being stored, the generated error can be recognized. Correcting when executing a command has the effect of executing the command without error.

A command processing device according to a fourth aspect of the present invention has an error correction code encoding circuit and an error correction code decoding circuit.
When a command is stored in the memory, an error correction code is added, and even when an error occurs in the memory by the SEU during storage of the command, the generated error is corrected at the time of executing the command, thereby executing the command without error. effective.

A command processing device according to a fifth aspect of the present invention has an error correction BCH code encoding circuit and an error correction BCH code decoding circuit, and adds an error correction BCH code when storing a command in a memory. Even when a random bit error is generated by the SEU on the memory during storage, the error can be corrected at the time of executing the command, so that the command can be executed without error.

A command processing device according to a sixth aspect of the present invention has an error correcting Reed-Solomon encoding and decoding circuit and an error correcting Reed-Solomon encoding and decoding circuit, and stores an error correcting Reed-Solomon code in a memory.
Even if a continuous burst error is generated by the SEU on the memory while the command is being stored and the ed-Solomon code is added, the generated error is corrected at the time of executing the command, thereby executing the command without error. .

A command processing apparatus according to a seventh aspect of the present invention has an error correction code decoding circuit. Even when an error occurs during transmission and an error occurs in a memory during storage of a command by an SEU, the command processing apparatus also executes an error correction code decoding circuit. The error that has occurred is corrected when the command is stored in the memory, and the error that has occurred in the memory is corrected when the command is executed, thereby effectively executing the command without error.

The command processing apparatus according to an eighth aspect of the present invention has an error correcting BCH code decoding circuit. When an error occurs during transmission and a random bit error occurs in the memory by the SEU during command storage. Also, there is an effect that a command can be executed without error by correcting an error occurring during transmission when storing the command in the memory and correcting an error occurring in the memory when executing the command.

The command processing apparatus according to the ninth aspect of the present invention has a Reed-Solomon code decoding circuit for error correction, in which an error occurs during transmission, and a continuous burst error occurs in the memory by the SEU during storage of the command. Also in this case, an error generated during transmission is corrected when the command is stored in the memory, and an error generated in the memory is corrected at the time of executing the command, thereby effectively executing the command without error.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of a command processing device according to a first embodiment of the present invention.

FIG. 2 is a format diagram showing a format of a delay command according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram illustrating the principle of the error correction code according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram illustrating a configuration of a command processing device according to a second embodiment of the present invention;

FIG. 5 is a format diagram showing a format of a delay command according to Embodiment 2 of the present invention.

FIG. 6 is a configuration diagram illustrating a configuration of a BCH code encoding circuit according to Embodiment 2 of the present invention;

FIG. 7 is a configuration diagram illustrating a configuration of a BCH code decoding circuit according to Embodiment 2 of the present invention;

FIG. 8 is a configuration diagram showing a configuration of a command processing device according to a third embodiment of the present invention.

FIG. 9 is a format diagram showing a format of a delay command according to Embodiment 3 of the present invention.

FIG. 10 shows Reed-S according to Embodiment 3 of the present invention.
FIG. 3 is a configuration diagram illustrating a configuration of an olon code encoding circuit.

FIG. 11 shows Reed-S according to Embodiment 3 of the present invention.
FIG. 3 is a configuration diagram illustrating a configuration of an olon code decoding circuit.

FIG. 12 is a configuration diagram showing a configuration of a command processing device according to a fourth embodiment of the present invention.

FIG. 13 is a format diagram showing a format of a delay command according to Embodiment 4 of the present invention.

FIG. 14 is a format diagram showing a format of an encoding delay command according to Embodiment 4 of the present invention.

FIG. 15 is a configuration diagram showing a configuration of a command processing device according to a fifth embodiment of the present invention.

FIG. 16 is a format diagram showing a format of a delay command according to Embodiment 5 of the present invention.

FIG. 17 is a format diagram showing a format of an encoding delay command according to Embodiment 5 of the present invention.

FIG. 18 is a configuration diagram showing a configuration of a command processing device according to a sixth embodiment of the present invention.

FIG. 19 is a format diagram showing a format of a delay command according to Embodiment 6 of the present invention.

FIG. 20 is a format diagram showing a format of an encoding delay command according to Embodiment 6 of the present invention.

FIG. 21 is a configuration diagram showing a configuration of a command processing device according to a seventh embodiment of the present invention.

FIG. 22 is a format diagram showing a format of a delay command according to Embodiment 7 of the present invention.

FIG. 23 is a configuration diagram showing a configuration of a command processing device according to an eighth embodiment of the present invention.

FIG. 24 is a format diagram showing a format of a delay command according to the eighth embodiment of the present invention.

FIG. 25 is a configuration diagram showing a configuration of a command processing device according to Embodiment 9 of the present invention.

FIG. 26 is a format diagram showing a format of a delay command according to Embodiment 9 of the present invention.

FIG. 27 is a configuration diagram showing the configuration of a command processing device according to this conventional example.

FIG. 28 is a format diagram showing a format of a delay command according to the conventional example.

[Explanation of symbols]

1 command receiving circuit, 2 memory, 3 command management unit, 4 error correction code decoding circuit, 5 command execution unit,
6 delay command, 7 time information, 8 command data, 9 error correction code, 10 error correction code coding circuit, 13 BCH code decoding circuit, 14 delay command,
15 BCH code for error correction, 16 switch, 17
Switch, 18 Reed-Solomon codec, 19 delay command, 20 error correction Reed-
Solomon code, 21 switch, 22 switch, 23 command receiving circuit, 24 error correction coding coding circuit, 25 delay command, 26 BCH coding coding circuit, 27 Reed-Solomon coding coding circuit, 28 command receiving circuit, 29 error correction Code decoding circuit, 30 BCH code decoding circuit, 31 Reed-S
olon code decoding circuit, 32 delay command.

Claims (9)

[Claims] 1. A command receiving circuit for receiving a delay command to which an error correction code and a command execution time are added from a command source, a memory for storing the received delay command, and reading a delay command from the memory at a specified time. , A command management unit that outputs to a specified destination,
And a decoding circuit for receiving the delay command output from the command management unit, decoding the command based on the error correction code of the delay command, and outputting command data in which the error of the command data is corrected. Command processing unit. 2. A BCH as an error correction code of a decoding circuit.
The command processing device according to claim 1, wherein a code is used. 3. An error correcting code for a decoding circuit,
using d-Solomon code,
The command processing device according to claim 1. 4. A command receiving circuit for receiving a delayed command added with a command execution time from a command source,
An encoding circuit that encodes the received delay command and outputs an encoded delay command to which an error correction code is added, a memory that stores the encoded delay command, and an encoded delay command from the memory at a specified time. A command management unit that reads out a command and outputs the command to a designated destination, performs decoding based on the error correction code of the command read from the memory, executes error correction of command data, and outputs a command in which an error has been corrected A command processing device comprising: a circuit; 5. An error correcting code of an encoding circuit, wherein BC
The command processing device according to claim 4, wherein an H code is used. 6. An error correction code of an encoding circuit,
The command processing device according to claim 4, wherein an ed-Solomon code is used. 7. A command receiving circuit for receiving a delay command to which an error correction code and a command execution time are added from a command source, and a first circuit for decoding based on the error correction code of the delay command and correcting an error of the delay command. A decoding circuit, a memory for storing the delayed command corrected by the decoding circuit, a command management unit for reading a command from the memory at a specified time and outputting the command to a specified destination, and a command management unit for reading the command read from the memory. A command processing device comprising: a second decoding circuit that performs decoding based on an error correction code, executes error correction of command data, and outputs a command in which an error is corrected. 8. The command processing device according to claim 7, wherein a BCH code is used as an error correction code for the first and second decoding circuits. 9. The command processing device according to claim 7, wherein a Reed-Solomon code is used as an error correction code for the first and second decoding circuits.