JPH10144890A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance manufacturing yield by providing a striped element isolating insulation film on a semiconductor substrate and providing a groove exposing the source region of a transistor and extending in the direction crossing the element isolating insulation film on an interlayer insulating film on the semiconductor substrate to fill the groove with a metal wiring. SOLUTION: A striped pattern of SiO2 film exetnding in the column direction is formed on the surface of P-type Si substrate 21 to specify the element isolating region and a film 23 is formed as a gate oxide film for a tunnel on the surface of an element active region between the SiO2 films. A groove 32 exposing the source region 28s, and extending in the column direction riding over the SiO2 film and a contact hole 33 exposing the drain region 28d are formed on the BPSG film 32 by the etching process. Tungsten 34 is deposited and entire surface is etched back, leaving tungsten 34 only in the groove 32 and the contact hole 33. Thereby, manufacturing yield can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device in which a control gate is stacked on a floating gate via a capacitive coupling insulating film.

[0002]

2. Description of the Related Art FIG. 4 shows a flash EEPROM as a conventional example of the present invention. The one to make conventional example, defines the device isolation region to form island-shaped SiO ₂ film 12 arranged in a matrix on the surface of the Si substrate 11, the element active regions between the SiO ₂ film 12 A SiO ₂ film 13 as a gate oxide film for tunneling is formed on the surface of the substrate.

Thereafter, a polycrystalline Si film 14 is deposited on the entire surface of the SiO ₂ films 12 and 13, and the polycrystalline Si film 14 is processed into a stripe pattern extending in the column direction and covering the element active region. Then, an ONO film 15 as a capacitive coupling insulating film is formed on the entire surface, and the polycrystalline Si film 1 is formed on the entire surface of the ONO film 15.
6 is deposited.

Thereafter, the polycrystalline Si film 16 and the ONO film 1 are formed in a stripe pattern extending in the row direction over the SiO ₂ film 12.
5 and the polycrystalline Si film 14 are continuously processed to obtain a polycrystalline S
A floating gate and a control gate are formed by the i films 14 and 16, respectively. Then, a source region 17s and a drain region 17d, which are N ⁺ -type diffusion layers, are formed in the Si substrate 11 by ion implantation of impurities using the polycrystalline Si films 14, 16 and the SiO ₂ film 12 as a mask. A transistor 18 forming a cell is formed.

Thereafter, although not shown, an interlayer insulating film is deposited, a contact hole reaching the drain region 17d is opened in the interlayer insulating film, and a bit line connected to the drain region 17d through the contact hole. To form Then, a surface protective film and the like are further formed to complete the flash EEPROM.

[0006]

However, in the conventional example shown in FIG. 4, the diffusion layer serving as the source region 17s is a common source line, and the diffusion layer has a high resistance. High-speed read operation has been difficult. If a shunt is provided in the source region 17s by metal wiring, high-speed operation is possible. However, a dedicated region for providing a contact hole for connecting the source region 17s and the shunt is required.
Miniaturization becomes difficult. That is, in the conventional example shown in FIG. 4, it is difficult to achieve both high-speed operation and miniaturization.

Further, in the conventional example shown in FIG. 4, since the SiO ₂ film 12 as the element isolation insulating film has an island shape,
When forming the floating gate and the control gate, the S
In the device active region between the iO ₂ films 12, ONO
S as a gate oxide film during over-etching of the film 15
The SiO ₂ film 13 is also etched at the same time, and the polycrystalline Si film 1
At the time of over-etching of 4, the Si substrate 11 is simultaneously etched.

As a result, as shown in FIGS. 4A and 4C, S
Since the concave portion 19 is formed in the i-substrate 11, even if the source region 17s is subsequently formed by ion implantation of impurities, FIG.
As shown in (c), the source region 17
The width of s becomes thin. Accordingly, in the conventional example shown in FIG. 4, the resistance of the source region 17s is also high, which makes it difficult to operate at high speed.

FIG. 4A shows an island-shaped SiO ₂ film 1.
Although 2 is shown as a rectangle, the corners of the SiO ₂ film 12 are actually rounded as shown in FIG. 5B due to the proximity effect and the like in the lithography process. If SiO ₂
If the film 12 is rectangular, the channel width W of the transistor 18 does not change even if the polycrystalline Si films 14 and 16 are displaced in the channel length direction, as is clear from FIG.

However, since the corners of the SiO ₂ film 12 are actually round, as is apparent from FIG.
When the films 14 and 16 are displaced in the channel length direction, the channel width W of the transistor 18 fluctuates, and the transistor 1
8 also varies. Therefore, in the conventional example shown in FIG. 4, the manufacturing yield was low.

[0011]

According to the present invention, there is provided a nonvolatile semiconductor memory device in which a control gate of a transistor forming a memory cell is stacked on a floating gate via a capacitive coupling insulating film. In the storage device, a stripe-shaped element isolation insulating film is provided on a surface of a semiconductor substrate, and a groove extending in a direction intersecting the element isolation insulating film while exposing a source region of the transistor is formed on the semiconductor substrate. The groove is filled with a metal wiring.

In the nonvolatile semiconductor memory device according to the present invention, a contact hole exposing a drain region of the transistor is provided in the interlayer insulating film, and the contact hole is filled with a metal wiring of the same layer as the metal wiring. Preferably.

In the nonvolatile semiconductor memory device according to the present invention, the metal wiring may be made of a high melting point metal.

In the nonvolatile semiconductor memory device according to the present invention, the stripe-shaped element isolation insulating film is provided on the surface of the semiconductor substrate, but is provided on the interlayer insulating film on the semiconductor substrate to reduce the source region of the transistor. Since the groove that is exposed and extends in the direction intersecting with the element isolation insulating film is filled with the metal wiring, the metal wiring serves as a common source line, and the resistance of the common source line is low. Therefore, a shunt for the common source line is unnecessary, and a dedicated area for providing a shunt contact hole is unnecessary.

In addition, since the element isolation insulating film provided on the surface of the semiconductor substrate is striped, no rounded corner exists in the element isolation insulating film, and the control gate and the floating gate are formed in the channel length direction. Even if the position shifts, the channel width of the transistor does not fluctuate, and variation in characteristics of the transistor is small.

Further, if the contact hole exposing the drain region of the transistor is filled with a metal wiring of the same layer as the metal wiring as the common source line, the trench and the contact hole can be formed simultaneously and the common source line can be formed. Since the metal wiring as the line and the metal wiring filling the contact hole can be formed at the same time, the contact hole for the bit line can be made shallow without increasing the number of manufacturing steps.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to a flash EEPROM will be described below with reference to FIGS. Flash EEPROM of this embodiment
As shown in FIGS. 1 and 2 (a), stripes extending in the column direction and having a thickness of 4 are formed on the surface of a P-type Si substrate 21.
Defining an isolation region to form the SiO ₂ film 22 of about nm, a thickness on the surface of the element active regions between the SiO ₂ film 22 for tunnel SiO ₂ film 23 of about 5.0~10nm It is formed as a gate oxide film.

Thereafter, a polycrystalline Si film 24 is deposited on the entire surface of the SiO ₂ films 22 and 23 by the CVD method, and the polycrystalline Si film 24 is processed into a stripe pattern extending in the column direction so as to cover the element active region. . And ON as a capacitive coupling insulating film
An O film 25 is formed on the entire surface, and a polycrystalline Si film 26 is deposited on the entire surface of the ONO film 25 by a CVD method.

Thereafter, the polycrystalline Si film 26 and the ONO film 2 are formed in a striped pattern extending in the row direction across the SiO ₂ film 22.
5 and the polycrystalline Si film 24 are continuously processed to obtain polycrystalline S
A floating gate and a control gate are formed by the i films 24 and 26, respectively. Then, ion implantation of impurities using the polycrystalline Si films 24 and 26 and the SiO ₂ film 22 as a mask, formation of a sidewall protective film composed of the SiO ₂ film 27 and the like, and polycrystalline Si film 2
4, 26 and the ion implantation of impurities using the SiO ₂ films 22 and 27 as a mask are sequentially performed.

As a result, the source region 28s and the drain region 28d, which are the diffusion layers of the LDD structure, are formed in the Si substrate 21, and the transistor 29 forming the memory cell is formed.
Is formed. After that, BPS with a thickness of about 600 nm
The G film 31 is deposited by the CVD method, and the surface of the BPSG film 31 is flattened by reflow or etch back.

Next, as shown in FIGS. 1 and 2 (b), a groove 32 extending in the row direction across the SiO ₂ film 22 by exposing the source region 28s and a contact hole 33 exposing the drain region 28d are formed by BPSG. The film 31 is formed simultaneously by etching. After that, as shown in FIG. 2C, tungsten 34 or the like is deposited by the CVD method, and the whole surface of the tungsten 34 is etched back, and as shown in FIGS.
Tungsten 34 only in groove 32 and contact hole 33
Leave.

Next, as shown in FIG. 3A, an interlayer insulating film 35 is formed, and tungsten 34 in contact hole 33 is formed.
Is formed by etching the interlayer insulating film 35. Then, as shown in FIGS. 1 and 3 (b), the contact hole 36 is filled with tungsten 37 or the like.
A bit line, an electrode pad, and the like are formed by the l film 38 and the like.

Next, as shown in FIG. 3C, a surface protection film 39 is formed, and an opening (not shown) for an electrode pad is formed in the surface protection film 39.
Complete the ROM. In the above embodiment, the groove 3
2 and the contact hole 33 are filled with only a single layer of tungsten 34, but a refractory metal other than tungsten may be used. By increasing the number of interlayer insulating films, a plurality of layers of metal can be used instead of tungsten 34. Can also be used.

In the above embodiment, the flash EEP
This is an application in which the present invention is applied to a ROM.
The invention of the present application can be applied to a nonvolatile semiconductor memory device other than a flash EEPROM as long as the control gate is stacked on the floating gate via a capacitive coupling insulating film, such as M.

[0025]

In the nonvolatile semiconductor memory device according to the present invention, the resistance of the common source line is low, a shunt to the common source line is unnecessary, and a dedicated area for providing a shunt contact hole is unnecessary. Since the operation is performed at high speed and miniaturization is possible, and the characteristics of the transistor are less varied, the production yield is high.

Further, if the contact hole exposing the drain region of the transistor is filled with a metal wiring of the same layer as the metal wiring as the common source line, the contact hole for the bit line can be made shallow without increasing the number of manufacturing steps. As a result, the step coverage of the bit line is excellent, and the production yield is further increased.

[Brief description of the drawings]

FIG. 1 is a plan view of an embodiment of the present invention.

FIG. 2 is a side sectional view at a position along a line DD of FIG. 1 sequentially showing a first half of a manufacturing process of the embodiment;

FIG. 3 is a side cross-sectional view at a position along a line DD in FIG. 1, which sequentially illustrates manufacturing steps in the latter half of the embodiment.

4A and 4B show a conventional example of the invention of the present application, wherein FIG. 4A is a plan view, and FIGS. 4B, 4C and 4D are BB of FIG.
It is a sectional side view in the position along a line, CC line, and DD line.

FIG. 5 is a plan view for explaining a problem in one conventional example.

[Explanation of symbols]

Reference Signs List 21 Si substrate (semiconductor substrate) 22 SiO ₂ film (element isolation insulating film) 24 Polycrystalline Si film (floating gate) 25 ONO film (capacitive coupling insulating film) 26 Polycrystalline Si film (control gate) 28 d Drain region 28 s Source region 29 Transistor 31 BPSG film (interlayer insulating film) 32 Groove 33 Contact hole 34 Tungsten (metal wiring)

Claims (3)

[Claims] In a nonvolatile semiconductor memory device in which a control gate of a transistor forming a memory cell is stacked on a floating gate via a capacitive coupling insulating film, a striped element isolation insulating film is formed on a semiconductor substrate. A groove is provided on the surface and extends in a direction intersecting the element isolation insulating film while exposing the source region of the transistor, and is provided in the interlayer insulating film on the semiconductor substrate, and the groove is filled with a metal wiring. A nonvolatile semiconductor memory device characterized in that: 2. The method according to claim 1, wherein a contact hole exposing a drain region of the transistor is provided in the interlayer insulating film, and the contact hole is filled with a metal wiring in the same layer as the metal wiring. Item 3. The nonvolatile semiconductor memory device according to Item 1. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said metal wiring is made of a high melting point metal.