JPH10144860A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid short-circuiting between a bus bar and a conductor wire arranged over the bus bar in a semiconductor device provided with the bus bar. SOLUTION: A lead 3 for a signal line is provided having its inner lead arranged along the row of an electrode pads on an integrated circuit chip 2, and is fixed on the chip 2 through an adhesive tape 2. A bus bar 4 has one or a plurality of arms. The arm extends toward the adhesive tape and supports the bus bar 4 between the row of the electrode pads 2a and the row of the inner leads by being fixed by the adhesive tape. A space is provided between the bus bar 4 and the major plane of the chip, and the height of the bus bar 4 is offset to the side of the chip major plane rather than the height of the inner lead by using the space. Each inner lead is electrically connected with the electrode pad 20 with a conductor wire 5 over the offset bus bar 4. As a result, a sufficient clearance between the bus bar 4 and the conductor wire 5 is ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a LOC (Lead On Chip) structure having a bus bar and a method of manufacturing the same, and is particularly suitable for a semiconductor device having a center bond LOC structure.

[0002]

2. Description of the Related Art One of the packaging techniques for semiconductor integrated circuit chips is called LOC. In the LOC, an inner lead of a lead frame is located on a surface (hereinafter, referred to as a main surface) on which a circuit element and an electrode pad of an integrated circuit chip are formed, and the inner lead and the electrode pad of the integrated circuit chip are connected by wires. Bonded. The LOC structure package is an effective technique for reducing the size of the semiconductor device by reducing the ratio of the width of the package to the width of the integrated circuit chip.

Some LOC-structured packages have power supply and ground leads called bus bars. FIG. 7 shows an example of a lead layout in a semiconductor device having an LOC structure with a bus bar. FIG. 7 is a plan view showing the leads arranged on the main surface of the integrated circuit chip. An electrode pad 20a electrically connected to a circuit element in the chip is provided at the center of the main surface of the integrated circuit chip 20.
Are arranged substantially in a line. Such a structure is particularly called a center bond LOC. The leads 21 for each signal line extend from both side surfaces of the chip 20 toward the central electrode pad 20a. Lead 21 for signal line
The area on the chip surface is called an inner lead. The bus bar 22 is a lead for supplying a power supply potential, and the bus bar 23 is a lead for supplying a ground potential. Bus bar 2
2 and 23 are arranged along both sides of the row of the electrode pads 20a, and are electrically connected to the plurality of electrode pads of the electrode pads 20a prepared for power supply by the conductor wires 24 at a plurality of locations of the bus bars 22 and 23. Connected to. The tip of the inner lead of the signal line lead 21 is bonded to each electrode pad 20a by a conductor wire disposed over the bus bar 22 or 23.

An object of arranging a bus bar is to apply a power supply voltage and a ground voltage to a plurality of points on an integrated circuit in a chip to suppress impedance in the circuit. That is, the low-resistance bus bar disposed outside the chip works more effectively in lowering the impedance than the power supply wiring routed in the circuit in the chip. Both ends of the bus bars 22 and 23 extend outward from the side surface of the chip similarly to the leads 21 for the signal lines, and are bent further downward to be able to contact the lands of the external substrate. The connection side of such a bus bar to the external board is called an outer lead, as in the case of the signal line lead. The signal line leads 21 and the bus bars 22 and 23 are provided in the form of a lead frame, and are formed by cutting unnecessary portions after being adhered to the main surface of the integrated circuit chip.

[0005]

However, in the semiconductor device having the LOC structure with a bus bar, the conductor wire for connecting the signal line lead and the electrode pad includes:
Must be placed across the busbar. Therefore,
There is a possibility that the conductor wire may come into contact with the bus bar during another process up to the resin sealing or during the resin sealing, causing a problem of causing a short circuit. With the recent demand for thinner semiconductor packages, the problem of contact between conductor wires has become more serious. In order to avoid such a problem, it is necessary to interpose another member between the bus bar and the conductor wire, or to secure a sufficient clearance between the bus bar and the conductor wire.

[0006] Conventionally, as a method for realizing the former, there is a method in which an insulating material such as polyimide is applied to the surface of a bus bar so that the bus bar and the conductor wire do not interfere with each other. However, the step of applying such an insulating material to the bus bar increases the manufacturing cost of the lead frame, and in turn, the cost of the semiconductor device. In order to realize the latter, a part or the whole of the bus bar is processed to be thinner than other parts of the lead frame by etching or pressing so that a clearance between the bus bar and the conductor wire can be secured. There is. However, in order to stably process the bus bar to a desired thickness by etching, it is necessary to add some steps for etching the lead frame, which eventually increases the manufacturing cost. Further, in processing by pressing, it is difficult to thin a long bus bar without causing undulation, and there is a possibility that the production yield of a lead frame may be reduced. Therefore, it has been desired to establish a technique for manufacturing a lead frame at a low cost and with a high yield and avoiding a short circuit between the bus bar and the conductor wire.

An object of the present invention is to provide a semiconductor device capable of avoiding a short circuit between a bus bar and a conductor wire without applying an insulating material on the bus bar, and a method of manufacturing the same.

Another object of the present invention is to realize a semiconductor device which achieves the above object without increasing the manufacturing cost.

[0009]

The present invention is suitable for application to a semiconductor device having a LOC structure in which inner leads of a lead frame are arranged on a main surface of a semiconductor integrated circuit chip. The signal line leads are arranged such that the inner leads are arranged along the rows of the electrode pads on the integrated circuit chip, and are fixed on the chip via an adhesive layer, preferably an adhesive tape. The bus bar has one or more arms.
The arm extends toward the adhesive layer and is fixed to the adhesive layer to support a bus bar between the row of the electrode pads and the row of the inner leads. There is a gap between the bus bar and the chip main surface, and the height of the bus bar is set lower on the chip main surface side than the height of the inner lead by using the gap. At the time of molding the lead frame, it is preferable to realize such an arrangement of the bus bar by pressing down the position of the bus bar with respect to the signal line lead. The inner leads and the electrode pads are electrically connected to each other by conductor wires over the bus bar which is set low. As a result, a sufficient clearance is secured between the bus bar and the conductor wire. By sealing the inner lead, the bus bar, and the conductor wire with the resin, the above clearance is permanently maintained.

In the present invention, it is preferable to provide a plurality of arms of the bus bar along the longitudinal direction of the bus bar and to support the bus bar at a plurality of positions in order to obtain the stability of the bus bar on the chip before resin sealing. In this case, some of the arms of the bus bar may be extended outside the semiconductor integrated circuit chip to supply power to the bus bar.

The scope of application of the present invention is not limited to a semiconductor device having a center-bond type LOC structure, but is suitable for application to such a semiconductor device. In the center bond type LOC structure, a row of electrode pads is provided at the center of a semiconductor integrated circuit chip, and a row of inner leads of signal line leads is extended on both sides thereof. The two bus bars are located between the rows of the inner leads and the rows of the electrode pads, and are fixed by their arms to an adhesive layer that fixes the inner leads on each side. Each bus bar is installed at a position lower than the inner lead on the chip main surface side, and a sufficient clearance with a conductor wire arranged beyond the bus bar is secured.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. 1 to 3 show a semiconductor device to which the present invention is applied. This semiconductor device is a memory device (DRAM) having a center bond LOC structure. In FIG. 1, a memory device 1 includes signal line leads 3 and bus bars 4 provided by a lead frame on a main surface of an integrated circuit chip 2. The integrated circuit chip 2 has a large number of electrode pads 2a in a line in the center of the main surface. Many signal wire leads 3
Are arranged on both sides of the row of the electrode pads 2a, and each extends outward from the center of the chip. The end of each signal line lead 3 on the electrode pad 2a side is called an inner lead, and is electrically connected to any one of the electrode pads 2a via a conductor wire 5 by wire bonding. The opposite end of each signal line lead 3 is called an outer lead, extends outward from the side surface of the package, and is bent to be mounted on an external substrate. Each signal line lead 3 is fixed on the main surface of the integrated circuit chip 2 by a polyimide adhesive tape 6 extending along the lower surface of the row of the inner leads.

The memory device 1 includes two bus bars 4 provided by a lead frame together with the signal line leads 3. One of the two bus bars is for supplying a power supply potential to the integrated circuit chip 2, and the other is for supplying a ground potential. Each bus bar 4
Are arranged to extend between the row of the electrode pads 2a and the row of the inner leads of the signal line leads 3. Each bus bar 4
Some legs 4a extend toward the outside of the chip, and similarly extend outward from the side surface of the chip along the signal line leads 3. The tip of the leg 4a is bent in the same manner as the outer lead of the signal line lead 3, and is connected to the power supply land on the external board.

Each of the bus bars 4 has a plurality of arms 4b arranged at appropriate intervals along the longitudinal direction. Arm 4b
Extend from the side surface of the bus bar 4 to the outside, that is, to the row side of the inner leads of the signal line leads 3, and are pasted on the adhesive tape 6 alongside the inner leads. The legs 4a of the bus bar are also pasted on the adhesive tape 6. That is, each bus bar 4 includes a plurality of arms 4b and legs 4a.
On the integrated circuit chip 2.

Further, as is particularly apparent in FIG. 3, the bus bar 4 has its surface located closer to the chip main surface than the surface formed by the rows of the inner leads. In the manufacturing process of the lead frame, the arrangement of the bus bar 4 is realized by pushing down the location of the bus bar 4 by one step from the surface formed by the lead frame by a pushing and cutting method described later. When the lead frame is mounted on the main surface of the integrated circuit chip 2 with the adhesive tape 6,
The lead frame is suspended above the chip main surface by the thickness of the adhesive tape 6. Utilizing the lift amount of the lead frame ("H" in FIG. 3), the bus bar 4 offset from the lead surface can be arranged.
The conductor wire 5 connecting between the electrode pad 2a and the inner lead of the signal line lead 3 is disposed beyond the offset bus bar 4. The conductor wires 5 extending from some of the electrode pads 2a are bonded at the positions of the arms 4b of the bus bar 4. In one embodiment, the adhesive tape 6 has a thickness of 80 μm and a thickness of 1 μm.
The offset amount F of the bus bar 4 in the 25 μm lead frame is 40 ^{+20, −10} μm.

In the manufacturing process of the memory device 1, a lead frame as shown in FIG. 4 is formed. The lead frame includes a row of signal line leads 3 and a pair of bus bars 4 formed by punching or etching with a die. In the next step of forming the lead frame, an offset is given to the bus bar 4. FIG. 5 conceptually shows a process of offsetting a bus bar by using a press-cutting method using a die. As shown in FIG. 2A, the bus bar 4 is held by the dice 1 at the position of the arm 4b.
0, and the offset is formed by lowering the punch 11 on the bus bar 4 as shown in FIG. FIG. 6 conceptually shows a state before and after the offset molding of the bus bar.

Next, an adhesive tape 6 is attached to the back surface of the lead frame. As shown in FIG.
Are provided at locations corresponding to the rows of the inner leads and at locations corresponding to the four corners of the chip. A lead frame is attached to the main surface of the integrated circuit chip manufactured in another process via the adhesive tape. FIG. 4 shows the outline of the integrated circuit chip 2, and the outer leads of the signal line leads 3 in the lead frame extend to both sides beyond the outline of the chip. Next, an electrode pad 2a is applied to the inner lead of each signal line lead 3 and each bus bar 4.
Wire bonding is performed. The wire bonding to the inner leads is performed beyond the bus bar 4. Wire bonding to the bus bar 4 is performed at the position of the arm 4b. Thereafter, the integrated circuit chip 2 is sealed together with the lead frame by transfer molding. After deburring the solidified resin, the outer leads of the lead frame are separated from the frame and bent so that they can be mounted on an external substrate. Through the above steps, the memory device 1 is assembled.

An example in which the present invention is applied to a memory device having a center bond LOC structure has been described. However, it is clear that the present invention is not limited to the structure shown in the above embodiment, but can be widely applied to a semiconductor device having a structure in which an inner lead and an electrode pad are electrically connected by a conductor wire over a bus bar. For example, in the structure shown in the above embodiment, the electrode pads are arranged in one line at the center of the chip. However, the electrode pads may be arranged in two or three or more lines in parallel. Further, the position of the electrode pad is not limited to the center bond LOC located at the center of the main surface of the chip, but may be shifted to either side from the center of the chip. Although it is not symmetrical, the bus bars may be located on both sides of the row of electrode pads, and the inner leads may be located outside the bus bars. Further, if bus bars are not required on both sides of the electrode pad, one side of the row of the electrode pad may be arranged.
One or two or more busbars may be arranged, and the inner leads may be arranged further outside.

[0019]

In the semiconductor device according to the present invention, since the bus bar is disposed on the chip surface side with respect to the inner lead surface, a sufficient clearance is provided between the bus bar and the conductor wire disposed beyond the bus bar. Is secured. Thereby, the possibility that the bus bar and the conductor wire are short-circuited by the pressure at the time of resin sealing is extremely reduced.

Further, in order to avoid a short circuit between the bus bar and the conductor wire, a semiconductor device can be manufactured at low cost without using an expensive insulating material or reducing the yield. That is, giving an offset to the bus bar in the process of forming the lead frame can be easily realized without requiring a special manufacturing device,
Does not affect the productivity of semiconductor devices.

[Brief description of the drawings]

FIG. 1 is a perspective view of an embodiment of a semiconductor device according to the present invention, showing a state of a lead frame on a chip except for a package.

FIG. 2 is an enlarged view showing a part of FIG. 1;

FIG. 3 is a cross-sectional view of the semiconductor device showing an offset state of a bus bar.

FIG. 4 is a plan view showing an example of a lead frame used in the semiconductor device according to the present invention.

FIG. 5 is a diagram showing a bus bar processing method.

FIG. 6 is a perspective view showing a state before and after processing of a bus bar.

FIG. 7 is a plan view showing one arrangement of leads in a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Integrated circuit chip 2a Electrode pad 3 Signal line lead 4 Bus bar 5 Conductor wire 6 Adhesive tape H Adhesive tape thickness F Offset amount

Claims (7)

[Claims] 1. A semiconductor integrated circuit chip having a row of electrode pads on a circuit forming surface side, and a row of inner leads arranged along the row of electrode pads, wherein the circuit forming surface is provided via an adhesive layer. A bus bar having a signal line lead fixed thereon and an arm fixed to the adhesive layer, the arm being supported between the row of the electrode pads and the row of the inner leads by the arm, A surface whose surface is located closer to the semiconductor integrated circuit chip side than a surface formed by the rows of the inner leads, a conductor wire that electrically connects the inner leads and the electrode pads beyond the bus bar, A semiconductor device including at least a resin for sealing the inner lead, the bus bar, and the conductor wire. 2. The semiconductor device according to claim 1, wherein said bus bar is formed by being pushed down toward said semiconductor integrated circuit chip at the position of its arm. 3. The semiconductor device according to claim 1, wherein said adhesive layer is an adhesive tape provided along a row of said inner leads. 4. The semiconductor device according to claim 1, wherein a plurality of arms of said bus bar are provided along a longitudinal direction of said bus bar. 5. The method of claim 5, wherein some of the arms of the busbar are
5. The semiconductor device according to claim 4, wherein the semiconductor device extends outside the semiconductor integrated circuit chip to supply power to a bus bar. 6. A semiconductor integrated circuit chip having a row of electrode pads on the circuit forming surface side, and a pair of inner leads arranged on both sides of the electrode pad along the row of electrode pads. A signal line lead fixed on the circuit forming surface, and an arm fixed to the adhesive layer. The arm is supported by the arm between the row of electrode pads and the row of each inner lead. A pair of bus bars, the surfaces of which are located closer to the semiconductor integrated circuit chip than the surface formed by the rows of the inner leads, and the inner leads and the electrode pads which extend beyond the bus bars. A semiconductor device comprising: a conductive wire for electrically connecting the conductive wires; and at least a resin for sealing the inner lead, the bus bar, and the conductive wire. 7. A step of forming a semiconductor integrated circuit chip having a row of electrode pads on a circuit forming surface side; and a signal line lead having a row of inner leads arranged along the row of electrode pads. Forming a bus bar disposed in front of the bus bar along the inner lead row, and a lead frame including the bus bar arm extending from the bus bar and disposed in the inner lead row; and At the position, pushing down the bus bar to the mounting surface side of the lead frame for the semiconductor integrated circuit chip; adhering an adhesive tape to the mounting surface side of the lead frame along the row of the inner leads; Fixing a lead frame on the semiconductor integrated circuit chip with the adhesive tape; and A step of connecting the head and the respective inner leads electrically by a conductor wire, a method of manufacturing a semiconductor device including a step of sealing at least the inner leads, bus bars and the conductive wires resin.