JPH10144806A - Incorrect measurement preventive device for floating gate potential - Google Patents
Incorrect measurement preventive device for floating gate potentialInfo
- Publication number
- JPH10144806A JPH10144806A JP29468796A JP29468796A JPH10144806A JP H10144806 A JPH10144806 A JP H10144806A JP 29468796 A JP29468796 A JP 29468796A JP 29468796 A JP29468796 A JP 29468796A JP H10144806 A JPH10144806 A JP H10144806A
- Authority
- JP
- Japan
- Prior art keywords
- floating gate
- floating
- thin film
- electrode
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005259 measurement Methods 0.000 title claims description 9
- 230000003449 preventive effect Effects 0.000 title 1
- 239000010409 thin film Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 abstract description 20
- 239000000758 substrate Substances 0.000 abstract description 10
- 230000000717 retained effect Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、浮遊ゲートを利用
した不揮発半導体メモリにおいて、秘密情報として保持
された浮遊ゲートの電位情報を外部から不正に読み取る
ことを防止する浮遊ゲート電位不正測定防止装置に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for preventing unauthorized measurement of floating gate potential in a nonvolatile semiconductor memory using a floating gate, which prevents unauthorized reading of potential information of the floating gate held as secret information from the outside. Things.
【０００２】[0002]
【従来の技術】従来の浮遊ゲートを利用した不揮発半導
体メモリとしてはＥＥＰＲＯＭやフラッシュメモリがあ
る。これらのメモリでは浮遊ゲートに電荷を保持し、浮
遊ゲートの電位の高い場合と、低い場合との２状態を使
って２値情報を記憶していた。このような不揮発半導体
メモリに秘密情報を記憶させた場合、電子回路で不正に
読み出せないようにしていたとしても、浮遊ゲートの電
位に外部から電子線を照射して反射電子を測定したり、
浮遊ゲートの周囲の電界を測定することで、浮遊ゲート
の２値情報を読み取ることができるので、記憶情報を秘
密にすることができないという欠点があった。2. Description of the Related Art As a conventional nonvolatile semiconductor memory using a floating gate, there is an EEPROM or a flash memory. In these memories, charges are held in the floating gate, and binary information is stored using two states, that is, a case where the potential of the floating gate is high and a case where the potential is low. When secret information is stored in such a non-volatile semiconductor memory, even if it is prevented from being read illegally by an electronic circuit, the potential of the floating gate is irradiated with an electron beam from the outside to measure reflected electrons,
Since the binary information of the floating gate can be read by measuring the electric field around the floating gate, there is a disadvantage that the stored information cannot be kept secret.
【０００３】[0003]
【発明が解決しようとする課題】本発明の目的は、浮遊
ゲートに保持された２値情報を外部から不正に読み取る
ことができるという従来の欠点を解決した秘密保持性に
優れた不揮発半導体メモリの提供を可能とした浮遊ゲー
ト電位不正測定防止装置を得ることにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a non-volatile semiconductor memory having excellent confidentiality which solves the conventional disadvantage that binary information held in a floating gate can be illegally read from the outside. An object of the present invention is to provide an apparatus for preventing illegal measurement of floating gate potential which can be provided.
【０００４】[0004]
【課題を解決するための手段】本発明は、浮遊ゲートを
有する不揮発半導体メモリにおける浮遊ゲート電位不正
測定防止装置であって、前記浮遊ゲート上部を一定電位
が印加される導電性薄膜で覆い、この導電性薄膜と前記
浮遊ゲート間の双方に対して容量結合する浮遊電極を設
け、かつ、この浮遊電極と導電性薄膜間の容量を浮遊電
極と浮遊ゲート間の容量より大として前記導電性薄膜が
除去されたとき浮遊電極と浮遊ゲート間の容量が破壊さ
れるようにしたものである。SUMMARY OF THE INVENTION The present invention relates to a device for preventing unauthorized measurement of floating gate potential in a nonvolatile semiconductor memory having a floating gate, wherein the upper portion of the floating gate is covered with a conductive thin film to which a constant potential is applied. A floating electrode that is capacitively coupled to both the conductive thin film and the floating gate is provided, and the capacitance between the floating electrode and the conductive thin film is set to be larger than the capacitance between the floating electrode and the floating gate. When removed, the capacitance between the floating electrode and the floating gate is destroyed.
【０００５】[0005]
【発明の実施の形態】本発明の浮遊ゲート電位不正測定
防止装置の基本構成の断面略図を図１に示す。この図に
おいて、１は半導体基板で、ＭＯＳトランジスタ部２が
形成されている。ＭＯＳトランジスタ部２は図示しない
ソース，ドレインの他、下記３〜６の各部からなる。す
なわち半導体基板１の上部に浮遊ゲート３を設け、その
上部に制御ゲート４を設ける。従来技術ではこの浮遊ゲ
ート３と制御ゲート４とソース，ドレインとでＭＯＳト
ランジスタ部２が構成されていた。本発明では浮遊ゲー
ト３の上部にさらに、浮遊電極５と金属薄膜６を設け
る。金属薄膜６は半導体基板１に接続して一定電位に保
持する。このようにすると、浮遊ゲート３の電荷による
電界は半導体基板１と金属薄膜６との間に集中し、外部
から浮遊ゲート３の電位を測定することは困難である。
しかし、金属薄膜６を除去すれば、浮遊ゲート３の電位
を測定することが可能になってしまう。そこで、浮遊電
極５と金属薄膜６の間、並びに浮遊電極５と浮遊ゲート
３の間を容量結合し、浮遊電極５に電荷を注入してお
く。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic cross-sectional view of a basic configuration of a floating gate potential incorrect measurement prevention apparatus according to the present invention. In this figure, reference numeral 1 denotes a semiconductor substrate on which a MOS transistor section 2 is formed. The MOS transistor section 2 includes the following sections 3 to 6 in addition to a source and a drain (not shown). That is, the floating gate 3 is provided above the semiconductor substrate 1, and the control gate 4 is provided above the floating gate 3. In the prior art, the MOS transistor section 2 is composed of the floating gate 3, the control gate 4, the source and the drain. In the present invention, a floating electrode 5 and a metal thin film 6 are further provided above the floating gate 3. The metal thin film 6 is connected to the semiconductor substrate 1 and is kept at a constant potential. In this case, the electric field due to the charge of the floating gate 3 is concentrated between the semiconductor substrate 1 and the metal thin film 6, and it is difficult to externally measure the potential of the floating gate 3.
However, if the metal thin film 6 is removed, the potential of the floating gate 3 can be measured. Thus, the floating electrode 5 and the metal thin film 6 and the floating electrode 5 and the floating gate 3 are capacitively coupled, and charges are injected into the floating electrode 5 in advance.
【０００６】ここで、図３の等価回路に示すように、半
導体基板１と浮遊ゲート３間の容量をＣ１、浮遊ゲート
３と制御ゲート４間の容量をＣ２、浮遊ゲート３と浮遊
電極５間の容量をＣ３、浮遊電極５と金属薄膜６間の容
量をＣ４とする。条件として、Ｃ４＞＞Ｃ３としてお
く。すると、もし、金属薄膜６が除去されると、それま
で浮遊電極５と金属薄膜６間の容量Ｃ４に蓄積していた
電荷が、浮遊電極５と浮遊ゲート３との容量Ｃ３に集中
し、浮遊電極５と浮遊ゲート３との電圧が増大して、容
量Ｃ３およびＣ１において静電破壊をおこす。そのた
め、浮遊ゲート３の電位が大きく変化し、それまでの記
憶情報が破壊される。すなわち、浮遊ゲート３の電位を
測定するために、邪魔になっている金属薄膜６を除去す
ると、浮遊電極５に蓄積されていた電荷によって浮遊ゲ
ート３の電荷が大きく変化し、記憶情報が破壊されて読
み取ることができなくなる。なお、図１では、半導体基
板１上の各部１，３〜６間の絶縁膜は省略してある。Here, as shown in the equivalent circuit of FIG. 3, the capacitance between the semiconductor substrate 1 and the floating gate 3 is C1, the capacitance between the floating gate 3 and the control gate 4 is C2, and the capacitance between the floating gate 3 and the floating electrode 5 is Is C3, and the capacitance between the floating electrode 5 and the metal thin film 6 is C4. The condition is C4 >> C3. Then, if the metal thin film 6 is removed, the electric charge that has been accumulated in the capacitance C4 between the floating electrode 5 and the metal thin film 6 is concentrated on the capacitance C3 between the floating electrode 5 and the floating gate 3, and floating. The voltage between the electrode 5 and the floating gate 3 increases, causing electrostatic breakdown in the capacitors C3 and C1. Therefore, the potential of the floating gate 3 greatly changes, and the stored information up to that point is destroyed. That is, if the obstructing metal thin film 6 is removed in order to measure the potential of the floating gate 3, the charge stored in the floating electrode 5 greatly changes the charge of the floating gate 3 and destroys the stored information. And cannot read. In FIG. 1, the insulating film between the components 1 and 3 to 6 on the semiconductor substrate 1 is omitted.
【０００７】[0007]
【実施例】図２は、図１のＭＯＳトランジスタ部２の平
面図に相当するもので、３〜６は図１に示すものと同じ
であり、７はソース、８はドレイン、９はソース電極、
１０はドレイン電極を示す。なお、図２の金属薄膜６は
浮遊電極５より寸法を大きくして見易くしてある。FIG. 2 corresponds to a plan view of the MOS transistor section 2 of FIG. 1. 3 to 6 are the same as those shown in FIG. 1, 7 is a source, 8 is a drain, and 9 is a source electrode. ,
Reference numeral 10 denotes a drain electrode. In addition, the metal thin film 6 in FIG. 2 is larger in size than the floating electrode 5 to make it easier to see.
【０００８】本発明の浮遊ゲート電位不正測定防止装置
の構成ならびに動作を図１および図２の実施例にしたが
って詳細に説明する。半導体基板１の上部に浮遊ゲート
３を設け、その上部に制御ゲート４を設ける。そして、
さらに浮遊ゲート３の上部に、浮遊ゲート３と制御ゲー
ト４を覆い隠すようにして、浮遊電極５と金属薄膜６を
設ける。金属薄膜６は半導体基板１に接続して一定電位
に保持する。そして、浮遊電極５と金属薄膜６の間、並
びに浮遊電極５と浮遊ゲート３の間を容量結合し、浮遊
電極５に電荷を注入しておく。この等価回路ももちろん
図３に示すようになる。また、容量Ｃ１〜Ｃ４も前述し
たとおりである。また、制御電極の制御性をよくするた
めには、Ｃ２＞＞Ｃ３とする。浮遊ゲート３の電位をＶ
ｇ、浮遊電極５の電極をＶｈ、浮遊電極５の電荷量をＱ
ｈとすると、Ｑｈ＝Ｃ３（Ｖｈ−Ｖｇ）＋Ｃ４Ｖｈの関
係がある。The configuration and operation of the apparatus for preventing illegal measurement of floating gate potential according to the present invention will be described in detail with reference to the embodiments of FIGS. A floating gate 3 is provided above a semiconductor substrate 1, and a control gate 4 is provided above the floating gate 3. And
Further, a floating electrode 5 and a metal thin film 6 are provided above the floating gate 3 so as to cover the floating gate 3 and the control gate 4. The metal thin film 6 is connected to the semiconductor substrate 1 and is kept at a constant potential. Then, capacitive coupling is performed between the floating electrode 5 and the metal thin film 6 and between the floating electrode 5 and the floating gate 3, and charges are injected into the floating electrode 5. This equivalent circuit is of course as shown in FIG. The capacitances C1 to C4 are also as described above. In order to improve controllability of the control electrode, C2 >> C3. The potential of the floating gate 3 is set to V
g, the electrode of the floating electrode 5 is Vh, and the charge amount of the floating electrode 5 is Q
If h, there is a relationship of Qh = C3 (Vh-Vg) + C4Vh.
【０００９】図１，図２において、もし、金属薄膜６が
除去されると、それまで浮遊電極５と金属薄膜６間の容
量Ｃ４に蓄積していた電荷が、浮遊電極５と浮遊ゲート
３との容量Ｃ３に集中する。このとき、浮遊電極５の電
荷量Ｑｈは変わらないが、容量Ｃ４は０になり、電位Ｖ
ｈはＶｈ′、電位ＶｈはＶｇ′に変化し、Ｑｈ＝Ｃ３
（Ｖｈ′−Ｖｇ′）の状態になる。したがって、容量Ｃ
３における電位差は（Ｖｈ′−Ｖｇ′）＝（１＋Ｃ４／
Ｃ３）Ｖｈ−Ｖｇとなるので、Ｃ４／Ｃ３＞＞１の関係
より、浮遊電極５と浮遊ゲート３との電圧が増大して、
容量Ｃ３において静電破壊をおこす。また、浮遊ゲート
３への電荷の流入により、Ｖｇが増大し、さらに容量Ｃ
１においても静電破壊を生じる。そのため、浮遊ゲート
３の電位が大きく変化し、それまでの記憶情報が破壊さ
れる。In FIG. 1 and FIG. 2, if the metal thin film 6 is removed, the electric charge that has been accumulated in the capacitor C4 between the floating electrode 5 and the metal thin film 6 until then is removed from the floating electrode 5 and the floating gate 3. Concentrated on the capacity C3 of. At this time, the charge amount Qh of the floating electrode 5 does not change, but the capacitance C4 becomes 0, and the potential Vh
h changes to Vh ', the potential Vh changes to Vg', and Qh = C3
(Vh'-Vg '). Therefore, the capacitance C
3 is (Vh'-Vg ') = (1 + C4 /
C3) Since Vh−Vg, the voltage between the floating electrode 5 and the floating gate 3 increases due to the relationship of C4 / C3 >> 1.
Electrostatic breakdown occurs in the capacitor C3. In addition, Vg increases due to the inflow of charges into the floating gate 3, and the capacitance C
1 also causes electrostatic breakdown. Therefore, the potential of the floating gate 3 greatly changes, and the stored information up to that point is destroyed.
【００１０】なお、上記の実施例では金属薄膜６を用い
たため、これはポリゴンシリコン等でもよく、要は導電
性薄膜であればよい。In the above embodiment, since the metal thin film 6 is used, it may be made of polygonal silicon or the like.
【００１１】[0011]
【発明の効果】以上説明したように、本発明は、浮遊ゲ
ートを有する不揮発半導体メモリにおける浮遊ゲート電
位不正測定防止装置であって、前記浮遊ゲート上部を一
定電位が印加される導電性薄膜で覆い、この導電性薄膜
と前記浮遊ゲート間の双方に対して容量結合する浮遊電
極を設け、かつ、この浮遊電極と導電性薄膜間の容量を
浮遊電極と浮遊ゲート間の容量より大として前記導電性
薄膜が除去されたとき浮遊電極と浮遊ゲート間の容量が
破壊されるようにしたので、浮遊ゲートの電位を不正に
測定するために、邪魔になっている導電性膜膜を除去す
ると、浮遊電極に蓄積されていた電荷によって浮遊電極
と浮遊ゲートの間で静電破壊をおこして浮遊ゲートの電
位を読めなくすることができる。また、このような静電
破壊を回避して不正な読み出しを行うためには技術的に
かなりの手間がかかるので、不正行為を防止する効果が
ある。As described above, the present invention relates to a device for preventing incorrect measurement of a floating gate potential in a nonvolatile semiconductor memory having a floating gate, wherein the upper portion of the floating gate is covered with a conductive thin film to which a constant potential is applied. Providing a floating electrode that is capacitively coupled to both the conductive thin film and the floating gate; and setting the capacitance between the floating electrode and the conductive thin film to be larger than the capacitance between the floating electrode and the floating gate. When the thin film is removed, the capacitance between the floating electrode and the floating gate is destroyed, so if the conductive film that is in the way is removed to measure the potential of the floating gate incorrectly, the floating electrode The electric charge accumulated in the floating gate causes electrostatic breakdown between the floating electrode and the floating gate, making it impossible to read the potential of the floating gate. In addition, in order to avoid such electrostatic damage and perform illegal reading, it takes a considerable technical time to perform illegal reading, so that there is an effect of preventing illegal acts.
【図１】本発明の基本構成を示す断面略図である。FIG. 1 is a schematic sectional view showing a basic configuration of the present invention.
【図２】本発明の一実施例の平面略図である。FIG. 2 is a schematic plan view of an embodiment of the present invention.
【図３】本発明の動作を示す等価回路図である。FIG. 3 is an equivalent circuit diagram showing the operation of the present invention.
１ 半導体基板 ２ ＭＯＳトランジスタ部 ３ 浮遊ゲート ４ 制御ゲート ５ 浮遊電極 ６ 金属薄膜 ７ ソース ８ ドレイン ９ ソース電極 １０ ドレイン電極 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 MOS transistor part 3 Floating gate 4 Control gate 5 Floating electrode 6 Metal thin film 7 Source 8 Drain 9 Source electrode 10 Drain electrode
フロントページの続き (72)発明者 藤田 修 東京都武蔵野市吉祥寺本町一丁目14番５号 エヌティティエレクトロニクステクノロ ジー株式会社内Continuation of the front page (72) Inventor Osamu Fujita 1-14-5 Kichijoji Honmachi, Musashino City, Tokyo Inside NTT Electronics Technology Co., Ltd.
Claims (1)
における浮遊ゲート電位不正測定防止装置であって、前
記浮遊ゲート上部を一定電位が印加される導電性薄膜で
覆い、この導電性薄膜と前記浮遊ゲート間の双方に対し
て容量結合する浮遊電極を設け、かつ、この浮遊電極と
導電性薄膜間の容量を浮遊電極と浮遊ゲート間の容量よ
り大として前記導電性薄膜が除去されたとき浮遊電極と
浮遊ゲート間の容量が破壊されるようにしたことを特徴
とする浮遊ゲート電位不正測定防止装置。1. An apparatus for preventing illegal measurement of a floating gate potential in a nonvolatile semiconductor memory having a floating gate, wherein an upper portion of the floating gate is covered with a conductive thin film to which a constant potential is applied, and a portion between the conductive thin film and the floating gate is provided. And a capacitance between the floating electrode and the conductive thin film is set to be larger than a capacitance between the floating electrode and the floating gate, and the floating electrode and the floating electrode are floated when the conductive thin film is removed. An apparatus for preventing unauthorized measurement of floating gate potential, wherein a capacitance between gates is destroyed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29468796A JP3914976B2 (en) | 1996-11-07 | 1996-11-07 | Floating gate potential fraud measurement prevention device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29468796A JP3914976B2 (en) | 1996-11-07 | 1996-11-07 | Floating gate potential fraud measurement prevention device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10144806A true JPH10144806A (en) | 1998-05-29 |
| JP3914976B2 JP3914976B2 (en) | 2007-05-16 |
Family
ID=17811015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29468796A Expired - Fee Related JP3914976B2 (en) | 1996-11-07 | 1996-11-07 | Floating gate potential fraud measurement prevention device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3914976B2 (en) |
-
1996
- 1996-11-07 JP JP29468796A patent/JP3914976B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3914976B2 (en) | 2007-05-16 |
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