JPH10144725A - Method of mounting integrated circuit - Google Patents
Method of mounting integrated circuitInfo
- Publication number
- JPH10144725A JPH10144725A JP8301487A JP30148796A JPH10144725A JP H10144725 A JPH10144725 A JP H10144725A JP 8301487 A JP8301487 A JP 8301487A JP 30148796 A JP30148796 A JP 30148796A JP H10144725 A JPH10144725 A JP H10144725A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- adhesive
- die
- conductive adhesive
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、集積回路の実装方
法に関し、特に、TCP(Tape Carrier Package)に封止
された集積回路のプリント配線板上への実装方法に適用
して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting an integrated circuit, and more particularly to a technique effective when applied to a method for mounting an integrated circuit sealed in a TCP (Tape Carrier Package) on a printed wiring board. Things.
【0002】[0002]
【従来の技術】従来の集積回路の実装方法としては、例
えば、「エレクトロニクス実装技術(1996.5 Vol12 No.
5)」のP31〜P36に開示されたものがある。2. Description of the Related Art Conventional mounting methods for integrated circuits include, for example, “Electronic mounting technology (1996.5 Vol.
5) ”on pages P31 to P36.
【0003】この実装方法について、図5を用いて説明
する。[0005] This mounting method will be described with reference to FIG.
【0004】図5は、従来のTCPに封止された集積回
路のプリント配線板上への実装方法を説明するために、
集積回路のダイとプリント配線板の接着部分を断面形状
を示したものである。FIG. 5 shows a conventional method of mounting an integrated circuit sealed in TCP on a printed wiring board.
FIG. 3 shows a cross-sectional shape of an adhesive portion between an integrated circuit die and a printed wiring board.
【0005】図5において、1は集積回路のダイ、2は
接着剤、3はダイ接続用パターン、4はスルーホール、
5は放熱片接続用パターン、6は放熱片、7はアウタリ
ードをそれぞれ示す。In FIG. 5, 1 is an integrated circuit die, 2 is an adhesive, 3 is a die connection pattern, 4 is a through hole,
Reference numeral 5 denotes a heat radiation piece connection pattern, 6 denotes a heat radiation piece, and 7 denotes an outer lead.
【0006】図5に示すTCPタイプの集積回路は軽
量、薄形が特徴で、ノート型パソコンに搭載される事が
多く、また、発熱が5〜8Wと大きいため、集積回路の
ダイ1はそのまま露出した形にしてあり、このダイ1を
放熱部材に直接接続して熱伝導を良好ならしめるように
工夫されている。The TCP type integrated circuit shown in FIG. 5 is characterized in that it is lightweight and thin, is often mounted on a notebook computer, and generates a large amount of heat of 5 to 8 W. The die 1 is exposed so that the die 1 is directly connected to a heat radiating member to improve heat conduction.
【0007】集積回路のダイ1は、図5に示すように、
裏面に導電性の接着剤2を付けてプリント配線板上のパ
ターン3に接続することによって実装される。[0007] The die 1 of the integrated circuit, as shown in FIG.
It is mounted by attaching a conductive adhesive 2 to the back surface and connecting to the pattern 3 on the printed wiring board.
【0008】このように実装することにより、集積回路
からの発熱はパターン3に設けられたスルーホール4を
経由してプリント配線板裏面に取り付けられた放熱片6
に伝達され、熱が放出されるようになる。[0008] With this mounting, heat generated from the integrated circuit is radiated from the integrated circuit via the through holes 4 provided in the pattern 3 to the heat radiation pieces 6 attached to the back surface of the printed wiring board.
And the heat is released.
【0009】[0009]
【発明が解決しようとする課題】上述した集積回路のダ
イ1は、熱の放出を良くするために、図5に示すよう
に、接着剤2でプリント配線板上のパターン3に接着
し、そのパターン3はスルーホール4でグランド層及び
集積回路実装面と反対側の面に設けられたパターン5に
接続され、さらにそのパターン5に放熱片6が取り付け
られるように実装している。The above-mentioned integrated circuit die 1 is bonded to a pattern 3 on a printed wiring board with an adhesive 2 as shown in FIG. The pattern 3 is connected to the pattern 5 provided on the surface opposite to the ground layer and the integrated circuit mounting surface through the through hole 4, and further mounted so that the heat radiation piece 6 is attached to the pattern 5.
【0010】また、集積回路のダイ1の裏面は、電気的
特性を満足させるために接地電位とする必要があるた
め、上述した実装では、ダイ1とプリント配線板上の接
続用パターン3は導電性接着剤2で接続し、接続用パタ
ーンの電位を接地電位としなければならず、かつ、集積
回路からの発熱を効率良く放熱片に伝達するために、ダ
イ1の裏面とプリント配線板の接続用パターン3との接
着面積は最大限に大きくしなければならない。In addition, since the back surface of the die 1 of the integrated circuit needs to be at the ground potential in order to satisfy electrical characteristics, in the above-described mounting, the die 1 and the connection pattern 3 on the printed wiring board are conductive. In order to transfer the potential of the connection pattern to the ground potential and to efficiently transmit the heat generated from the integrated circuit to the heat radiating piece, the connection between the back surface of the die 1 and the printed wiring board is required. The bonding area with the application pattern 3 must be maximized.
【0011】しかしながら、接着面積を最大限に大きく
すると、導電性接着剤2がダイ1の外形以上にはみ出し
て濡れ広がってしまい、アウターリードを短絡してしま
う恐れがあり、接着剤の塗布量及び濡れ広がり面積の制
御を高精度に行わなければならないという問題点があっ
た。However, if the bonding area is maximized, the conductive adhesive 2 may protrude beyond the outer shape of the die 1 and spread, resulting in short-circuiting of the outer leads. There was a problem that the wet spread area had to be controlled with high precision.
【0012】本発明の目的は、接着剤の塗布量及び濡れ
広がり面積の制御を高精度に行うことなく、接着剤のは
み出しによるアウタリードの短絡を防止することが可能
な技術を提供することにある。An object of the present invention is to provide a technique capable of preventing short-circuiting of an outer lead due to the protrusion of an adhesive without controlling the amount of adhesive applied and the spread area of the adhesive with high precision. .
【0013】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【0014】[0014]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.
【0015】集積回路とプリント配線基板との接着面の
中央部分に導電性の高い接着剤を塗布し、その中央部分
を囲む接着面の周囲部分に絶縁性の高い接着剤を塗布
し、集積回路をプリント配線基板上に実装する。[0015] A highly conductive adhesive is applied to the central portion of the adhesive surface between the integrated circuit and the printed wiring board, and a highly insulating adhesive is applied to a peripheral portion of the adhesive surface surrounding the central portion. Is mounted on a printed wiring board.
【0016】[0016]
【発明の実施の形態】以下、本発明の実施形態にかかる
集積回路の実装方法について図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for mounting an integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings.
【0017】図1は、集積回路を実装するプリント基板
における接着剤の塗布を説明するための図である。図1
において、8は集積回路のダイの外形、9は導電性接着
剤、10は絶縁性接着剤をそれぞれ示す。FIG. 1 is a diagram for explaining the application of an adhesive on a printed circuit board on which an integrated circuit is mounted. FIG.
In the figure, 8 indicates an outer shape of a die of an integrated circuit, 9 indicates a conductive adhesive, and 10 indicates an insulating adhesive.
【0018】本実施形態の集積回路の実装は、図1に示
すように、プリント配線板上に設けられた集積回路のダ
イを接続するための接続用パターン3の中央部分、即ち
集積回路のダイ外形8の中央部分に導電性接着剤9を塗
布し、更にその導電性接着剤9の周囲に絶縁性接着剤1
0を塗布する。上述した導電性接着剤9は、導電性が高
い接着剤であれば良く、例えば、銀ペースト等を用い
る。絶縁性接着剤10は、絶縁性、かつ、熱伝導性が高
い接着剤であれば良く、例えば、シリコン系の接着剤等
を用いる。As shown in FIG. 1, the integrated circuit according to the present embodiment is mounted on a central portion of a connection pattern 3 for connecting an integrated circuit die provided on a printed wiring board, that is, an integrated circuit die. A conductive adhesive 9 is applied to a central portion of the outer shape 8, and an insulating adhesive 1 is further provided around the conductive adhesive 9.
0 is applied. The conductive adhesive 9 described above may be an adhesive having high conductivity, and for example, a silver paste or the like is used. The insulating adhesive 10 may be an adhesive having high insulating properties and high thermal conductivity. For example, a silicon-based adhesive or the like is used.
【0019】その後に、集積回路を実装すると、図2に
示すように、集積回路のダイ1により各接着剤9、10
は押し広げられて集積回路のダイ1とプリント配線板上
の接続用パターン3との間で濡れ広がる。After that, when the integrated circuit is mounted, as shown in FIG.
Are spread and wet between the die 1 of the integrated circuit and the connection pattern 3 on the printed wiring board.
【0020】図3は、その集積回路のダイ1とプリント
基板の接着部分の断面形状を示したものである。図2及
び図3に示すように、導電性接着剤9は、絶縁性接着剤
10によるダム効果により集積回路のダイ外形8より充
分小さな範囲でのみ濡れ広がり、アウターリード7に付
着することなく集積回路のダイ裏面とプリント配線板上
の接続用パターン3とを電気的に接続することが可能に
なる。FIG. 3 shows the cross-sectional shape of the bonding portion between the die 1 of the integrated circuit and the printed circuit board. As shown in FIGS. 2 and 3, the conductive adhesive 9 wets and spreads only in a range sufficiently smaller than the die outer shape 8 of the integrated circuit due to the dam effect of the insulating adhesive 10 and is integrated without adhering to the outer leads 7. It is possible to electrically connect the back surface of the die of the circuit and the connection pattern 3 on the printed wiring board.
【0021】また、導電性接着剤9の周囲に塗布した絶
縁性接着剤10は、絶縁性であるためアウターリードに
付着しても短絡することはないので良好な放熱効果を得
るために十分な量を塗布する事が可能となる。The insulating adhesive 10 applied around the conductive adhesive 9 is insulative and does not short-circuit even if it adheres to the outer leads. The amount can be applied.
【0022】また、上述した導電性接着剤9と絶縁性接
着剤10は、それぞれ異なる成分からなる接着剤である
ため、それぞれの粘度等により、均一な接着層を得るこ
とができなくなることがある。Further, since the above-mentioned conductive adhesive 9 and insulating adhesive 10 are adhesives composed of different components, a uniform adhesive layer may not be obtained due to their respective viscosities. .
【0023】このような場合、図4に示すように、中央
部分のスルーホール4a(導電性接着剤9が塗布される
部分の径の大きさと周囲部分のスルーホール4b(絶縁
性接着剤10が塗布される部分)の径の大きさをそれぞ
れの粘度に応じて変えることによって均一な接着層を得
ることが可能になる。In such a case, as shown in FIG. 4, the through hole 4a in the center portion (the diameter of the portion to which the conductive adhesive 9 is applied and the through hole 4b in the peripheral portion (the insulating adhesive 10 A uniform adhesive layer can be obtained by changing the size of the diameter of the portion to be applied) according to the respective viscosities.
【0024】例えば、集積回路のダイ1の中央部分に塗
布した導電性接着剤9に比べ、その周辺に塗布した絶縁
性接着剤10の方がスルーホールを通してプリント配線
板の裏面に流出し易い場合には、中央部分のみ集積回路
のダイ1の裏面とプリント配線板上の接続用パターン3
間に接着剤層を形成し、周辺部分の接着が不完全となる
ため、図4に示すように、周囲部分のスルーホール4b
の径を中央部分のスルーホール4aの径に比し小さくす
る。これにより、均一な接着層を得ることが可能とな
る。For example, when the insulating adhesive 10 applied to the periphery of the integrated circuit die 1 is more likely to flow out to the back surface of the printed wiring board through the through hole than the conductive adhesive 9 applied to the central portion of the die 1 of the integrated circuit. In the figure, only the central portion has the back surface of the integrated circuit die 1 and the connection pattern 3 on the printed wiring board.
Since an adhesive layer is formed in between and the adhesion of the peripheral portion is incomplete, as shown in FIG.
Is smaller than the diameter of the through hole 4a at the center. Thereby, it is possible to obtain a uniform adhesive layer.
【0025】また、図4に示すように、中央部分のスル
ーホール4a(導電性接着剤9が塗布される部分)の径
を大きくすることによって、導電性接着剤9の接続面積
が大きくすることができ、導電性を向上することが可能
となる。As shown in FIG. 4, by increasing the diameter of the through hole 4a (the portion to which the conductive adhesive 9 is applied) at the center, the connection area of the conductive adhesive 9 can be increased. And the conductivity can be improved.
【0026】なお、上述したような2種類の接着剤を用
いた実装だけでなく、集積回路のダイ1とプリント配線
基板上のパターンを導電性、かつ、良熱伝導性の接着シ
ートで接続しても、同様に、アウターリードの短絡を防
止できる。In addition to the above-described mounting using two types of adhesives, the die 1 of the integrated circuit and the pattern on the printed wiring board are connected by a conductive and good heat conductive adhesive sheet. Similarly, short-circuiting of the outer lead can be prevented.
【0027】したがって、説明してきたように、集積回
路とプリント配線基板との接着面の中央部分に導電性接
着剤を塗布し、その中央部分を囲む接着面の周囲部分に
絶縁性接着剤を塗布し、集積回路をプリント配線基板上
に実装することにより、絶縁性接着剤がダムとなり導電
性接着剤はアウターリード側にはみ出して濡れ広がるこ
とがなくなるので、接着剤の塗布量及び濡れ広がり面積
の制御を高精度に行うことなく、接着剤のはみ出しによ
るアウタリードの短絡を防止することが可能になる。Therefore, as described above, a conductive adhesive is applied to the central portion of the bonding surface between the integrated circuit and the printed wiring board, and an insulating adhesive is applied to the peripheral portion of the bonding surface surrounding the central portion. However, by mounting the integrated circuit on the printed wiring board, the insulating adhesive becomes a dam, and the conductive adhesive does not protrude to the outer lead side and does not spread. Without performing the control with high precision, it is possible to prevent the outer leads from being short-circuited due to the protrusion of the adhesive.
【0028】以上、本発明者によってなされた発明を、
前記実施形態に基づき具体的に説明したが、本発明は、
前記実施形態に限定されるものではなく、その要旨を逸
脱しない範囲において種々変更可能であることは勿論で
ある。As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.
【0029】[0029]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
【0030】接着剤の塗布量及び濡れ広がり面積の制御
を高精度に行うことなく、接着剤のはみ出しによるアウ
タリードの短絡を防止することが可能になる。It is possible to prevent the outer leads from being short-circuited due to the protrusion of the adhesive without controlling the amount of the adhesive applied and the wet spread area with high precision.
【図1】本発明の実施形態にかかる集積回路の実装方法
における接着剤の塗布を説明するための図である。FIG. 1 is a diagram for explaining application of an adhesive in a method of mounting an integrated circuit according to an embodiment of the present invention.
【図2】集積回路のダイ1とプリント基板の接着部分の
形状を示した図である。FIG. 2 is a diagram showing a shape of an adhesive portion between a die 1 of an integrated circuit and a printed board.
【図3】集積回路のダイとプリント基板の接着部分の断
面形状を示した図である。FIG. 3 is a diagram illustrating a cross-sectional shape of an adhesive portion between a die of an integrated circuit and a printed circuit board.
【図4】集積回路のダイとプリント基板の接着面の中央
部分と周囲部分のスルーホールの径の大きさを変えたプ
リント配線基板を示した図である。FIG. 4 is a diagram showing a printed wiring board in which the diameters of through holes in the central part and the peripheral part of the bonding surface between the die of the integrated circuit and the printed board are changed.
【図5】従来のTCPに封止された集積回路のプリント
配線板上への実装方法を説明するための図である。FIG. 5 is a view for explaining a conventional method of mounting an integrated circuit sealed in TCP on a printed wiring board.
1…集積回路のダイ、2…接着剤、3…ダイ接続用パタ
ーン、4,4a,4b…スルーホール、5…放熱片接続
用パターン、6…放熱片、7…アウターリード、8…集
積回路のダイ外形、9…導電性接着剤、10…絶縁性接
着剤。DESCRIPTION OF SYMBOLS 1 ... Die of integrated circuit, 2 ... Adhesive, 3 ... Die connection pattern, 4, 4a, 4b ... Through hole, 5 ... Heat dissipation piece connection pattern, 6 ... Heat dissipation piece, 7 ... Outer lead, 8 ... Integrated circuit Die outer shape, 9: conductive adhesive, 10: insulating adhesive.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 水野 秀明 愛知県尾張旭市晴丘町池上1番地 株式会 社日立製作所情報機器事業部内 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hideaki Mizuno 1 Ikegami, Haruoka-cho, Owariasahi-shi, Aichi Pref. Information Equipment Division, Hitachi, Ltd.
Claims (2)
線板上に実装する集積回路の実装方法において、 前記集積回路とプリント配線基板との接着面の中央部分
に導電性の高い接着剤を塗布し、その中央部分を囲む接
着面の外側部分に絶縁性の高い接着剤を塗布し、集積回
路をプリント配線基板上に実装することを特徴とする集
積回路の実装方法。1. An integrated circuit mounting method for applying an adhesive to an integrated circuit and mounting the integrated circuit on a printed wiring board, wherein a highly conductive adhesive is applied to a central portion of a bonding surface between the integrated circuit and the printed wiring board. A method for mounting an integrated circuit, comprising applying a highly insulating adhesive to an outer portion of an adhesive surface surrounding a central portion thereof, and mounting the integrated circuit on a printed wiring board.
法において、 前記プリント配線基板上のパターンに配されるスルーホ
ールの径を前記集積回路との接着面の中央部分と周囲部
分とで異なる大きさにして前記集積回路を前記プリント
基板上に実装することを特徴とする集積回路の実装方
法。2. The method of mounting an integrated circuit according to claim 1, wherein a diameter of a through hole arranged in a pattern on the printed wiring board is determined by a central portion and a peripheral portion of a bonding surface with the integrated circuit. A method of mounting an integrated circuit, wherein the integrated circuit is mounted on the printed circuit board with different sizes.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8301487A JPH10144725A (en) | 1996-11-13 | 1996-11-13 | Method of mounting integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8301487A JPH10144725A (en) | 1996-11-13 | 1996-11-13 | Method of mounting integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10144725A true JPH10144725A (en) | 1998-05-29 |
Family
ID=17897509
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8301487A Pending JPH10144725A (en) | 1996-11-13 | 1996-11-13 | Method of mounting integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH10144725A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001097277A1 (en) * | 2000-06-16 | 2001-12-20 | Matsushita Electric Industrial Co., Ltd. | Electronic parts packaging method and electronic parts package |
-
1996
- 1996-11-13 JP JP8301487A patent/JPH10144725A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001097277A1 (en) * | 2000-06-16 | 2001-12-20 | Matsushita Electric Industrial Co., Ltd. | Electronic parts packaging method and electronic parts package |
US7355126B2 (en) * | 2000-06-16 | 2008-04-08 | Matsushita Electric Industrial Co., Ltd. | Electronic parts packaging method and electronic parts package |
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