JPH10143265A - Band gap reference circuit having start circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the current consumption and to quicken the rise of an output voltage. SOLUTION: Voltages V11 and V12 generated by transistors Q1 and Q2 and resistors R1-R3 are differentially amplified by an operational amplifier OP1 so that a reference output voltage Vf can be provided, and this is amplified by an operational amplifier OP2 so that an output voltage Vout can be provided. A start circuit ST is composed of a p channel MOS transistor PM1 connecting its drain to a power source VDD and its source to the bases of the Q1 and Q2 and a buffer circuit Buff connecting its input terminal to the output terminal of the OP2 and connecting its output terminal to the gate of PM1. When a power source is turned on, the PM1 is conducted, supplies the base current of Q1 and Q2 and activates the circuit. When the circuit is activated, the output voltage Vout rises so that a gate input voltage Vi gets high and the pM1 is turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bandgap reference circuit used as a reference voltage source in a semiconductor integrated circuit, and more particularly to a bandgap reference circuit having a starting circuit.

[0002]

2. Description of the Related Art Bandgap reference circuits have a very low temperature coefficient and are widely used in semiconductor integrated circuits to produce a relatively constant and stable reference voltage. This voltage may be used, for example, for setting a relatively constant current, or for emitter coupled logic (ECL).
Used as the input reference voltage for the circuit. A band gap reference circuit usually has two stable points. That is, a point where the output becomes zero and a point where a desired output voltage is generated. Therefore, it is necessary to add a start-up circuit (start-up circuit) in order to escape the zero stable point at the time of start-up, and several circuits for this purpose have been proposed.

FIG. 6A is a circuit diagram of a band gap reference circuit having a starting circuit proposed in Japanese Patent Application Laid-Open No. 3-123209, and FIG. 6B is used therein. FIG. 3 is a circuit diagram of an operational amplifier (hereinafter, referred to as a first conventional example). In FIG. 6A, the collectors of the transistors Q11 and Q12 are connected to a positive voltage power supply V.
Each base is connected to the output terminal (Vout) of the operational amplifier OP. The emitter of Q11 is connected to the inverting input terminal of the operational amplifier OP and is grounded via the resistor R13. Also, the transistor Q
Twelve emitters are connected in series with resistors R11, R12
, And the connection point of these resistors is connected to the non-inverting input terminal of the operational amplifier OP.

The starting circuit ST has a collector connected to the power supply VDD.
The transistor Q13 has an emitter connected to the bases of the transistors Q11 and Q12, and resistors R14 and R15 connected in series between the power supply VDD and the ground to apply a base bias to the transistor Q13. The operational amplifier OP, as shown in FIG.
A differential circuit composed of p-channel MOS transistors pM11 and pM12 as drive transistors, n-channel MOS transistors nM11 and nM12 as load transistors, and an output circuit composed of an n-channel MOS transistor nM13 and a capacitor C. It has. PM1 constituting the driving transistor
1. The pM12 is configured such that the ratio of the channel width W to the channel length L is imbalanced with each other such that W / L (pM11)> W / L (pM12).

In this conventional circuit, two types of starting circuits are provided. Before describing the circuit, a normal band gap reference operation will be described first. Operational amplifier O
Due to the action of P, the potentials at the inverting and non-inverting input terminals of the operational amplifier OP become substantially the same, so that the base-emitter voltages Vbe (Q11) and Vbe (Q1
2) IE current flowing through Q11 and Q12
(Q11) and IE (Q12), Vbe (Q11) = Vbe (Q12) + IE (Q12)
R11 is represented. Vout−Vbe (Q12) = (R11 + R12) IE
(Q12), Vout = Vbe (Q11) + (Vbe (Q11) −V
be (Q12)) × R12 / R11.

Now, the emitter area of Q12 is N
If it is doubled, Vbe (Q11) -Vbe (Q12) = VTln (N.IE (Q11) / IE (Q12)). Here, VT = kT / q. On the other hand, since the potentials of the inverting and non-inverting input terminals of the operational amplifier OP are substantially the same, IE (Q11) R13 = IE (Q12) R12, and IE (Q11) / IE (Q12) = R12 / R13. Become. Accordingly, the output voltage Vout is as follows: Vout = Vbe (Q11) + (R12 / R11) VT In (NR12 / R13) (1) Therefore, ∂Vout / ∂T = 0, that is, ∂Vbe (Q11) / ∂T = − (R12 / R11) ln
If R11, R12, R13, and N are determined so as to satisfy the condition of (NR12 / R13) ∂VT / ∂T, a reference voltage with extremely low temperature fluctuation can be obtained.

If the starting circuit ST is not provided in this circuit and the operational amplifier OP has a negative offset voltage, the operational amplifier OP draws the base current of Q11 and Q12. No emitter current flows through Q12, and the circuit cannot be started. Therefore, in the conventional example described in JP-A-3-123209, the differential circuit of the operational amplifier OP is configured to be unbalanced, so that the operational amplifier OP can be started with a positive offset. further,
A start circuit ST is provided to separately supply a base current to Q11 and Q12 to ensure start-up.

FIG. 7 is a circuit diagram of a bandgap reference circuit having a starting circuit proposed in Japanese Patent Application Laid-Open No. 4-158418 (hereinafter referred to as a second conventional example). In this conventional example, transistors Q21, Q2
2. The voltage V1 generated by the resistors R21 to R23
1, and V12 are differentially amplified by an operational amplifier OP21 to output a reference output voltage Vf, which is further amplified by an operational amplifier OP22.
To obtain an output voltage Vout. Starting circuit S
In T, the output voltage Vout is changed to the NAND gate N21 controlled by the inverter In21 and the power down signal PS.
Via A, the drain is input to the non-inverting input terminal of the operational amplifier OP21, and the source is input to the gate of the p-channel MOS transistor pM21 connected to the power supply VDD.

In the circuit shown in FIG. 7, when the power down signal PS is high when the power is turned on, the output of the NAND gate NA becomes low and the MOS transistor p
M21 conducts and sets the non-inverting input terminal of the operational amplifier OP21 to high level. Thereby, the reference output voltage Vf,
The output voltage Vout can rise, and the state of zero output can be escaped. When the output voltage Vout rises, the output of the NAND gate NA of the starting circuit ST goes high, pM21 turns off, and the starting circuit ST is disconnected from the reference voltage generating circuit.

[0010]

In the first prior art example (FIG. 6) described above, there is a problem that the current consumption increases because the current always flows through the starting circuit ST. This problem is a significant deficiency in integrated circuits that require multiple reference voltage sources. There is also a problem that the operation of the bandgap reference circuit after starting is affected by the current supplied by the starting circuit ST.

In the first conventional example, the operational amplifier is configured to generate a positive offset in order to guarantee that starting occurs. That is, a positive design offset voltage is generated by making the ratio (W / L) of the channel width W and the channel length L of the drive transistors pM11 and pM12 of the differential circuit different. Since the offset voltage introduced by configuring the operational amplifier OP to be unbalanced has a temperature dependency, a temperature-dependent error is introduced into Vout. Normally, a desired voltage obtained by amplifying this Vout is used as the reference voltage, and thus the introduced offset voltage is also amplified, so that it is used in an environment with a large temperature change or an application requiring an accurate reference voltage. ,
The existence of the temperature-dependent error cannot be ignored.

Further, the above-mentioned second conventional example (FIG. 7) has a disadvantage that the time required for the output voltage Vout to settle to the original output value after the p-channel MOS transistor pM21 is turned off becomes long. That is, the second
In the circuit of the related art, the high voltage applied to the non-inverting input terminal of the operational amplifier OP21 is pulled down through a loop including the operational amplifier OP21 and the transistors Q22 and R22, so that the reference output voltage Vf and the output voltage Vou.
It takes time for t to settle to a steady value.

Therefore, the problem to be solved by the present invention is:
It is as follows. The starting current is allowed to flow only when the bandgap reference may fail to start (i.e., the starting circuit current is zero after starting is started). After starting, the starting circuit does not affect the output voltage Vout, so that the starting circuit can prevent the output voltage Vout from introducing an error. The output voltage value of the bandgap reference is stabilized more quickly so that it can be used in higher operating frequency applications.

[0014]

An object of the present invention is to supply a current required for starting by a switching element whose on / off is controlled by an output signal of a band gap reference circuit. This problem can be solved by adopting a means that the current injected by the switching element is quickly removed by the bipolar transistor that generates the reference voltage after the switching element is turned off.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A band gap reference circuit according to the present invention has two bipolar transistors (Q
1, Q2) and resistors (R1, R2, R3) for generating a reference voltage, and a two-stage operational amplifier (OP) for amplifying the reference voltage generated by the reference voltage generation circuit
1, OP2) and a starting circuit (ST) for supplying a starting current. The starting circuit (ST) includes a one-stage or two-stage inverter (In1; B)
uff) and a MOS transistor (pM1; nM1), and the control signal is given from the output terminal (Vout) of the second-stage operational amplifier. The output signal of the starting circuit is used to supply the base current of the two bipolar transistors in the case of the band gap reference circuit of the positive power supply, and is used in the case of the band gap reference circuit of the negative power supply. It is used to apply a starting voltage to the inverting input terminal of the operational amplifier (OP1) at the stage.

[Operation] The operation of the bandgap reference circuit of the present invention will be described with reference to a circuit using a positive power supply. In the band gap reference circuit of the present invention, since the control signal of the starting circuit is obtained from the output terminal of the second-stage operational amplifier, the failure of starting the band gap reference circuit can be reliably detected. Since the starting current is injected into the bases of the two bipolar transistors forming the reference voltage generating circuit by the starting circuit, the reference voltage can be reliably generated and the starting can be performed. After starting, MO
Since the S transistor is cut off, the influence of the starting circuit on the circuit operation of the reference circuit can be eliminated. In addition, since the inverter and the buffer for controlling the MOS transistors are constituted by CMOS circuits, the current consumption of the starting circuit in a steady state can be made substantially zero. Further, after the start, the starting current injected into the base of the bipolar transistor of the reference voltage generating circuit at the time of starting can be quickly eliminated through the bipolar transistor, so that the output voltage Vout is not changed until the output voltage Vout reaches the set value. Time can be reduced.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention. In the figure, Q1 and Q2 are bipolar transistors, R1 to R5 are resistors, OP1, OP
Reference numeral 2 denotes a first and a second operational amplifier, and ST denotes a starting circuit including a buffer circuit Buff including a CMOS-structured two-stage inverter and a p-channel MOS transistor pM1. In the circuit of this embodiment, the starting circuit ST
Since the basic configuration of the bandgap reference circuit main body except for the above is the same as that of the conventional example, detailed description thereof is omitted. This embodiment is characterized in that the source of the starting circuit ST is connected to the power supply VDD, and the drain of the p-channel MOS transistor pM1 is connected to the bipolar transistor Q.
1 and Q2. In addition,
The transistor Q2 has a wider emitter region than the transistor Q1.

Next, the operation of the circuit of this embodiment will be described with reference to FIGS. FIGS. 2A and 2B are simulation results showing the rising states of the gate input voltage Vi, the reference output voltage Vf, and the node voltages V11 and V12 of the circuits shown in FIGS. 1 and 7, respectively. In the circuit of the present embodiment shown in FIG. 1, all the node voltages are 0 V before the power is turned on. When the power is turned on, since the gate input voltage Vi is 0 V, the pM1 immediately conducts and supplies a starting current to the bases of the bipolar transistors Q1 and Q2, thereby conducting the Q1 and Q2. As a result, the reference output voltage Vf rises rapidly as shown in FIG. The starting current is the output voltage of the buffer circuit Buff (gate input voltage Vout) when the output voltage Vout rises.
Continue to flow to pM1 until i) goes high. This high state is seen at t = 28 ns in FIG. When the starting is completed, the MOS transistor pM1 is cut off, and the current flowing through the starting circuit ST becomes almost zero. Therefore, the above-mentioned problem to be solved is solved.

When the MOS transistor pM1 is turned off, the starting circuit is disconnected from the feedback loop of the reference circuit. Thereby, the above-mentioned problem to be solved is solved. Further, when pM1 is turned off, the current (charge) injected into the bases of the transistors Q1 and Q2 is immediately removed by Q1 and Q2. That is, the above-mentioned problem to be solved is solved. As shown in FIG. 2A, the reference output voltage Vf is about 70 ns after the power is turned on.
Thus, the set voltage Vf = 1.25 V has been reached.
On the other hand, in the conventional circuit shown in FIG. 7, as shown in FIG. 2B, the reference output voltage Vf and the node voltages V11 and V11 after the gate input voltage Vi rises (a).
12 has a gentle fall. In the conventional circuit, the reference output voltage Vf requires about 90 ns after power-on to reach the set voltage Vf = 1.25 V. This is due to pM21 charging the non-inverting terminal of OP21.

Second Embodiment FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In this figure, parts that are the same as the parts of the first embodiment shown in FIG. 1 are given the same reference numerals, and duplicate explanations are omitted. The difference of the present embodiment from the first embodiment is that the transistor for supplying the base current to the transistors Q1 and Q2 at the time of starting is n
A channel MOS transistor nM1 is provided, and a circuit element connected between the output terminal of the second operational amplifier OP2 and the gate of nM1 is accordingly a buffer circuit Buff
Is changed to a CMOS configuration inverter In1. The operation is the same as in the first embodiment.

Third Embodiment FIG. 4 is a circuit diagram showing a third embodiment of the present invention. The circuit of this embodiment is used when a negative voltage power supply is used, and has a negative output voltage Vo.
ut is obtained. In this figure, parts that are the same as the parts of the first embodiment shown in FIG. 1 are given the same reference numerals. The bases and collectors of transistors Q1 and Q2 for generating a reference voltage are grounded, and the emitter of Q1 is a resistor R
1 is connected to the output terminal of the first operational amplifier OP1, and the emitter of Q2 is connected to the output terminal of the first operational amplifier OP1 via the resistors R2 and R3. And
The connection point between the emitter of Q1 and R1 is the first operational amplifier O
It is connected to the non-inverting input terminal of P1, and the connection point between R2 and R3 is connected to the inverting input terminal of the first operational amplifier OP1. The starting circuit ST has a source of the first operational amplifier O
Connected to the inverting input terminal of P1 and drain connected to power supply VEE
A p-channel MOS transistor pM1 connected to
A CMOS having an input terminal connected to the output terminal of the second operational amplifier OP2 and an output terminal connected to the gate of pM1
And the configured inverter In1.

In the circuit of this embodiment shown in FIG. 4, after the start, the first operational amplifier OP1 outputs the negative reference output voltage Vf.
And the transistors Q1 and Q2 conduct to maintain a stable state. However, if the start fails, the transistors Q1 and Q2 do not conduct, and the output voltages Vf and Vout become zero.
V. Therefore, a start circuit ST is provided to assist the start of the band gap reference circuit. Immediately after power-on, the output voltage Vout is at a high level (ground level), so that the gate of pM1 is at a low level, and pM1 is turned on. As a result, the inverting input terminal of the first operational amplifier OP1 becomes low level, the transistor Q2 conducts, and the reference output voltage Vf of the operational amplifier OP1 rises to a negative voltage. As a result, Q1 also conducts, and the start is completed. When the start is completed, the output voltage Vo
When the output signal ut goes low, the inverter In1
Becomes high level and pM1 is turned off. When pM1 is turned off, the charge injected into the node of the inverting input terminal of OP1 is quickly eliminated by the transistor Q2.

[Fourth Embodiment] FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention. In this figure, parts that are the same as the parts of the third embodiment shown in FIG. 4 are given the same reference numerals, and duplicate explanations are omitted. The difference of this embodiment from the third embodiment is that the transistor for supplying a negative voltage to the inverting input terminal of the first operational amplifier OP1 at the time of starting is an n-channel MOS transistor nM1, and the second operational amplifier The point is that the circuit element connected between the gate of OP2 and the gate of nM1 is changed from the inverter In1 to the buffer circuit Buff of the CMOS configuration. The operation is similar to that of the third embodiment.

[0024]

As described above, the band gap reference circuit of the present invention supplies the starting current by the switching element whose on / off is controlled by the output signal of the operational amplifier, and performs switching when the switching element is turned off. Since the charge injected by the element is quickly removed by the bipolar transistor, the following effects can be obtained. The current consumption of the starting circuit can be reduced to 0 after the start of the circuit, and power consumption can be reduced. After starting, the starting circuit can be prevented from affecting the circuit operation of the band gap reference circuit main body, and a stable reference voltage can be provided. After the power is turned on, the reference output voltage Vf and the output voltage Vou
The time until t rises to the voltage of the set value can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing simulation results of the first embodiment and a second conventional example.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram of a first conventional example.

FIG. 7 is a circuit diagram of a second conventional example.

[Explanation of symbols]

ST starting circuit OP, OP1, OP2, OP21, OP22 Operational amplifier

Claims (6)

[Claims] 1. A first transistor having a collector connected to a power supply and an emitter grounded via a first resistor, and a second transistor having a collector connected to the power supply and an emitter connected in series.
And a second transistor grounded via a third resistor and the emitter of the first transistor are connected to an inverting input terminal, and a connection point of the second and third resistors is connected to a non-inverting input terminal. A first-stage operational amplifier whose output signal provides a base current of the first and second transistors;
Receives and amplifies the output signal of the first operational amplifier 2
ON / OFF is controlled by an output signal of the operational amplifier of the second stage and the operational amplifier of the second stage.
And a switching means for supplying a base current to the second transistor. 2. A band gap reference circuit having a starting circuit according to claim 1, wherein said switching means comprises a p-channel or n-channel MOS transistor. 3. The switching means is controlled by an output signal of a CMOS-structured inverter or a CMOS-structured buffer circuit to which an output signal of the second-stage operational amplifier is input. 3. A band gap reference circuit having the starting circuit according to 2. 4. A first transistor having a collector and a base grounded and an emitter connected to one end of the first resistor, and a second and third resistor having a collector and a base grounded and an emitter connected in series. A second transistor connected to the other end of the first resistor, a non-inverting input terminal connected to the emitter of the first transistor, and an inverting input terminal connected to a connection point of the second and third resistors. And
A first-stage operational amplifier having an output terminal connected to the other end of the first resistor, a second-stage operational amplifier receiving and amplifying an output signal of the first-stage operational amplifier; ON / OFF is controlled by the output signal of the operational amplifier of the eye,
Switching means for turning on when the absolute value of the output voltage of the operational amplifier of the second stage is lower than a predetermined value and supplying a starting current to a connection point between the second and third resistors. A band gap reference circuit having a starting circuit. 5. The band gap reference circuit having a starting circuit according to claim 4, wherein said switching means is constituted by a p-channel or n-channel MOS transistor. 6. The switching means is controlled by an output signal of a CMOS-structured inverter or a CMOS-structured buffer circuit to which an output signal of the second-stage operational amplifier is input. A band gap reference circuit comprising the starting circuit according to claim 5.