JP2006222495A - Photocurrent detection circuit - Google Patents

Photocurrent detection circuit Download PDF

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JP2006222495A
JP2006222495A JP2005031365A JP2005031365A JP2006222495A JP 2006222495 A JP2006222495 A JP 2006222495A JP 2005031365 A JP2005031365 A JP 2005031365A JP 2005031365 A JP2005031365 A JP 2005031365A JP 2006222495 A JP2006222495 A JP 2006222495A
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terminal
photodiode
input terminal
inverting input
bias voltage
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Shuzo Hiraide
修三 平出
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Olympus Corp
オリンパス株式会社
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a photocurrent detection circuit capable of detecting a stable photocurrent with excellent an S/N ratio by optimally biasing a photodiode to suppress a dark current. <P>SOLUTION: The photocurrent detection circuit is configured to include: the photodiode 102; an operational amplifier 103 to the inverting the input terminal of which respective one-side terminals of the photodiode, an integration capacitor 105, and an analog switch 106 are connected, and to the output terminal of which the respective other-side terminals of the integration capacitor and the analog switch are connected; a voltage source 104 connected to the noninverting input terminal of the operational amplifier; and a bias voltage generating circuit for generating a prescribed bias voltage between the one-side terminal and the other-side terminal of the photodiode, and the bias voltage generating circuit generates an offset voltage as the prescribed bias voltage between the inverting input terminal and the noninverting input terminal of the operational amplifier. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a photocurrent detection circuit for detecting a photocurrent from a photodiode.

  Conventionally, as a photocurrent detection device for detecting photocurrent from a photodiode, for example, there is a photocurrent detection circuit used in a solid-state imaging device disclosed in Japanese Patent No. 2965777. FIG. 10 shows the configuration of the photocurrent detection circuit disclosed in the above publication. In the photocurrent detection circuit having the configuration shown in FIG. 10, reference numeral 1001 denotes a photodiode that converts a received optical signal into a current signal. The anode terminal of the photodiode 1001 is grounded, and the source terminal is grounded to the cathode terminal. The gate terminal of the NMOS transistor 1002, one end of the integration capacitor 1003 for storing photocurrent, and one end of the analog switch 1004 for resetting the integration capacitor 1003 are connected, and the drain terminal of the NMOS transistor is connected to the other terminal of the integration capacitor 1003. The other terminal of the analog switch 1004, the source terminal is connected to the power supply, and the gate terminal is connected to the drain terminal of the PMOS transistor 1005 biased to a predetermined voltage, and the output terminal 1007. In the photocurrent detection circuit shown in FIG. 10, reference numeral 1008 denotes an inverting amplifier, the NMOS transistor 1002 constituting the inverting amplifier 1008 is a source-grounded amplification transistor, and the PMOS transistor 1005 is an active load transistor. .

Next, the operation of the photocurrent detection circuit having such a configuration will be described. Before the photocurrent detection, the analog switch 1004 is in a closed state. At this time, the output terminal 1007 has an output voltage Vout as a voltage Vgs between the gate and source of the NMOS transistor 1002 as shown in the following equation (1). Is output.
Vout = Vgs (1)

Next, the analog switch 1004 is opened by a command (not shown), and photocurrent detection is started. When the analog switch 1004 is opened and the time T has elapsed, assuming that the photocurrent from the photodiode 1001 is Ip, the dark current is Id, and the value of the integrating capacitor is Cint, the output voltage Vout is expressed by the following equation (2). In addition,
Vout = Vgs + (Ip + Id) T / Cint (2)
Thus, a voltage signal is obtained.
Japanese Patent No. 2965777

  Incidentally, the dark current generated by the photodiode is affected by the bias voltage. Therefore, in order to suppress the dark current of the photodiode, the bias voltage to the photodiode must be optimized. Here, in the conventional photocurrent detection circuit shown in FIG. 10, the bias voltage to the photodiode 1001 is determined by the gate-source voltage Vgs of the NMOS transistor 1002. However, the gate-source voltage of the MOS transistor is usually several hundred mV or more, and when the optimum bias voltage to the photodiode is about several tens of mV, an appropriate bias voltage cannot be set. Further, the gate-source voltage Vgs of the MOS transistor varies greatly due to the influence of temperature variation and manufacturing variation of the threshold voltage Vth of the MOS transistor, and as a result, the amount of dark current varies. Furthermore, the dark current is temperature-dependent, resulting in a problem that the amount of dark current varies.

  The present invention has been made in order to solve the above-mentioned problems in the conventional photocurrent detection circuit. The photodiode is optimally biased to suppress the generation of dark current and detect a stable photocurrent with an excellent SN ratio. An object of the present invention is to provide a photocurrent detection circuit capable of performing the above.

  In order to solve the above-described problem, the invention according to claim 1 is configured such that one terminal of each of the photodiode, the capacitor, and the analog switch is connected to the photodiode and the inverting input terminal, and the non-inverting input terminal is connected to the non-inverting input terminal. An operational amplifier connected to the other terminal of the photodiode and connected to the output terminal of the capacitor and the analog switch, respectively, and a voltage source connected to a non-inverting input terminal of the operational amplifier; The photocurrent detection circuit includes a bias voltage generation circuit that generates a predetermined bias voltage between the one terminal and the other terminal of the photodiode.

  According to a second aspect of the present invention, in the photocurrent detection circuit according to the first aspect, the bias generation circuit includes an offset as the predetermined bias voltage between an inverting input terminal and a non-inverting input terminal of the operational amplifier. It is configured to generate a voltage.

  According to a third aspect of the present invention, in the photocurrent detection circuit according to the second aspect, the operational amplifier includes a first MOS transistor pair to which the inverting input terminal and the non-inverting input terminal are connected, and the first And a second MOS transistor pair that constitutes a current mirror circuit serving as an active load for the MOS transistor pair, and the bias voltage generation circuit includes the first MOS transistor pair or the second MOS transistor pair. , At least one of the paired MOS transistors is configured to generate the offset voltage by changing the ratio (W / L) of the gate width (W) and the gate length (L) of the paired MOS transistors. Is.

  According to a fourth aspect of the present invention, in the photocurrent detection circuit according to the second aspect, the operational amplifier includes a first MOS transistor pair to which the inverting input terminal and the non-inverting input terminal are connected, and the first A second MOS transistor pair constituting a current mirror circuit serving as an active load for the transistor pair, and first and second resistance elements respectively connected to the source terminals of the second MOS transistor pair, The bias voltage generation circuit is configured to generate the offset voltage by differentiating resistance values of the first resistance element and the second resistance element.

  According to a fifth aspect of the present invention, in the photocurrent detection circuit according to the first aspect, the bias voltage generation circuit includes an adjustment circuit that adjusts the predetermined bias voltage.

  The invention according to claim 6 is a photodiode, an operational amplifier in which one terminal of each of the photodiode, capacitor, and analog switch is connected to an inverting input terminal, and a voltage source is connected to a non-inverting input terminal; A buffer amplifier having an output terminal connected to the other terminal of the photodiode and a third resistance element having one terminal connected to the voltage source and the other terminal connected to the input terminal of the buffer amplifier and one terminal The other terminal of the third resistor element is connected to the other terminal of the third resistor element and the input terminal of the buffer amplifier, and the one terminal and the other terminal of the photodiode are connected to each other. A photocurrent detection circuit is configured with a bias voltage generation circuit for generating a predetermined bias voltage therebetween.

  According to a seventh aspect of the present invention, in the photocurrent detection circuit according to the sixth aspect of the present invention, the bias voltage generation circuit includes the third resistance element as a variable resistance element.

  The invention according to claim 8 is the photocurrent detection circuit according to claim 6 or 7, wherein the voltage source has a temperature coefficient corresponding to a temperature coefficient of dark current generated by the photodiode. It is.

  According to the first aspect of the present invention, since the photodiode is optimally biased by the bias voltage generation circuit, the photocurrent detection capable of detecting a stable photocurrent with an excellent S / N ratio while suppressing generation of dark current. A circuit can be realized. According to the second aspect of the present invention, the bias generation circuit generates an offset voltage as a predetermined bias voltage between the inverting input terminal and the non-inverting input terminal of the operational amplifier. A voltage can be generated, generation of dark current can be suppressed, and a stable photocurrent with an excellent SN ratio can be detected. According to the third and fourth aspects of the present invention, the offset voltage as the bias voltage is generated by breaking the pair property of the pair elements constituting the differential stage of the operational amplifier. The amount of offset voltage generated can be finely controlled by breaking the pairing, so the optimum photodiode bias voltage can be set, and the generation of dark current is suppressed and stable photocurrent with an excellent S / N ratio is detected. can do.

  According to the fifth aspect of the present invention, the bias voltage applied to the photodiode can be easily adjusted and optimized even after the photocurrent detection circuit is manufactured by the adjustment circuit. Stable photocurrent with excellent S / N ratio can be detected. According to the sixth aspect of the present invention, since an optimum bias voltage can be applied to the photodiode, it is possible to detect a stable photocurrent with an excellent S / N ratio while suppressing generation of dark current. According to the seventh aspect of the present invention, the bias voltage applied to the photodiode can be easily adjusted and optimized even after the photocurrent detection circuit is manufactured. Excellent and stable photocurrent can be detected. According to the eighth aspect of the invention, since the bias voltage applied to the photodiode corresponds to the temperature coefficient of the dark current generated by the photodiode, it is possible to cancel the dark current fluctuation accompanying the temperature change. It is possible to detect a stable photocurrent with a better SN ratio.

  Next, the best mode for carrying out the present invention will be described.

Example 1
First, Example 1 of the present invention will be described. FIG. 1 is a circuit configuration diagram showing Embodiment 1 of a photocurrent detection circuit according to the present invention. As shown in FIG. 1, in the photocurrent detection circuit 101 according to this embodiment, an anode terminal and a cathode terminal of a photodiode 102 for converting an optical signal into a current signal are an inverting input terminal of an operational amplifier 103 and a constant voltage source. 104 is connected to a non-inverting input terminal to which 104 is connected. The inverting input terminal of the operational amplifier 103 is connected to one end of an integration capacitor 105 that stores the photocurrent from the photodiode 102 and one end of an analog switch 106 that resets the integration capacitor 105. On the other hand, the other terminal of the capacitor 105, the other terminal of the analog switch 106, and the signal output terminal 107 are connected to the output terminal of the operational amplifier circuit 103. Note that when the voltage at the inverting input terminal is Vin and the voltage at the non-inverting input terminal is Vin + between the inverting input terminal and the non-inverting input terminal of the operational amplifier 103, the following equation (3) is satisfied. In addition,
Voff = Vin -- Vin + (3)
The offset voltage Voff is such that the value of the offset voltage Voff is set so that the value of the dark current generated from the photodiode is minimized.

Next, the operation of the photocurrent detection circuit 101 configured as described above will be described. Before the photocurrent detection, the analog switch 106 is in a closed state, and the integrating capacitor 105 is in a short circuit state. At this time, the operational amplifier 103 operates as a voltage follower from the output terminal 107 of the photocurrent detection circuit 101, the constant voltage source 104 is connected to the non-inverting input terminal of the operational amplifier 103, and the operational amplifier 103 is Since it has an offset voltage, as shown in the following equation (4),
Vout = Er + Voff (4)
The voltage Vout is output. Here, Er is a voltage value of the constant voltage source 104.

Next, when the analog switch 106 is opened by a command (not shown), the integrating capacitor 105 is electrically connected between the inverting input terminal and the output terminal of the operational amplifier 103, and the detection of the photocurrent is started. The photocurrent Ip and dark current Id generated by the photodiode 102 flow into the electrically connected integrating capacitor 105, and are stored as charges, and a voltage proportional to the amount of charges is output. That is, when the analog switch 106 is opened and the time T has elapsed, the signal output terminal 107 is expressed by the following equation (5):
Vout = Er + Voff + (Ip + Id) T / Cint (5)
Output a voltage signal. Here, Cint is the capacitance value of the integrating capacitor 105.

  In the photocurrent detection circuit configured as described above, the dark current Id becomes Id≈0 by the offset voltage generated between the inverting input terminal and the non-inverting input terminal, that is, the generation of the dark current is minimized. Since it can be biased optimally, it is possible to detect a stable photocurrent with an excellent SN ratio.

  Next, an example of a specific configuration of the operational amplifier 103 used in the above-described photocurrent detection circuit 101 will be described with reference to FIG. The operational amplifier 103 of this configuration example includes a differential stage 201 and an output stage 202 which is an inverting amplifier as shown in the figure. In the differential stage 201, the PMOS transistor 203 and the PMOS transistor 204 are different in the ratio W / L of the gate width (W) to the gate length (L), and the value is n: 1. The source terminals of 203 and PMOS transistor 204 are connected in common, and a constant current source 205 for supplying an operating current is connected to the commonly connected source terminals. Each of the source terminals is commonly grounded, and the drain terminal is connected to the drain terminal of the PMOS transistor 203. The NMOS transistor 207 has the drain terminal connected to the drain terminal of the PMOS transistor 204. Are connected in common, and the drain terminal of the NMOS transistor 206 is connected to the gate terminal of the NMOS transistor 206. The drain terminals of the PMOS transistor 204 and the NMOS transistor 207 are connected to the output stage 202. The NMOS transistor 206 and the NMOS transistor 207 have the same gate width to gate length ratio.

  The PMOS transistor 203 and the PMOS transistor 204 constitute a differential transistor pair 208 for inputting a differential signal, and the NMOS transistor 206 and the NMOS transistor 207 serve as an active load of the differential transistor pair 208. A current mirror circuit 209 is configured.

Next, the operation of the operational amplifier used in the thus configured photocurrent detection circuit will be described. When negative feedback is applied to the operational amplifier 103 through a path not shown, assuming that the current value of the constant current source 205 is Io, the gate width (W) and gates of the NMOS transistor 206 and NMOS transistor 207 constituting the current mirror circuit 209 Since the ratios of the lengths (L) are the same, the drain currents of the PMOS transistor 203 and the PMOS transistor 204 constituting the differential transistor pair 208 are the same.
I D203 = I D204 = Io / 2 (6)
It becomes. However, I D203 is the drain current of the PMOS transistor 203, and I D204 is the drain current of the PMOS transistor 204. By the way, generally, when the MOS transistor operates in the saturation region, the gate-source voltage V GS is given by the following equation (7).
V GS = √ (2 / k · L / W · I D ) + V th (7)
However, k is a process constant, L is a gate length, W gate width, ID is a drain current, and Vth is a threshold voltage.

Therefore, the voltage difference between the non-inverting input terminal and the inverting input terminal of the operational amplifier 103, that is, the offset voltage Voff is calculated as
Voff = Vin -- Vin + = V GS203 -V GS204
= {√ (2 / k · L 203 / W 203 · I D203 ) + V th }
-{√ (2 / k · L 204 / W 204 · ID 204 ) + V th } (8)
It becomes. However, V GS203 and V GS204 are the gate-source voltages of the PMOS transistor 203 and the PMOS transistor 204, respectively, L 203 and L 204 are the gate lengths of the PMOS transistor 203 and the PMOS transistor 204, respectively, and W 203 and W 204 Are the gate widths of the PMOS transistor 203 and the PMOS transistor 204, respectively.

The PMOS transistor 203 and the PMOS transistor 204 have different gate width (W) to gate length (L) ratio W / L, and their value is n: 1.
W 203 / L 203 = W / L,
W204 / L204 = 1 / n.W203 / L203 = 1 / n.W / L (9)
Then, the offset voltage Voff in the equation (8) is calculated from the equations (6) and (9) as shown in the following equation (10):
Voff = √ (Io / k · L / W) · {1-1 / √n} (10)
It becomes.

  In this way, n, which is the ratio of the gate width to the gate length of the MOS transistor of the differential transistor pair 208 in the differential stage 201, is changed, that is, the pair characteristics of the pair elements constituting the differential stage are destroyed, and the operational amplifier Since the offset voltage 103 is generated, the bias voltage to the photodiode 102 can be set from a very small value.

  Further, another specific configuration example of the operational amplifier used in the above-described photocurrent detection circuit will be described with reference to FIG. The operational amplifier 103 according to this configuration example includes a differential stage 301 and an output stage 302 which is an inverting amplifier, as shown in FIG. In the differential stage 301, the source terminals of the PMOS transistor 303 and the PMOS transistor 304 are commonly connected, and a constant current source 305 for supplying an operating current is connected to the commonly connected source terminals. The gate width is such that each source terminal is grounded in common, the drain terminal is connected to the drain terminal of the PMOS transistor 303, and the drain terminal is connected to the drain terminal of the PMOS transistor 304. The gate terminal of the NMOS transistor 307 having a ratio W / L of (W) to the gate length (L) which is m times larger than the ratio of the gate width (W) to the gate length (L) of the NMOS transistor 306 is commonly used. Further, the drain terminal of the NMOS transistor 306 is connected to the gate terminal of the NMOS transistor 306. The drain terminals of the PMOS transistor 304 and the NMOS transistor 307 are connected to the output stage 302. Note that the ratio between the gate width and the gate length of the PMOS transistor 303 and the PMOS transistor 304 is the same.

  As in the case shown in FIG. 2, the PMOS transistor 303 and the PMOS transistor 304 are a pair element constituting a differential stage, and constitute a differential transistor pair 308 for inputting a differential signal. The transistor 306 and the NMOS transistor 307 are also pair elements constituting a differential stage, and constitute a current mirror circuit 309 having a current mirror ratio of m times as an active load of the differential transistor pair 308.

Next, the operation of the operational amplifier used in the thus configured photocurrent detection circuit will be described. When negative feedback is applied to the operational amplifier 103 through a path (not shown), if the current value of the constant current source 305 is Io, the current mirror ratio of the current mirror circuit 309 is m times, so that the PMOS constituting the differential transistor pair 308 When the drain current of the transistor 303 and PMOS transistor 304, respectively, and I D 303, I D304, as shown in the following equation (11),
ID 303 = Io / (1 + m), ID304 = mIo / (1 + m) (11)
It becomes. Therefore, since the ratio of the gate width (W) to the gate length (L) of the PMOS transistor 303 and the PMOS transistor 304 constituting the differential transistor pair 308 is the same, the gate width and the gate length of the PMOS transistor 303 and the PMOS transistor 304 are set to W, respectively. , L, from Equations (7) and (11), the voltage difference between the non-inverting input terminal and the inverting input terminal of the operational amplifier 103, that is, the offset voltage Voff is expressed by the following equation (12):
Voff = Vin -- Vin + = V GS303 -V GS304
= {√ (2 / k · L / W · I D303 ) + V th }
− {√ (2 / k · L / W · I D304 ) + V th }
= √ (2Io / k · L / W) [√ {1 / (m + 1)} − √ {m / (m + 1)}] (12)
It becomes.

  Thus, the current mirror ratio is changed by changing the ratio W / L of the gate width (W) and the gate length (L) of the MOS transistors 306 and 307 constituting the current mirror circuit 309 in the differential stage 301. Since the configuration is such that the pair of elements constituting the dynamic stage is broken and the offset voltage of the operational amplifier 103 is generated, the bias voltage to the photodiode can be set from a very small value.

  Further, another specific configuration example of the operational amplifier used in the above-described photocurrent detection circuit will be described with reference to FIG. Similar to the configuration examples shown in FIGS. 2 and 3, the operational amplifier 103 according to this configuration example includes a differential stage 401 and an output stage 402 which is an inverting amplifier. In the differential stage 401, the PMOS transistors 403 and 404 have their source terminals connected in common, and further connected to the common connected source terminal is a constant current source 405 for supplying an operating current. The drain terminal of the PMOS transistor 403 is connected to the drain terminal, and the source terminal is connected to the other end of the resistance element 410 having a resistance value R1 with one end grounded, and the drain terminal is connected to the drain terminal. The drain terminal of the PMOS transistor 404 is connected, and the other end of the resistance element 411 having a resistance value R2 different from that of the resistance element 410 having one end grounded to the source terminal is connected to the NMOS transistor 407 The gate terminals of the NMOS transistors 406 are connected in common, and the drain terminal of the NMOS transistor 406 is connected to the gate terminal of the NMOS transistor 406. The drain terminals of the PMOS transistor 404 and the NMOS transistor 407 are connected to the output stage 402.

  The PMOS transistor 403 and the PMOS transistor 404 are a pair element constituting a differential stage, and constitute a differential transistor pair 408 for inputting a differential signal. The NMOS transistor 406 and the NMOS transistor 407, and the resistance element Reference numeral 410 and resistance element 411 are also pair elements constituting a differential stage, and constitute a current mirror circuit 409 serving as an active load of the differential transistor pair 408. Note that the ratios of the gate width and gate length of the PMOS transistors 403 and 404 constituting the differential transistor pair 408 are the same, and the gate widths of the NMOS transistors 406 and 407 constituting the current mirror circuit 409 are the same. The gate length ratio is also the same.

Next, the operation of the operational amplifier used in the thus configured photocurrent detection circuit will be described. It is assumed that negative feedback is applied to the operational amplifier 103 through a path (not shown), and the current value of the constant current source 405 is Io. Although the ratio of the gate width (W) and the gate length (L) of the NMOS transistor 406 and the NMOS transistor 407 constituting the current mirror circuit 409 is the same, the resistance values of the resistance element 410 and the resistance element 411 are R1 and R2, respectively. since different gate of the NMOS transistor 406 - a value different from the source voltage V GS407 - gate-source voltage V GS406 and the NMOS transistor 407. Therefore, the drain currents of the NMOS transistor 406 and the NMOS transistor 407, that is, the drain currents of the PMOS transistor 403 and the PMOS transistor 404 have different values. If the drain current of the PMOS transistor 403 is I1 and the drain current of the PMOS transistor 404 is I2, the ratio of the gate width (W) to the gate length (L) of the PMOS transistors 403 and 404 is the same. When the gate width and the gate length of the transistor 404 are W and L, respectively, the offset voltage Voff of the operational amplifier 103 is as shown in the following equation (13):
Voff = Vin -- Vin + = V GS403 -V GS404
= {√ (2 / k · L / W · I1) + V th }
− {√ (2 / k · L / W · I2) + V th }
= √ (2 / k · L / W) (√I1-√I2) (13)
It becomes. However, since the drain currents I1 and I2 are supplied from the constant current source 405, I1 + I2 = Io.

  As described above, the resistance values of the resistance element 410 and the resistance element 411 constituting the current mirror circuit 409 in the differential stage 401 are set to different values, and the current mirror ratio is changed, that is, the pair elements constituting the differential stage. Thus, the offset voltage of the operational amplifier 103 is generated and the bias voltage to the photodiode can be set from a very small value.

  In each configuration example of the operational amplifier of the above-described embodiment, the gate width of the MOS transistor constituting the current mirror circuit is changed by changing n which is a ratio of the gate width to the gate length of the differential MOS transistor pair. By changing the current mirror ratio by changing the gate length ratio W / L, or by setting the resistance values of the two resistance elements constituting the current mirror circuit to different values and changing the current mirror ratio, the differential The paired characteristics of the stage are broken to generate the offset voltage of the operational amplifier, but the paired characteristics of these paired elements are broken in a plurality of paired elements to generate the offset voltage of the operational amplifier. May be.

(Example 2)
Next, Example 2 will be described. FIG. 5 is a circuit configuration diagram showing Embodiment 2 of the photocurrent detection circuit according to the present invention. As shown in FIG. 5, in the photocurrent detection circuit 501 according to this embodiment, an anode terminal and a cathode terminal of a photodiode 502 for converting an optical signal into a current signal are an inverting input terminal of an operational amplifier 503 and a constant voltage source. And 504 are connected to the non-inverting input terminal. The inverting input terminal of the operational amplifier 503 is connected to one end of an integrating capacitor 505 that stores the photocurrent from the photodiode 502 and one end of an analog switch 506 that resets the integrating capacitor 505. The output terminal is configured by connecting the other terminal of the capacitor 505, the other terminal of the analog switch 506, and a signal output terminal 507. The operational amplifier 503 includes an offset voltage adjusting circuit 508 that adjusts the offset voltage Voff between the inverting input terminal and the non-inverting input terminal.

The photocurrent detection circuit 501 configured in this manner operates in the same manner as the photocurrent detection circuit 101 according to the first embodiment described above. When the analog switch 506 is opened and the time T has elapsed, the signal output terminal 507 Is expressed by the following equation (14):
Vout = Er + Voff + (Ip + Id) T / Cint (14)
The voltage signal Vout is output. Here, Cint is the capacitance value of the integrating capacitor 505.

  In the photocurrent detection circuit configured in this way, the offset voltage adjustment circuit 507 can arbitrarily adjust the offset voltage even after the circuit is manufactured, so that the generation of dark current is always minimized in the photodiode. The photodiode can be optimally biased, and a stable photocurrent with an excellent SN ratio can be detected.

  Next, an example of a specific configuration of the operational amplifier 503 used in the photocurrent detection circuit 501 will be described with reference to FIG. An operational amplifier 503 according to this configuration example includes a differential stage 601 and an output stage 602 which is an inverting amplifier. In the differential stage 601, the PMOS transistors 603 and 604 have their source terminals connected in common, and the common source terminal is connected to a constant current source 605 that supplies an operating current. The drain terminal of the PMOS transistor 603 is connected to the drain terminal, the source terminal is connected to the other end of the resistance element 610 whose one end is grounded, and the drain terminal is connected to the drain of the PMOS transistor 604. The gate terminal of the NMOS transistor 607 is connected in common to the NMOS transistor 607 to which the other end of the resistance element 611 having one end grounded is connected to the source terminal, and the drain terminal of the NMOS transistor 606 is connected to the source terminal. The gate terminal of the NMOS transistor 606 is connected. Each of the source terminals of the NMOS transistor 606 and the NMOS transistor 607 is connected to each of the variable resistance element 612 and the variable resistance element 613 having one end connected in common and a constant voltage source 614 connected to the common connection point. The other terminals are connected to each other.

  The PMOS transistor 603 and the PMOS transistor 604 constitute a differential transistor pair 608 for inputting a differential signal. The NMOS transistor 606 and the NMOS transistor 607, and the resistance element 610 and the resistance element 611 are included in the differential transistor. A current mirror circuit 609 serving as an active load of the pair 608 is configured, and the variable resistance element 612, the variable resistance element 613, and the constant voltage source 614 are generated between the inverting input terminal and the non-inverting input terminal of the operational amplifier 601. An offset voltage adjustment circuit 615 that adjusts the offset voltage is configured. Note that the ratio of the gate width to the gate length of the PMOS transistor 603 and the PMOS transistor 604 constituting the differential transistor pair 608 is the same.

Next, the operation of the operational amplifier used in the thus configured photocurrent detection circuit will be described. It is assumed that negative feedback is applied to the operational amplifier 503 through a path (not shown) and a current Io is supplied from the constant current source 605. In FIG. 6, since a voltage is applied from a constant voltage source 614 to a common connection point (point A in the figure) between the variable resistance element 612 and the variable resistance element 613, the resistance of the variable resistance element 612 and the variable resistance element 613 When the value is set to a different value by means not shown, due to the potential drop due to the resistance element, the potential at the connection point between the resistance element 610 and the variable resistance element 612, and the potential at the connection point between the resistance element 611 and the variable resistance element 613, the gate of the NMOS transistor 606 - a value different from the source voltage V GS607 - gate-source voltage V GS606 and the NMOS transistor 607. Therefore, the drain currents of the NMOS transistor 606 and the NMOS transistor 607, that is, the drain currents of the PMOS transistor 603 and the PMOS transistor 604 have different values.

When the drain current of the PMOS transistor 603 is I3 and the drain current of the PMOS transistor 604 is I4, the ratio of the gate width (W) to the gate length (L) of the PMOS transistors 603 and 604 is the same. Assuming that the gate width and gate length of the PMOS transistor 604 are W and L, respectively, the offset voltage Voff of the operational amplifier 503 is expressed by the following equation (15):
Voff = Vin -- Vin + = V GS603 -V GS604
= {√ (2 / k · L / W · I3) + V th }
− {√ (2 / k · L / W · I4) + V th }
= √ (2 / k · L / W) (√I3-√I4) (15)
It becomes. However, since the drain currents I3 and I4 are supplied from the constant current source 605, I3 + I4 = Io.

  Thus, the current mirror circuit 609 in the differential stage 601 is provided with the offset voltage adjustment circuit 615 including the variable resistance element 612, the variable resistance element 613, and the constant voltage source 614, and the variable resistance elements 612, 613 are adjusted. Can change the current mirror ratio of the current mirror circuit 609, thereby causing the differential stage 601 to be unbalanced and generating the offset voltage of the operational amplifier 503. Even after the photocurrent detection circuit is manufactured, The bias voltage to the photodiode can be easily set from a minute value.

(Example 3)
Next, Example 3 will be described. FIG. 7 is a circuit configuration diagram showing Embodiment 3 of the photocurrent detection circuit according to the present invention. As shown in FIG. 7, in the photocurrent detection circuit 701 according to this embodiment, a cathode terminal of a photodiode 702 for converting an optical signal into a current signal is connected to an inverting input terminal of an operational amplifier 703, and the operational amplifier 703 One end of an integration capacitor 704 that stores the photocurrent from the photodiode 702 and one end of an analog switch 705 that resets the integration capacitor 704 are connected to the inverting input terminal of the operational amplifier 703, and the integration terminal is connected to the output terminal of the operational amplifier 703. The other terminal of the capacitor 704, the other terminal of the analog switch 705, and the signal output terminal 706 are connected. A voltage source 707 and one end of a resistance element 708 are connected to the non-inverting input terminal of the operational amplifier 703. The other terminal of the resistor element 708 is connected to a resistor element 709 whose one end is grounded and an anode terminal of the photodiode 702 via a buffer amplifier 710.

Next, regarding the operation of the photocurrent detection circuit 701 configured as described above, the bias voltage applied to the photodiode will be described first. In FIG. 7, the voltage Er 3 of the voltage source 707 is applied to the non-inverting input terminal of the operational amplifier 703. Therefore, a voltage of Er3 is applied to the cathode terminal of the photodiode 702 due to a virtual short circuit of the operational amplifier 703. The potential at the connection point between the resistance elements 708 and 709 is R2 / (R1 + R2) × Er3 due to the voltage division of the voltage source 707 by the resistance element, and this potential is a buffer amplifier 710 having a high input impedance and a low output impedance. Is transmitted to the anode terminal of the photodiode 702. Therefore, the bias voltage Vb given by the following equation (16) is applied to the photodiode 702.
Vb = Er3-R2 / (R1 + R2) .Er3 = R1 / (R1 + R2) .Er3
.... (16)

Next, the signal detection operation of the photocurrent detection circuit according to the third embodiment will be described. Before the photocurrent detection, the analog switch 705 is in a closed state, and the integrating capacitor 704 is in a short circuit state. At this time, the voltage output from the output terminal 706 of the photocurrent detection circuit 701 is such that the operational amplifier 703 operates as a voltage follower, and the voltage source 707 is connected to the non-inverting input terminal of the operational amplifier 703. The output voltage Vout is expressed by the following equation (17):
Vout = Er3 (17)
It becomes.

Next, when the analog switch 705 is opened by a command (not shown), the integrating capacitor 704 is electrically connected between the inverting input terminal and the output terminal of the operational amplifier 703, and the detection of the photocurrent is started. The photocurrent Ip and dark current Id generated by the photodiode 702 flow into the integrating capacitor 704 that is electrically connected, and are stored as charges, and a voltage proportional to the amount of charges is output. That is, when the analog switch 705 is opened and the time T has elapsed, the signal output terminal 706 is expressed by the following equation (18):
Vout = Er3 + (Ip + Id) T / Cint (18)
The voltage signal Vout is output. Here, Cint is the capacitance value of the integrating capacitor 704.

  In the photocurrent detection circuit 701 configured as described above, the bias voltage Vb to the photodiode is determined by the voltage source 707, the resistance element 708, and the resistance element 709 as shown in the equation (16), so that an error is generated. A low-precision and high-accuracy bias voltage can be set. This makes it possible to optimally bias so that the generation of dark current from the photodiode is minimized, so that a stable photocurrent with an excellent SN ratio can be detected. Further, since the reference voltage of the output signal is the voltage Er3 of the voltage source 707, the dynamic range and offset level of the output signal can be set optimally and easily.

  Note that the resistance element 708 in the photocurrent detection circuit 701 shown in FIG. 7 may be replaced with a variable resistance element 808 as shown in FIG. In the photocurrent detection circuit 801 configured in this way, the bias voltage to the photodiode 702 can be arbitrarily set by adjusting the value of the variable resistance element 808, and thus the photocurrent detection circuit was manufactured. Even later, it is possible to easily optimize the bias voltage to the photodiode, further suppress the generation of dark current, and detect a stable photocurrent with an excellent SN ratio.

Example 4
Next, Example 4 will be described. FIG. 9 is a circuit configuration diagram showing Embodiment 4 of the photocurrent detection circuit according to the present invention. In the configuration of the photocurrent detection circuit according to the present embodiment, the voltage source 707 in the third embodiment shown in FIG. 7 is replaced with the temperature proportional voltage source 907 whose temperature coefficient corresponds to the temperature coefficient of the dark current generated by the photodiode 702. It is a replacement.

  In the photocurrent detection circuit 901 configured in this way, the bias voltage applied to the photodiode 702 is made to correspond to the temperature coefficient of the dark current generated by the photodiode, so that the fluctuation of the dark current accompanying the temperature change can be reduced. Since it can suppress, the stable photocurrent which was further excellent in S / N ratio is detectable.

1 is a circuit configuration diagram showing a configuration of Embodiment 1 of a photocurrent detection circuit according to the present invention. FIG. 2 is a circuit configuration diagram illustrating a configuration example of an operational amplifier in the photocurrent detection circuit according to the first embodiment illustrated in FIG. 1. FIG. 6 is a circuit configuration diagram illustrating another configuration example of the operational amplifier in the photocurrent detection circuit according to the first embodiment illustrated in FIG. 1. FIG. 6 is a circuit configuration diagram illustrating still another configuration example of the operational amplifier in the photocurrent detection circuit according to the first embodiment illustrated in FIG. 1. It is a circuit block diagram of the photocurrent detection circuit which concerns on Example 2 of this invention. FIG. 6 is a circuit configuration diagram illustrating a configuration example of an operational amplifier according to the second exemplary embodiment illustrated in FIG. 5. It is a circuit block diagram of the photocurrent detection circuit which concerns on Example 3 of this invention. FIG. 8 is a circuit configuration diagram illustrating a modification of the third embodiment illustrated in FIG. 7. It is a circuit block diagram of the photocurrent detection circuit which concerns on Example 4 of this invention. It is a circuit block diagram which shows the structural example of the conventional photocurrent detection circuit.

Explanation of symbols

101,501,701,801,901 Photocurrent detection circuit
102, 502, 702 Photodiode
103,503,703 operational amplifier
104, 504, 707 Voltage source
105, 505, 704 integrating capacitor
106, 506, 705 analog switch
107, 507, 706 signal output terminals
201, 301, 401, 601 differential stage
202, 302, 402, 602 Output stage
203, 204, 303, 304, 403, 404, 603, 604 PMOS transistors
205, 305, 405, 605 constant current source
206, 207, 306, 307, 406, 407, 606, 607 NMOS transistors
208, 308, 408, 608 differential transistor pairs
209, 309, 409, 609 Current mirror circuit
410,411,610,708,709 resistance element
508 and 615 offset voltage adjustment circuit
612, 613, 808 Variable resistance element
614 constant voltage source
710 buffer amplifier
907 Temperature proportional voltage source

Claims (8)

  1.   One terminal of each of the photodiode, the capacitor, and the analog switch is connected to the photodiode and the inverting input terminal, the other terminal of the photodiode is connected to the non-inverting input terminal, and the output terminal An operational amplifier to which the other terminal of each of the capacitor and the analog switch is connected, a voltage source connected to a non-inverting input terminal of the operational amplifier, and the one terminal and the other terminal of the photodiode And a bias voltage generation circuit for generating a predetermined bias voltage.
  2.   2. The bias voltage generation circuit is configured to generate an offset voltage as the predetermined bias voltage between an inverting input terminal and a non-inverting input terminal of the operational amplifier. Such a photocurrent detection circuit.
  3.   The operational amplifier includes a first MOS transistor pair to which the inverting input terminal and the non-inverting input terminal are respectively connected, and a second MOS that constitutes a current mirror circuit serving as an active load for the first MOS transistor pair. The bias voltage generation circuit includes at least one of the first MOS transistor pair or the second MOS transistor pair, and the gate width (W) and gate length (W) of the paired MOS transistors. 3. The photocurrent detection circuit according to claim 2, wherein the offset voltage is generated by changing a ratio (W / L) to L).
  4.   The operational amplifier includes a first MOS transistor pair to which the inverting input terminal and the non-inverting input terminal are connected, and a second MOS transistor constituting a current mirror circuit serving as an active load for the first transistor pair. And a first and second resistance elements connected to the source terminals of the second MOS transistor pair, respectively, and the bias voltage generation circuit includes the first resistance element and the second resistance element. 3. The photocurrent detection circuit according to claim 2, wherein the offset voltage is generated by making a resistance value different from that of the element.
  5.   The photocurrent detection circuit according to claim 1, wherein the bias voltage generation circuit includes an adjustment circuit that adjusts the predetermined bias voltage.
  6.   A photodiode, an operational amplifier in which one terminal of each of the photodiode, capacitor and analog switch is connected to the inverting input terminal, and a voltage source is connected to the non-inverting input terminal, and an output to the other terminal of the photodiode A buffer amplifier to which a terminal is connected, a third resistor having one terminal connected to the voltage source and the other terminal connected to the input terminal of the buffer amplifier, one terminal being grounded, and the other terminal being the first terminal And a fourth resistance element connected to the input terminal of the buffer amplifier, and generates a predetermined bias voltage between the one terminal and the other terminal of the photodiode. And a bias voltage generation circuit.
  7.   7. The photocurrent detection circuit according to claim 6, wherein in the bias voltage generation circuit, the third resistance element is constituted by a variable resistance element.
  8.   8. The photocurrent detection circuit according to claim 6, wherein the voltage source has a temperature coefficient corresponding to a temperature coefficient of dark current generated by the photodiode.
JP2005031365A 2005-02-08 2005-02-08 Photocurrent detection circuit Pending JP2006222495A (en)

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Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS625707A (en) * 1985-07-01 1987-01-12 Oki Electric Ind Co Ltd Photodetecting pre-amplifier circuit
JPS6364405A (en) * 1986-09-05 1988-03-22 Hamamatsu Photonics Kk Photoelectric current amplifier circuit
JPH0279608A (en) * 1988-09-16 1990-03-20 Olympus Optical Co Ltd Offset adjusting device for operational amplifier
JPH03227105A (en) * 1990-01-31 1991-10-08 Sony Corp Offset adjustment circuit for operational amplifier
JPH04174566A (en) * 1990-11-07 1992-06-22 Canon Inc Photodetector
JPH04265004A (en) * 1991-02-20 1992-09-21 Nec Corp Apd bias voltage control circuit
JPH04367108A (en) * 1991-06-14 1992-12-18 Hitachi Cable Ltd Optical receiving circuit
JPH0595232A (en) * 1991-02-22 1993-04-16 Sumitomo Electric Ind Ltd Input circuit
JPH0629754A (en) * 1992-07-07 1994-02-04 Mitsubishi Electric Corp Photoelectric current conversion circuit
JPH10143265A (en) * 1996-11-14 1998-05-29 Nec Corp Band gap reference circuit having start circuit
WO2004043062A1 (en) * 2002-11-07 2004-05-21 Xenics N.V. Read-out circuit for infrared detectors.
JP2005033541A (en) * 2003-07-14 2005-02-03 Yamaha Corp Offset correction method, offset correction circuit, and electronic volume

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS625707A (en) * 1985-07-01 1987-01-12 Oki Electric Ind Co Ltd Photodetecting pre-amplifier circuit
JPS6364405A (en) * 1986-09-05 1988-03-22 Hamamatsu Photonics Kk Photoelectric current amplifier circuit
JPH0279608A (en) * 1988-09-16 1990-03-20 Olympus Optical Co Ltd Offset adjusting device for operational amplifier
JPH03227105A (en) * 1990-01-31 1991-10-08 Sony Corp Offset adjustment circuit for operational amplifier
JPH04174566A (en) * 1990-11-07 1992-06-22 Canon Inc Photodetector
JPH04265004A (en) * 1991-02-20 1992-09-21 Nec Corp Apd bias voltage control circuit
JPH0595232A (en) * 1991-02-22 1993-04-16 Sumitomo Electric Ind Ltd Input circuit
JPH04367108A (en) * 1991-06-14 1992-12-18 Hitachi Cable Ltd Optical receiving circuit
JPH0629754A (en) * 1992-07-07 1994-02-04 Mitsubishi Electric Corp Photoelectric current conversion circuit
JPH10143265A (en) * 1996-11-14 1998-05-29 Nec Corp Band gap reference circuit having start circuit
WO2004043062A1 (en) * 2002-11-07 2004-05-21 Xenics N.V. Read-out circuit for infrared detectors.
JP2005033541A (en) * 2003-07-14 2005-02-03 Yamaha Corp Offset correction method, offset correction circuit, and electronic volume

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