JPH10143184A - Surround circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of D/A converting circuits in the surround circuit which employs an A/D converting circuit, a delaying circuit and D/A converting circuits. SOLUTION: A sampling signal generating circuit 14 generates the sampling signals whose frequency varies in the form of triangular waves. The input signals of an input terminal IN are A/D converted by an A/D converting circuit 11 employing the sampling signals. The output signals of the circuit 11 are delayed in a memory 12. The output signals of the memory 12 are D/A converted in a D/A converting circuit 13 by the sampling signals. Since the frequency of the sampling signals varies, the sampling frequencies of the circuits 11 and 13 corresponding to same digital signals are different. Thus, the frequency of the output signals of the circuit 13 differs from the frequency of the input signals of the circuit 11 and the frequencies of the input signals are spread into various frequencies.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an A / D conversion circuit,
The present invention relates to a surround circuit using a delay circuit and a D / A conversion circuit.

[0002]

2. Description of the Related Art Conventionally, there has been provided an audio reproducing apparatus provided with a mode for reproducing a sound field of a concert hall, a stadium, a church, or the like as a surround so that a listener operates an audio apparatus to obtain a desired surround mode. there were. Basic generation of such a surround is performed by generating a pseudo reflected sound by delaying an audio signal for a predetermined time, and superimposing the audio reproduction sound and the pseudo reflected sound. FIG. 5 is a diagram showing a conventional surround circuit for generating surround.

In FIG. 5, an audio signal is applied to an A / D conversion circuit 1 via an input terminal IN, and is converted into a digital signal by a fixed frequency sampling signal. The digital signal is delayed by the delay circuit 2. The delay circuit 2 delays the digital signal by different delay times. Therefore, the output signal a1 delayed by the first delay time, the output signal a2 delayed by the second delay time longer than the first delay time, and the delay signal by the third delay time longer than the second delay time are output from the delay circuit 2. Output signal a3 and the fourth signal longer than the third delay time.
An output signal a4 delayed by the delay time is generated.

The output signals a1 to a4 of the delay circuit 2 are converted into analog signals at fixed sampling frequencies by first to fourth D / A conversion circuits 4 to 7, respectively. The output signals of the first to fourth D / A conversion circuits 4 to 7 are added to an addition circuit 8
Is added. The output signal of the addition circuit 8 is supplied to the input terminal IN.
Is added to the audio signal from the adder 10 by the adder circuit 10. Therefore, the output signal of the addition circuit 10 is converted into an audio signal,
It becomes a signal on which signals for reproducing various pseudo reflection sounds are superimposed.

[0005]

However, in the circuit shown in FIG. 5, a large number of output signals having different delay times are generated from the delay circuit 2 in order to generate various pseudo reflected sounds. A large number of D /
There is a problem that an A conversion circuit must be used. Therefore, there is a problem that the circuit configuration becomes complicated and the circuit scale becomes large.

[0006]

SUMMARY OF THE INVENTION The present invention provides an A / D conversion circuit for converting an analog signal into a digital signal,
A delay circuit for delaying an output digital signal of the D conversion circuit;
A surround circuit comprising: a D / A conversion circuit that converts an output digital signal of the delay circuit into an analog signal; and a sampling signal for sampling the A / D conversion circuit and the D / A conversion circuit. A sampling signal generation circuit for changing the frequency of the sampling signal over time is provided.

The delay circuit generates an address signal for writing and reading in response to the sampling signal, and outputs a digital signal output from the A / D conversion circuit in response to the address signal. And a memory for writing or reading. Further, the delay circuit includes a shift register that sequentially shifts an output signal of the A / D conversion circuit using the sampling signal as a clock.

Still further, the sampling signal generating circuit is characterized in that the frequency of the sampling signal is repeatedly changed in a rising direction and a falling direction within a predetermined frequency range. Still further, the sampling signal generation circuit randomly changes the frequency of the sampling signal.

According to the present invention, in the A / D conversion circuit, an input signal is converted into a digital signal by a sampling signal of a certain frequency, and while the output signal of the A / D conversion circuit is delayed by the delay circuit, The frequency of the sampling signal changes, and the D / A conversion circuit converts the output signal of the delay circuit into an analog signal at a frequency different from the sampling frequency of the A / D conversion circuit. In the same digital signal, the frequency of the sampling signal differs between digital conversion and analog conversion, so that the output frequency of the surround circuit is different from the input frequency of the surround circuit.

[0010]

FIG. 1 is a diagram showing an embodiment of the present invention. Reference numeral 11 denotes an A / D conversion circuit for converting an input audio signal into a digital signal using a sampling signal whose frequency changes with time; Reference numeral 12 denotes a memory for storing an output signal of the A / D conversion circuit 11 and constituting a delay circuit. Reference numeral 13 denotes a D / A conversion circuit for converting an output signal of the memory 12 into an analog signal by a sampling signal whose frequency changes with time. , 1
Reference numeral 4 denotes a sampling signal generation circuit that generates a sampling signal whose frequency changes with time, and reference numeral 15 denotes an address signal generation circuit that generates an address signal for writing and reading the memory 12 according to the sampling signal.
Note that, in FIG. 1, the same circuits as those in FIG. 4 are denoted by the same reference numerals.

In FIG. 1, an input audio signal is A
The sampling signal generation circuit 1 in the / D conversion circuit 11
The digital signal is converted into a digital signal c at a sampling frequency determined by the sampling signal b. Since the sampling signal b changes over time, the sampling frequency of the A / D conversion circuit 11 also changes over time. The output digital signal c of the A / D conversion circuit 11 is stored at the address of the memory 12 specified by the write address signal d from the address signal generation circuit 15. Then, the output digital signal is read by the read address signal d from the address signal generation circuit 15. At this time, the sampling frequency differs between when a certain digital signal c is written to the memory 12 and when the same digital signal e is read from the memory 12. That is, the write address and the read address are separated by a predetermined address, and the difference between those addresses is the delay time. Here, the address signal generation circuit 15 generates the address signal d in synchronization with the frequency of the sampling signal b. While the same output digital signal c is stored in the memory 12, the frequency of the sampling signal changes with time, so that the sampling frequency of the memory 12 for writing and reading of the same digital signal differs. Therefore, the generation timings of the write address signal d and the read address signal d for the same digital signal are different.

Thereafter, the output digital signal e from the memory 12 is converted by the D / A conversion circuit 13 into an analog signal f at a sampling frequency determined by the sampling signal b. At this time, since the frequency of the sampling signal b of the digital signal c changes in the memory 12, the output digital signal d of the memory 12 is converted into an analog signal at a sampling frequency different from the sampling frequency of the A / D conversion circuit 11. After that, the output signal f of the D / A conversion circuit 13 is added to the input signal of the input terminal IN by the addition circuit 10.

Next, the state of the input / output signals of the surround circuit of FIG. 1 will be described using specific numerical values. First, the frequency of the sampling signal b from the sampling signal generating circuit 14 is 7.5 MHz and 8.5 MHz as shown in FIG.
The range with z changes with a triangular waveform with a period of 10 Hz.
For example, when the sampling frequency of the A / D conversion circuit 11 is 7.5 MHz, an input signal as shown in FIG.
/ D conversion circuit 11. Then, the input signal is converted into a digital signal c at intervals determined by the dotted line in FIG. Thereafter, the frequency of the sampling signal d changes, and the output signal c of the A / D conversion circuit 11 becomes approximately 7.5 M
The data is written into the memory 12 by a write address signal d synchronized with the sampling signal of Hz. While the output signal c is delayed by the memory 12, the sampling signal b changes from 7.5 MHz to 8.5 MHz. After the delay, the output digital signal e is read from the memory 12 by the read address signal d synchronized with the sampling signal b of approximately 8.5 MHz. Digital signal e
Is read, the sampling frequency of the D / A conversion circuit 13 is 8.5 MHz. Therefore, by converting the output digital signal e into an analog signal, D / A
The output analog signal f of the conversion circuit 13 becomes a signal as shown in FIG. From FIG. 2 (c), the interval for analog conversion is narrower than the interval for digital conversion at 7.5 MHz. That is, after a certain input signal is A / D-converted at a sampling frequency of 7.5 MHz, a corresponding digital signal is D / A-converted at a sampling frequency of 8.5 MHz, so that the input signal at the input terminal IN can be reduced. , D /
The cycle of the analog signal f output from the A conversion circuit 13 becomes shorter, and its frequency becomes higher.

Considering the above analogy, for example, if the input signal IN is A / D at a sampling frequency of 8.5 MHz,
When converted, the corresponding digital signal is D /
When applied to the A conversion circuit 13, the sampling frequency becomes 7.5 MHz. In this case, the sampling interval at the time of D / A conversion is wider than that at the time of A / D conversion.
The output signal f of the A conversion circuit 13 has a longer cycle and a lower frequency than the input signal of the input terminal IN. Thus, when the input signal is applied to the A / D conversion circuit 11,
The frequency of the output analog signal f is higher or lower than that of the same input signal IN depending on whether the sampling frequency changes in the upward direction or the downward direction.

In the above example, the frequency difference of the sampling signal between the analog conversion and the digital conversion corresponding to the same digital signal is 1 MHz. As described above, assuming that the transmission time of the output signal c of the A / D conversion circuit 11 to the D / A conversion circuit 13 takes about half a cycle of the change of the sampling frequency, the sampling frequency at the time of A / D conversion becomes 7 In the case of 0.6 MHz, the sampling frequency at the time of D / A conversion for the same digital signal is 8.4 MHz, and the frequency difference between the sampling signals is 0.8 MHz. Therefore, the sampling interval at the time of D / A conversion is 1
Since the width is wider than when the sampling frequency width is MHz, the period of the output analog signal f is longer than when the sampling frequency difference is 1 MHz. Therefore, one cycle of the output analog signal f corresponding to the input signal IN changes variously depending on the sampling frequency when the input signal IN is applied to the A / D conversion circuit 11, and the output analog signal f
Frequency changes.

Therefore, a certain input signal is supplied to the A / D conversion circuit 1
1, the output signal f of the D / A conversion circuit 13 corresponding to the same input signal depends on the sampling frequency of the A / D conversion or whether the sampling frequency is changing in the rising or falling direction at that time. The frequency changes. For example, when an input signal of a single frequency of 1 KHz as shown in FIG. 3A is applied to the input terminal IN, the output analog signal f of the D / A conversion circuit 13 varies as shown in FIG. The output signal has an appropriate frequency component, and the frequency of 1 KHz is dispersed to other frequencies. By making the frequency change of the sampling signal “b” regular, FIG.
The frequency of the output analog signal f can be distributed symmetrically with respect to the frequency of the input signal as shown in FIG. And the motion distributed in order from the low frequency direction to 1 KHz are alternately repeated and dispersed. This allows
When the output signal of the D / A conversion circuit 13 is superimposed on the input signal of the input terminal IN in the adder circuit 10, the output signal of the adder circuit 10 has a frequency component in addition to the frequency component of the input signal. The frequency component of the input signal at the input terminal IN can be blurred. By blurring the frequency components of the input signal, it is possible to reproduce a state in which the original audio signal and the echo signal are superimposed in a pseudo manner.

FIG. 4 shows another embodiment of the present invention. The difference from FIG. 1 is that an N-stage shift register 16 is used instead of the memory 12 in FIG. FIG.
In the shift register 16, the sampling signal b
Is directly applied as a clock, and data in the shift register 16 is shifted by a sampling signal b. The output signal c of the A / D conversion circuit 11 is taken into the shift register 16 by the sampling signal b, and is shifted in the shift register 16. The shift time of the N-stage shift register 16 is a delay time. Since the frequency of the sampling signal b changes with time, while the output signal c of the A / D conversion circuit 11 is shifted,
The shift speed of the shift register 16 changes every moment. Therefore, the frequency of the sampling signal b differs between when the output signal c of the A / D conversion circuit 11 is applied to the shift register 16 and when the output signal is generated from the shift register 16. Therefore, the sampling frequencies of the A / D conversion circuit 11 and the D / A conversion circuit 13 for the same digital signal are different. Therefore, similarly to FIG. 1, a frequency component other than the frequency component of the input signal of the input terminal IN can be generated at the output terminal of the D / A conversion circuit 13.
Therefore, by relatively blurring the frequency component of the input signal at the input terminal IN, it is possible to reproduce a state in which the original audio signal and the echo signal are superimposed in a pseudo manner.

In FIG. 1, the frequency of the sampling signal from the sampling signal generating circuit 14 is, for example, 7.5 MHz and 8.5 MHz as shown in FIG.
2 is continuously changed, but the present invention is not limited to this, and the frequency of the sampling signal may be changed randomly as shown in FIG. Since the frequency of the sampling signal changes randomly, while the output signal of the A / D conversion circuit 11 is delayed by the memory 12, the sampling frequency at the time of A / D conversion and the time of D / A conversion for the same digital signal varies. And randomly different. When the input signal IN of 1 KHz is applied, the frequency of the output analog signal f is as shown in FIG. 3B, but the dispersed frequencies appear randomly. Therefore, even if the frequency of the sampling signal is changed at random, the frequency component of the input signal at the input terminal IN is applied to the output terminal of the D / A conversion circuit 13 in the same manner as when the frequency of the sampling signal is changed continuously. Besides, frequency components can be generated.

[0019]

According to the present invention, since the frequency of the sampling signal changes with time, while the output signal of the A / D conversion circuit is delayed by the memory, the A / D conversion circuit and the D / A The frequency of the sampling signal with the conversion circuit is different, and output signals having various frequencies can be obtained. When the output signal of the D / A conversion circuit is superimposed on the input signal, the frequency component of the input signal is blurred, and a state in which the original audio signal and the echo signal are superimposed can be reproduced in a pseudo manner. . Therefore, a single D / A conversion circuit can reproduce the sound field in a pseudo manner, and the circuit configuration can be simplified and the circuit scale can be reduced.

If a shift register is used instead of a memory as a delay circuit, a pseudo sound field can be reproduced with a single D / A conversion circuit, and the circuit configuration of the delay circuit can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform chart showing each output signal of the circuit of the present invention.

FIG. 3 is a characteristic diagram showing frequency components of input / output signals of the circuit of FIG. 1;

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 11 A / D conversion circuit 12 Memory 13 D / A conversion circuit 14 Sampling signal generation circuit 15 Address signal generation circuit 16 Shift register

Claims (5)

[Claims] 1. A converter for converting an analog signal into a digital signal
A / D conversion circuit, a delay circuit that delays an output digital signal of the A / D conversion circuit, and a D / A conversion circuit that converts an output digital signal of the delay circuit into an analog signal, A surround circuit comprising: a / D conversion circuit; and a sampling signal generation circuit that generates a sampling signal for sampling by the D / A conversion circuit and that changes a frequency of the sampling signal with time. 2. The delay circuit according to claim 1, wherein the delay circuit generates an address signal for writing and reading in response to the sampling signal, and outputs a digital signal output from the A / D conversion circuit in response to the address signal. 2. The surround circuit according to claim 1, comprising: a memory for writing or reading. 3. The surround circuit according to claim 1, wherein the delay circuit comprises a shift register that sequentially shifts an output digital signal of the A / D conversion circuit using the sampling signal as a clock. 4. The surround according to claim 1, wherein said sampling signal generating circuit alternately and repeatedly changes the frequency of said sampling signal in an ascending direction and a descending direction within a predetermined frequency range. circuit. 5. The surround circuit according to claim 1, wherein said sampling signal generating circuit changes a frequency of said sampling signal at random.