JPH10136405A - Device and method for processing image - Google Patents

Abstract

PROBLEM TO BE SOLVED: To store image data in a small capacity frame memory by thinning 2nd chroma data on the odd-numbered lines of inputted image data for one frame and thinning 1st chroma data on the even-numbered lines. SOLUTION: Concerning image data DI to be inputted for one frame, all the lines have luminance data and 1st and 2nd chroma data. When writing image data D2 in a DRAM 1, the 2nd chroma data are thinned in the odd- numbered lines, the luminance data and the 1st chroma data are written and concerning the even-numbered lines, the luminance data and the 2nd chroma data are written while thinning the 1st chroma data. The image data D2 are written in row addresses different for each line. By thinning the chroma data like that, the amount of data can be reduced without lowering picture quality so much in comparison with the case of thinning the luminance data. Besides, image data can be processed in real time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing technique using a frame memory capable of inputting or outputting an image signal in real time.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing a method for storing image data in a frame memory according to the prior art.

The frame memory is composed of two DRAMs 51 and 52. Each DRAM is a general purpose DRA
M, and has a 512 × 512 address space. The row address is 0 to 511, and the column address is 0 to 511.
511.

[0004] The size of image data differs depending on the standard. One of the image data standards is the VGA standard. VG
The A-standard image data is composed of 640 (horizontal) × 480 (vertical) pixels. Hereinafter, the image data of the VGA standard will be described as an example.

[0005] The DRAMs 51 and 52 can access a plurality of image data at high speed unless the row address is changed. That is, a plurality of image data can be written and read at high speed even if the column address is changed within the same row address.

When receiving image data from a video source and supplying image data to a display device, it is necessary to write or read one line of image data to or from the DRAM within one horizontal scanning period. Therefore, 1
It is necessary to access image data in a line at high speed.

In order to access the same line of image data at high speed, it is necessary to store the same line of image data at the same row address. The image data 53 is 640 ×
It has a size of 480 pixels and has two DRAMs 51 and 52.
Is stored over That is, the image data 53
Are 0 to 479 of the row address and 0 to the column address.
639.

[0008]

The frame memory has two
Composed of two DRAMs 51 and 52, 2 × 512 ×
It has 512 address spaces. The image data 53 is 6
It has 40 × 480 pixels. When the image data 53 is stored in the frame memory, an empty area 54 is created in the frame memory. The free area 54 is a useless area where data is not stored.

If a frame memory having an address space of 640.times.480 is used, no empty area can be formed. However, a DRAM having such an odd size is not general-purpose, and the cost is high.

A general-purpose DRAM is a power of two. If a frame memory is configured using a general-purpose DRAM, the above-mentioned empty area 54 is created. The empty area 54 is a useless area of the memory, and hinders efficient use of the memory.

An object of the present invention is to provide an image processing device capable of efficiently storing image data.

It is another object of the present invention to provide an image processing apparatus capable of storing image data in a small-capacity frame memory.

Another object of the present invention is to provide an image processing method capable of efficiently storing image data.

It is another object of the present invention to provide an image processing method capable of storing image data in a small-capacity frame memory.

[0015]

An image processing apparatus according to a first aspect of the present invention has an input terminal for inputting digital image data in which each line includes luminance data, first chroma data, and second chroma data. A DRAM for storing one frame of image data addressed by a row address and a column address, and thinning out second chroma data for odd lines of one frame of image data input to the input terminal. The luminance data and the first chroma data are used, the first chroma data is thinned out for even lines, and the luminance data and the second chroma data are used.
Writing means for writing the image data to different row addresses of the DRAM for each line.

In one frame of input image data, all lines are composed of luminance data, first chroma data, and second data.
With chroma data. When the image data is written to the DRAM, the second chroma data is decimated and the first chroma data is written for odd lines, and the first chroma data is decimated and the second chroma data is written for even lines. Write chroma data. The image data is written to a different row address for each line. When the chroma data is thinned out, the data amount can be reduced without significantly lowering the image quality as compared with the case where the luminance data is thinned out. Further, by writing the image data to different row addresses for each line, the image data can be processed in real time.

An image processing apparatus according to a second aspect of the present invention is configured to convert one frame of image data including luminance data and first chroma data for odd lines and luminance data and second chroma data for even lines. A DRAM for storing a different row address for each line;
The first or second chroma data read from M
A buffer for storing lines, a buffer writing means for reading out one line of the first chroma data of an odd line or a second chroma data of an even line from the DRAM, and writing the data into the buffer;
From the buffer, reads out the odd-numbered line luminance data and the first chroma data from the buffer, reads out the second chroma data of the even-numbered line adjacent to the odd-numbered line from the buffer, generates new odd-numbered image data, and reads the even-numbered line from the DRAM. Image data generating means for reading out the luminance data and the second chroma data and reading the first chroma data of an odd line adjacent to the even line from the buffer to generate new even line image data.

The DRAM stores odd-numbered line image data including luminance data and first chroma data, and even-numbered line image data including luminance data and second chroma data. Since the odd-numbered lines have only the luminance data and the first chroma data, the second chroma data is interpolated to generate new image data. Even lines are
Since there is only the luminance data and the second chroma data, the first chroma data is interpolated to generate new image data.
Since the chroma data to be interpolated is stored at different row addresses of the DRAM, the chroma data is read out in advance and temporarily stored in a buffer. The luminance data and the first chroma data of the odd line are read from the DRAM, and the second data of the even line adjacent to the odd line is read from the buffer.
Is read to generate new odd-numbered line image data. Further, the luminance data and the second chroma data of the even lines are read from the DRAM, and the first chroma data of the odd lines adjacent to the even lines are read from the buffer to generate new image data of the even lines. By using a buffer, chroma data stored at different row addresses can be interpolated, and new image data can be generated in real time.

An image processing method according to another aspect of the present invention comprises:
Inputting digital image data in which each line includes luminance data, first chroma data and second chroma data, and thinning out the second chroma data for odd lines of the input image data. And using the first chroma data, thinning out the first chroma data for even lines, employing the luminance data and the second chroma data, and writing the image data to different row addresses of the DRAM line by line. .

An image processing method according to another aspect of the present invention comprises:
An image processing method using a DRAM which stores luminance data and first chroma data for odd lines and one frame of image data including luminance data and second chroma data for even lines at different row addresses for each line. Writing the first chroma data of the odd-numbered lines or the second chroma data of the even-numbered lines stored in the DRAM into the buffer before the start of each horizontal scanning period; And the DRAM
From the buffer, and reads out the second chroma data of the even-numbered line adjacent to the odd-numbered line from the buffer to generate new odd-numbered line image data or reads the even-numbered image data from the DRAM. Reading the luminance data and the second chroma data of the line and reading the first chroma data of the odd line adjacent to the even line from the buffer to generate new even line image data.

[0021]

FIG. 1 is a diagram showing the configuration of an image processing apparatus according to an embodiment of the present invention.

The image processing device is a DRAM (frame memory) for storing one frame of digital image data.
1, a buffer 2 for storing chroma (color) data for one horizontal scanning period (hereinafter abbreviated as 1H), and a data format converter 3 for converting a data format.

The image processing apparatus receives the image data D1 from the video source and writes the image data D2 to the DRAM 1. Further, the image processing apparatus reads the image data D3 from the DRAM 1 and supplies the display image data D6 to the display device. The image data D1 and D6 are of a non-interlace type.

The data format conversion section 3 has a 4: 2:
Image data conversion between the 2 format and the 4: 2: 0 format is performed. The format of both formats will be described later with reference to FIGS.

The image data D1 is image data input from the video source to the conversion unit 3, and includes luminance data:
Chroma data: The second chroma data is in 4: 2: 2 format. The image data D6 output from the conversion unit 3 to the display device is also in 4: 2: 2 format. On the other hand, D
The image data stored in the RAM 1 is in 4: 2: 0 format.

The 4: 2: 0 format has a smaller number of data than the 4: 2: 2 format. In the 4: 2: 2 format, as shown in FIG.
Two M are required. On the other hand, if the format is 4: 2: 0, if the data storage method is devised, 5
Only one 12 × 512 DRAM is required. Details will be described later. In this embodiment, the frame memory is stored in one DRA.
An example constituted by M1 will be described.

The conversion unit 3 performs the 4: 2: 2 image data D1
Is converted into 4: 2: 0 image data D2 and written into the DRAM1. Thereafter, the conversion unit 3 reads out the 4: 2: 0 image data D3 stored in the DRAM 1, and reads the 4: 2: 0 image data D3.
The image data is converted into 2: 2 image data D6 and output to a display device.

FIG. 2 is a diagram showing an arrangement of data in 4: 2: 2 format. Image data has only 640 (horizontal) × 480 (vertical) pixels. The first H image data is the image data of the first line. 2nd
The image data of 480H is image data of the second to 480th lines. The image data is from the first H to the fourth H
Line up in order up to 80H.

The first H image data is composed of data of 640 pixels. Specifically, 640 pieces of luminance data Y1 to
Y640 and 640 chroma data Cb1 to Cb32
0, Cr1 to Cr320. However, the blue chroma data Cb and the red chroma data Cr are alternately arranged. That is, Cb1, Cr1, Cb2, Cr2,.
320 and Cr320. The second to 480H image data have the same data configuration as the first H image data.

Y is luminance data, Cb is blue chroma data, and Cr is red chroma data. 4:
In the 2: 2 format, the ratio of the number of data of Y: Cb: Cr is 4: 2: 2.

FIG. 3 is a diagram showing an arrangement of data in 4: 2: 0 format. Image data has only 640 (horizontal) × 480 (vertical) pixels. The image data is arranged in order from 1H to 480H. The arrangement of data is different between the odd lines (1H, 3H,...) And the even lines (2H, 4H,...).

As an example of an odd line, the first H image data will be described. The first H image data is composed of data of 640 pixels. Specifically, 640 luminance data Y1 to Y640 and 320 chroma data Cb1 to Cb
b320. By thinning out the red chroma data Cr1 to Cr320 from the 4: 2: 2 first H image data (FIG. 2), the 4: 2: 0 first H image data can be generated.

As an example of an even-numbered line, the 2H image data will be described. The 2H image data includes data of 640 pixels. Specifically, 640 pieces of luminance data Y1 to Y640 and 320 pieces of chroma data Cr1 to C
r320. By thinning out the blue chroma data Cb1 to Cb320 from the 4: 2: 2 second H image data (FIG. 2), 4: 2: 0 second H image data can be generated.

In the 4: 2: 0 format, one blue chroma data Cb and one red chroma data Cr correspond to four luminance data Y. For example, the first H two image data Y1, Y2 and the second H two image data Y
One blue chroma data C of the 1H for 1 and Y2
b and one red chroma data Cr of the 2H correspond.

FIG. 4 is a diagram showing a method for storing image data in the 4: 2: 0 format (FIG. 3) in the DRAM 1.

The DRAM 1 has a row address of 0 to 51.
The number is up to 1, and the column address is from 0 to 511.
The first H image data is stored at the row address “0”.
Row addresses 2 to 48 are assigned to row addresses "1" to "479", respectively.
0H image data is stored. Row address "480"
To “511” are empty areas.

As shown in FIG. 3, in the 4: 2: 0 format, the arrangement of data is different between odd lines and even lines. The image data of 4: 2: 0 format is stored in DRAM 1
In the DRAM 1, the arrangement of data is different between the odd row address and the even row address.

As an example of an even row address, image data of a row address "0" will be described. In the row address “0”, the first half column addresses “0” to “31”
9 ”stores luminance data Y, and chroma data C is stored in the second half column addresses“ 320 ”to“ 479 ”.

First, the luminance data Y will be described. In the row address “0”, the column addresses “0” to
In “319”, 640 pieces of luminance data Y1 to Y640 are 2
They are stored in byte units as shown in FIG.

FIG. 5 is a three-dimensional view of the DRAM shown in FIG. One luminance Y is one byte (8 bits). Each of the chroma data Cb and Cr is also 1 byte. The DRAM has a 512 × 512 address space, and can store 2 bytes (16 bits) of data at one address.

The first two pieces of luminance data Y1 and Y2 are stored at column address "0", and the next two pieces of luminance data Y3 and Y4 are stored at column address "1". Then, the last two pieces of luminance data Y6 are added to the column address “319”.
39 and Y640 are stored.

Next, the chroma data will be described. In the row address “0”, the column address “320”
To “479”, 320 blue chroma data Cb1 to Cb
b320 is stored in units of 2 bytes as shown in FIG.

The first two pieces of chroma data Cb1 and Cb2 are stored at column address "320", and the last two pieces of chroma data Cb319 and Cb319 are stored at column address "479".
b320 is stored.

Returning to FIG. 4, a row address "1" will be described as an example of an odd row address data arrangement.
In the row address “1”, the luminance data Y1 to Y640 are 2 in the first half column addresses “0” to “319”.
Stored in byte units, the second half column address "32
Red chroma data Cr1 to Cr3 are stored in "0" to "479".
20 is stored in units of 2 bytes.

All image data can be stored in one DRAM (512 × 512) 1. 4: 2:
Two image data require two DRAMs,
If the image data is 4: 2: 0, only one DRAM is required, so that the cost can be reduced.

In FIG. 1, 4: 2: 0 (FIG. 3) image data D2 can be generated by simply thinning out 4: 2: 2 (FIG. 2) input image data D1. Part 4: 2:
If the image data D2 of 0 is stored at the addresses shown in FIGS. 4 and 5, it is possible to process in real time in synchronization with the vertical synchronization signal and the horizontal synchronization signal.

For example, the first H image data is all stored at a row address "0", and the second H image data is all stored at a row address "1". If the image data of the same line is stored at the same row address, the image data can be processed in real time.

On the other hand, 4: 2:
In order to convert the image data D3 of 0 into image data D6 of 4: 2: 2 and supply it to the display device in real time, it is necessary to perform the following control.

FIG. 6 is a circuit diagram of 4: 2: in the DRAM shown in FIG.
FIG. 3 is a diagram schematically illustrating image data of a 0 format.

For convenience of explanation, the image data is hereinafter represented by simple symbols. The luminance data Y1 to Y640 stored in the row address “0” are represented as Y (1), and the blue chroma data Cb1 to Cb320 are represented as Cb (1). Luminance data Y1 to Y6 stored in row address "1"
40 is Y (2), and red chroma data Cb1 to Cb3
20 is represented as Cr (2).

Similarly, assume that the luminance data of the row address “2” is Y (3) and the blue chroma data is Cb (3). It is assumed that the luminance data of the row address “3” is Y (4) and the red chroma data Cr (4). Finally, the row address “47”
The luminance data of 9 "is Y (480), and the red chroma data is Cr (480).

A method of converting image data from 4: 2: 0 format to 4: 2: 2 format will be described using the above simplified symbols. In FIG. 1, the DRAM 1 stores image data of 4: 2: 0. The data format conversion unit 3 performs 4: 2:
The data is converted from 0 to 4: 2: 2 to generate 4: 2: 2 image data D6, which is supplied to the display device.

The conversion method of the image data is different between the odd line and the even line. However, since the previous line does not exist in the first H image data, the interpolation method is different from the others.
The case of the 1H and 3H image data will be described as an example of the odd line, and the case of the 2H and 4H image data will be described as an example of the even line.

The first H image data includes the luminance data Y (1) of the row address “0” and the blue chroma data C.
The red chroma data Cr (2) generated based on b (1) and having the row address “1” is further interpolated.

In the 4: 2: 0 format, since there is only luminance data Y (1) and blue chroma data Cb (1) in the first H, it is necessary to interpolate red chroma data. The red chroma data Cr (2) to be interpolated is the second H image data adjacent to the first H.

The data Y (1) and Cb (1) are stored at the row address "0", but the data Cr (2) is stored at the row address "1". become. Since some time is required for switching the row address, it is difficult to store the first H image data in 1H. Therefore, by using the buffer 2 (FIG. 1) for storing 1H of chroma data, it is possible to store the 1H image data in 1H. Details will be described later with reference to FIG.

The second H image data is composed of the luminance data Y (2) of the row address “1” and the red chroma data C.
The blue chroma data Cb (1) generated based on r (2) and having a row address “0” is further interpolated. The chroma data Cb (1) to be interpolated is the first H image data adjacent to the second H.

The third H image data includes the luminance data Y (3) of the row address “2” and the blue chroma data C.
The red chroma data Cr (2) generated based on b (3) and having the row address “1” is further interpolated. The interpolated chroma data Cr (2) is the second H image data adjacent to the third H.

The fourth H image data includes the luminance data Y (4) of the row address “3” and the red chroma data C
The blue chroma data Cb (3) generated based on r (4) and having the row address “2” is further interpolated. The interpolated chroma data Cb (3) is the third H image data adjacent to the fourth H.

FIG. 7 is a timing chart for reading out the image data D3 from the DRAM 1 and generating 4: 2: 2 image data D6. VSYNC is a vertical synchronizing signal, and HSYNC is a horizontal synchronizing signal. The DRAM 1 stores 4: 2: 0 image data.

First, a method of generating the first H image data D6 will be described. The conversion unit 3 converts the data Cr from the row address “1” of the DRAM 1 during the VSYNC blanking period to the data Cr.
(2) is read out as image data D3 and written into buffer 2 as image data D4.

Next, at the same time as the start of the first H, the conversion unit 3 changes the data Y from the row address “0” of the DRAM 1 to the data Y.
(1) and Cb (1) are read as image data D3,
It is output to the display device as image data D6. Further, in parallel with this, data Cr (2)
Is read as image data D5, and is read out as image data D5.
Output to the display device as 6.

The image data D6 includes data Y (1), Cb (1), and Cr (2), and falls in the first H period of HSYNC. Data Y (1) and Cb (1) are converted to DRAM
1 is read from the row address “0” and the data Cr
By reading (2) from the buffer 2, real-time processing becomes possible. The image data D6 is an arrangement of data in the 4: 2: 2 format shown in FIG.

Note that the image data D from the DRAM 1
The data Cb (1) read as 3 is output to the display device as image data D6, and is written into the buffer 2 as image data D4. This data Cb
(1) is used as interpolation data when generating second H image data described later.

Next, a method of generating the second H image data D6 will be described. The conversion unit 3 outputs the DR at the same time as the start of the second H.
From the row address “1” of AM1 to data Y (2) and Cr
(2) is read out as image data D3 and is output to the display device as image data D6. Further, in parallel with this, the data Cb (1) is read from the buffer 2 as image data D5, and is output to the display device as image data D6. The image data D6 falls within the second H period of HSYNC.

The data Cr (2) read out from the DRAM 1 as image data D3 is output to the display device as image data D6 and written into the buffer 2 as image data D4. The data Cr (2) is
It is used as interpolation data when generating 3H image data described later.

Next, a method of generating the third H image data D6 will be described. The conversion unit 3 outputs the DR at the same time as the start of the third H.
From the row address "2" of AM1, data Y (3) and Cb
(3) is read out as image data D3 and output to the display device as image data D6. Further, in parallel with this, the data Cr (2) is read from the buffer 2 as image data D5, and is output to the display device as image data D6. The image data D6 falls in the third H period of HSYNC.

The data Cb (3) read out from the DRAM 1 as image data D3 is output to the display device as image data D6 and written into the buffer 2 as image data D4. The data Cb (3) is
It is used as interpolation data when generating the 4H image data. Hereinafter, similarly, the image data D6 from the 4H to the 480H is generated.

In the 4: 2: 0 format, for example, row address “0” has only luminance data Y and blue chroma data Cb. The red chroma data to be interpolated exists at the row address “1”. To read three types of data over different row addresses, it is necessary to take into account the delay in row address switching time. The buffer 2 is used to absorb this delay. By storing interpolation data in the buffer 2 in advance, the image data D
6 can be output to a display device in real time.

The buffer 2 only needs to have a capacity enough to store 1H chroma data in 4: 2: 0 format. In the case of the present embodiment, the buffer 2 only needs to have a capacity of 320 bytes or more to store 320 pieces of chroma data.

Also, by converting the image data of the 4: 2: 2 format into the 4: 2: 0 format, 1
Image data can be stored in one DRAM (512 × 512). Storing 4: 2: 2 format image data requires two DRAMs.
To store the image data in the 2: 0 format, only one DRAM is required. Since only a small-capacity DRAM is required, miniaturization and cost reduction can be achieved.

Further, when image data is stored in the DRAM in 4: 2: 0 format, it can be converted to 4: 2: 2 image data in real time by using a buffer and output to a display device.

In this embodiment, when converting from 4: 2: 2 format to 4: 2: 0 format, red chroma data is thinned out for odd lines, luminance data and blue chroma data are adopted, and even lines are Has shown an example in which blue chroma data is thinned out and luminance data and red chroma data are adopted, but the present invention is not limited to this. For example,
The odd-numbered lines may employ thinned luminance data and red chroma data for blue chroma data, and the even-numbered lines may employ thinned luminance data and blue chroma data for red chroma data.

The color image is not limited to the YCbCr system. For example, another system such as an RGB system may be used. However, since the chroma data is less important than the luminance data, it is preferable to thin out the chroma data.
The color image is preferably applied to a format including luminance data and chroma data.

Further, the size of the image data is 640 × 4
80, the size of the DRAM is not limited to 512 × 512. Other sizes may be used. The data format is not limited to 4: 2: 2 and 4: 2: 0,
Other formats such as 4: 1: 1 may be used.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0077]

As described above, according to the present invention,
Since the image data is written to the DRAM by thinning out the chroma data, the data amount can be reduced without significantly lowering the image quality as compared with the case where the luminance data is thinned out. If the data amount is small, the capacity of the DRAM can be reduced. Further, by writing the image data to different row addresses for each line, the image data can be processed in real time.

Further, the chroma data to be interpolated is DR data
Since the chroma data is stored in the buffer at different row addresses of the AM, new image data can be generated in real time by temporarily storing the chroma data in the buffer.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing an arrangement of data in 4: 2: 2 format.

FIG. 3 is a diagram showing an arrangement of data in 4: 2: 0 format.

FIG. 4: DRA of 4: 2: 0 format image data
FIG. 9 is a diagram illustrating a method of storing data in M.

FIG. 5 is a diagram three-dimensionally showing the DRAM shown in FIG. 4;

6 is a diagram schematically showing image data of 4: 2: 0 format in the DRAM shown in FIG. 4;

FIG. 7 is a timing chart for reading 4: 2: 0 image data from a DRAM and generating 4: 2: 2 image data.

FIG. 8 is a diagram showing a method for storing image data in a frame memory according to the related art.

[Explanation of symbols]

 Reference Signs List 1 DRAM 2 Chroma data buffer 3 Data format converter 51, 52 DRAM 53 Image data 54 Free space

Claims (6)

[Claims] 1. An input terminal for inputting digital image data in which each line includes luminance data, first chroma data and second chroma data, and an address designated by a row address and a column address. DRAM for storage
In one frame of image data input to the input terminal, the second chroma data is thinned out for odd lines, luminance data and first chroma data are adopted, and the first chroma data is used for even lines. An image processing apparatus that employs thinning luminance data and second chroma data, and has a writing unit that writes the image data to different row addresses of the DRAM for each line. 2. A buffer for storing one line of the first or second chroma data read from the DRAM, and a first chroma data of an odd line or a second chroma of an even line from the DRAM. Buffer writing means for reading one line of data and writing the data to the buffer; and reading the luminance data and the first chroma data of the odd line from the DRAM and the second chroma of the even line adjacent to the odd line from the buffer. Read out data to generate new odd-numbered line image data,
Image data generating means for reading luminance data and second chroma data of an even line from the buffer and reading first chroma data of an odd line adjacent to the even line from the buffer to generate new even line image data. The image processing device according to claim 1. 3. An odd-numbered line includes luminance data and first data.
A DRAM that stores one frame of image data including luminance data and second chroma data at different row addresses for each line for even-numbered lines including the first and second chroma data read from the DRAM. A buffer for storing one line of the first chroma data of the odd-numbered line or the second chroma data of the even-numbered line from the DRAM, and a buffer writing unit for writing the same into the buffer; Reading the odd line luminance data and the first chroma data and reading the second chroma data of the even line adjacent to the odd line from the buffer to generate new odd line image data;
Image data generating means for reading luminance data and second chroma data of an even line from the buffer and reading first chroma data of an odd line adjacent to the even line from the buffer to generate new even line image data. Image processing apparatus. 4. A step of inputting digital image data in which each line includes luminance data, first chroma data, and second chroma data; and, for odd lines of the input image data, a second chroma signal. For data, thinned-out luminance data and first chroma data are used. For even lines, the first chroma data is used for thinned-out luminance data and second chroma data. The image data is stored in different row addresses of the DRAM for each line. An image processing method including a writing step. 5. A step of writing one line of the first chroma data of the odd line or the second chroma data of the even line stored in the DRAM into the buffer before the start of each horizontal scanning period; Within the horizontal scanning period, the luminance data and the first chroma data of the odd line are read from the DRAM, and the second chroma data of the even line adjacent to the odd line is read from the buffer, and the image data of the new odd line is read. Alternatively, the luminance data and the second chroma data of the even line are read from the DRAM, and the first chroma data of the odd line adjacent to the even line is read from the buffer to generate new even line image data. 5. The image processing method according to claim 4, comprising the steps of: 6. An odd-numbered line includes luminance data and first data.
An image processing method using a DRAM for storing one frame of image data including luminance data and second chroma data at different row addresses for each line for even-numbered lines including The first chroma data of an odd line or the second chroma data of an even line previously stored in the DRAM.
Writing the one line of chroma data into the buffer, reading the odd line luminance data and the first chroma data from the DRAM during each horizontal scanning period, and reading the even line adjacent to the odd line from the buffer. The second chroma data is read to generate new odd line image data, or the even line luminance data and the second chroma data are read from the DRAM, and the first odd line adjacent to the even line is read from the buffer. And reading out the chroma data of the image data to generate image data of a new even line.