JPH10135826A - Pll frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a locking up time by allowing a phase comparing means to compare the phase of a feedback signal from a frequency divider with the phase of a reference signal from a reference oscillator with a second timing different from a first timing so as to generate a difference signal. SOLUTION: Delay circuits 61 to 64 generate the plural reference signals RF1 to RF4 of mutually different phase in response to a reference signal from the reference oscillator 1. Namely the delay circuit 61 gives the reference signal RF as it is to a phase comparator 31 as a reference signal RF1 without delaying. The delay circuit 62 delays the signal RF by 1/4 period and gives it as a reference signal RF 2 to the comparator 31. The delay circuits 63 and 64 process similarly. Phase comparators 31 to 34 compare the phases and the frequencies of feedback signals FB1 to FB4 from programmable frequency dividers 21 to 24 with the phases and the frequencies of the signals RF1 to RF4 and generate differential signals ER1 to ER4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer, and more particularly, to a PLL frequency synthesizer that generates an output signal phase-locked to a reference signal.

[0002]

2. Description of the Related Art Referring to FIG. 11, a conventional PLL frequency synthesizer used for a radio receiver or the like is for generating an output signal CV phase-locked to a reference signal RF. Reference oscillator 1 that generates
And a programmable frequency divider 2 for dividing the output signal CV to generate a feedback signal FB, and comparing the phase and frequency of the feedback signal FB with the phase and frequency of the reference signal RF to generate an error signal ER. And a low-pass filter (LP) that generates a control voltage CN in response to the error signal ER.
F) 4 and a voltage controlled oscillator (VCO) 5 that generates an output signal CV in response to the control voltage CN. Such a PLL frequency synthesizer is described in “SANYO TECHNICAL RE
VIEW ", VOL. 10, NO. 1, FEB. 1978, page 32, FIG.

Here, the reference frequency fr of the reference signal RF
Is set basically the same as the inter-station frequency determined for each band. That is, the reference frequency fr is not usually set higher than the inter-station frequency, and is determined to a constant value in consideration of the channel space.

The PLL frequency synthesizer includes a prescaler system, a pulse swallow system, a fractional frequency division system, and the like, in addition to the typical ones described above. In the prescaler type PLL frequency synthesizer, the reference frequency is set lower than the inter-station frequency. Pulse swallow P
In the LL frequency synthesizer, the reference frequency is set basically the same as the inter-station frequency. In the PLL frequency synthesizer of the fractional frequency division system, the reference frequency is set higher than the inter-station frequency.

[0005] The prescaler method is described in "SANYO TECHNI
CAL REVIEW, page 2, Figure 2, and by Toshiyuki Ozawa,
"PLL Frequency Synthesizer / Circuit Design Method", pages 74 to 75, published by Sogo Denshi Shuppan, July 10, 1994.
Page. The pulse swallow method is described in “PL
L Frequency Synthesizer / Circuit Design Method ", pp. 111-112. Fractional frequency division method is Ken Mais
on, Translated by Toshihiro Tada, Philips Semiconductors Applicati
on Note, "A Frequency Synthesizer UMA1005 Designer's Guide", published on November 5, 1992, pp. 7-10.

[0006]

It is desirable that the lock-up time of the above-mentioned PLL frequency synthesizer be short, but the relationship between the reference frequency fr and the lock-up time is theoretically and unitarily determined if it is designed optimally. It will be. As a method of shortening the lock-up time, a method of switching the time constant of the LPF 4 is disclosed on page 217 of the above-mentioned "PLL frequency synthesizer / circuit design method".

In the above-mentioned fractional frequency division method, the reference frequency can be set higher than the inter-station frequency. However, since a phase error always occurs, a compensation output for the phase error is required. Has the problem that various adjustments are required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has been developed to solve the above-mentioned problems.
It is an object to provide an L frequency synthesizer.

[0009]

According to one aspect of the present invention, a PLL frequency synthesizer for generating an output signal phase-locked to a reference signal includes a reference oscillator for generating a reference signal, and a frequency divider for dividing the output signal. A frequency divider for generating a feedback signal, a phase comparator for comparing the phase of the feedback signal from the frequency divider with the phase of the reference signal from the reference oscillator at a first timing, and generating an error signal; A low-pass filter that generates a control voltage in response to an error signal from the means;
A voltage-controlled oscillator that generates an output signal in response to a control voltage from the low-pass filter. The phase comparing means further generates an error signal by comparing the phase of the feedback signal from the frequency divider with the phase of the reference signal from the reference oscillator at a second timing different from the first timing.

According to another aspect of the present invention, the first
Generating an output signal phase-locked to a reference signal
A frequency synthesizer comprising: a reference oscillator for generating the first reference signal; and reference signal generating means for generating a plurality of second reference signals having different phases in response to the first reference signal from the reference oscillator. A frequency divider that divides the output signal to generate a plurality of feedback signals respectively corresponding to the plurality of second reference signals, and calculates a phase of the plurality of feedback signals from the frequency divider by the reference signal generation. Phase comparing means for generating an error signal by comparing the phases of the plurality of second reference signals from the means, a low-pass filter for generating a control voltage in response to the error signal from the phase comparing means, and the low-pass filter And a voltage-controlled oscillator that generates the output signal in response to a control voltage from

According to another aspect of the present invention, the first
Generating an output signal phase-locked to a reference signal
A frequency synthesizer for generating a first reference signal; a reference signal generating means for generating a plurality of second reference signals having phases different from each other in response to the first reference signal from the reference oscillator; A plurality of frequency dividers provided corresponding to the second reference signal, each of which divides an output signal to generate a feedback signal, and a phase of the feedback signal from the plurality of frequency dividers is used as a reference signal generating means. From the plurality of second reference signals to generate an error signal, a low-pass filter generating a control voltage in response to the error signal from the phase comparison means, and a control from the low-pass filter. A voltage controlled oscillator for generating an output signal in response to a voltage.

Preferably, the phase comparing means is provided in correspondence with the plurality of second reference signals, and compares the phase of the corresponding feedback signal with the phase of the corresponding second reference signal to generate an error signal. A plurality of phase comparators are generated.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 and FIG. 2 are views showing a first embodiment of the present invention.

Referring to FIG. 1, a PLL frequency synthesizer according to an embodiment of the present invention comprises a reference oscillator 1, a plurality of programmable frequency dividers 21 to 24, a plurality of phase comparators 31 to 34, a low-pass filter. (LPF) 4;
Voltage controlled oscillator (VCO) 5 and delay circuits 61 to 64
, Gate circuits 71 to 74, and a central processing unit (CP
U) 8).

The reference oscillator 1 generates a reference signal RF. The delay circuits 61 to 64 respond to the reference signal RF from the reference oscillator 1 and provide a plurality of reference signals R having different phases from each other.
Generate F1 to RF4.

More specifically, the delay circuit 61 does not delay the reference signal RF and does not delay the reference signal RF1.
To the phase comparator 31. Therefore, delay circuit 61 in this embodiment functions as a simple gate circuit. The delay circuit 62 delays the reference signal RF by １ ／ cycle, and supplies the same to the phase comparator 32 as the reference signal RF2. The delay circuit 63 reduces the reference signal RF by half.
The signal is delayed by a period, and is supplied to the phase comparator 33 as the reference signal RF3. The delay circuit 64 sets the reference signal RF to 3
The signal is delayed by / 4 cycle, and is supplied to the phase comparator 34 as the reference signal RF4.

The programmable frequency dividers 21 to 24 divide the frequency of the output signal CV from the voltage controlled oscillator 5 to provide a feedback signal FV.
B1 to FB4 are generated. The phase comparators 31 to 34 determine the phase and frequency of the feedback signals FB1 to FB4 based on the reference signal R.
The error signal E is compared with the phase and frequency of F1 to RF4.
R1 to ER4 are generated.

More specifically, the phase comparator 31 compares the phase and frequency of the feedback signal FB1 from the programmable frequency divider 21 with the phase and frequency of the reference signal RF1 from the delay circuit 61 to generate the error signal ER1. Occur. The phase comparator 32 compares the phase and frequency of the feedback signal FB2 from the programmable frequency divider 22 with the phase and frequency of the reference signal RF2 from the delay circuit 62, and outputs an error signal ER.
2 is generated. The phase comparator 33 compares the phase and frequency of the feedback signal FB3 from the programmable frequency divider 23 with the phase and frequency of the reference signal RF3 from the delay circuit 63 to generate an error signal ER3. The phase comparator 34
An error signal ER4 is generated by comparing the phase and frequency of the feedback signal FB4 from the programmable frequency divider 24 with the phase and frequency of the reference signal RF4 from the delay circuit 64.

The LPF 4 generates a control voltage CN in response to error signals ER1 to ER4 from the phase comparators 31 to 34. The voltage controlled oscillator 5 receives the control voltage C from the LPF 4
An output signal CV is generated in response to N. Since the LPF 4 receives error signals ER1 to ER4 that are four times the normal, the control voltage CN is set to １ ／ of the normal. Alternatively, the error signals ER1 to ER4 may be set to 1/4 of the normal values instead.

The CPU 8 controls the delay circuits 61 to 64 and the gate circuits 71 to 74. Gate circuits 71 to 7
Numeral 4 is for synchronizing the frequency division start timings of the programmable frequency dividers 21 to 24 with the respective delay circuits 61 to 64, and operates only for the first cycle of the reference signal RF. More specifically, under the control of the CPU 8, the gate circuit 71 is turned on in synchronization with the reference signal RF from the reference oscillator 1, that is, in synchronization with the delay circuit 61. Then, the gate circuit 72 is turned on with a delay of １ ／ cycle from the gate circuit 71. The gate circuit 73 is 1/1 of the gate circuit 72.
It turns on with a delay of four cycles. The gate circuit 74 is turned on with a delay of １ ／ cycle from the gate circuit 73. Gate circuits 71 to 74 are continuously on in the second and subsequent cycles.

Next, the operation of the PLL frequency synthesizer configured as described above will be described with reference to the timing chart of FIG.

The reference oscillator 1 has a reference frequency fr (period T
ref = 1 / fr). The reference signal RF is passed through the delay circuit 61 as it is to the phase comparator 31 as the reference signal RF1 shown in FIG. The reference signal RF is also converted by the delay circuit 62 to 1 /
The signal is delayed by four periods (Tref / 4) and supplied to the phase comparator 32 as the reference signal RF2 shown in FIG. The reference signal RF is also halved by the delay circuit 63.
The signal is delayed by the period (Tref / 2) and supplied to the phase comparator 33 as the reference signal RF3 shown in FIG. The reference signal RF is also 3/4 by the delay circuit 64.
The signal is delayed by the period (3Tref / 4) and supplied to the phase comparator 34 as the reference signal RF4 shown in FIG. Reference signal RF1 provided to phase comparators 31-34
To RF4 are the same, but their phases are shifted by π / 2.

On the other hand, the output signal CV from the VCO 5 is frequency-divided by the programmable frequency divider 21 and the feedback signal FV
B1 is provided to the phase comparator 31. Output signal CV
Is also divided by a programmable frequency divider 22;
The feedback signal FB2 is provided to the phase comparator 32. The output signal CV is also frequency-divided by the programmable frequency divider 23 and provided to the phase comparator 33 as a feedback signal FB3. The output signal CV is also supplied to the programmable frequency divider 2
4 and supplied to the phase comparator 34 as a feedback signal FB4. Here, the programmable frequency divider 21
Assuming that the dividing ratio of N to -24 is N, the frequency f of the output signal CV
₀ is represented by the following equation (1).

F ₀ = N · fr (1) The phase and frequency of the feedback signal FB 1 are compared with the phase and frequency of the reference signal RF 1 by the phase comparator 31.
As a result, error signal ER1 is provided to LPF4. The phase and frequency of the feedback signal FB2 are
2 is compared with the phase and frequency of the reference signal RF2, and as a result, the error signal ER2 is provided to the LPF4. The phase and frequency of the feedback signal FB3 are compared with the phase and frequency of the reference signal RF3 by the phase comparator 33, and as a result, the error signal ER3 is given to the LPF4. The phase and frequency of the feedback signal FB4 are compared with the phase and frequency of the reference signal RF4 by the phase comparator 34, and as a result, the error signal ER4 is provided to the LPF 4. Therefore, the phase comparators 31 to 34 perform the phase comparison four times (at timings T1 to T4) during one cycle of the reference signal RF as a whole.

The error signals ER1 to ER4 are converted into a control voltage CN by the LPF 4. VCO is the control voltage CN
Generates an output signal CV having a frequency f ₀ proportional to. As a result, the output signal CV is phase-synchronized with the reference signal RF.

In this PLL frequency synthesizer, the reference signal RF is shifted by π / 2,
Since the phase comparison is performed four times during one period, the lock-up time is reduced. For example, the frequency fr of the reference signal RF is set to 1 KHz, and the programmable frequency dividers 21 to 2 are set.
When the frequency division ratio N of 4 is set to 1000, an output signal CV of 1000 KHz that is phase-synchronized with the reference signal RF is output. If the frequency division ratio N of the programmable frequency dividers 21 to 24 is changed from 1000 to 2000 while the output signal CV of 1000 KHz is stably output, the output signal CV
Changes from 1000 KHz to 2000 KHz, but since the phase comparison is performed four times during one cycle of the reference signal RF, the frequency f ₀ of the output signal CV converges to 2000 KHz at a speed four times faster than in the prior art. This means that the apparent frequency of the reference signal RF has quadrupled to 4 KHz.

As described above, according to the PLL frequency synthesizer, since the phase comparison is performed four times during one cycle of the reference signal RF, the lock-up time is reduced to one-fourth of the conventional one.

In the above-described embodiment, the number of the programmable frequency dividers and the number of the phase comparators are respectively four, but are not particularly limited. For example, four programmable frequency dividers 21 to 24 may be combined, and only one programmable frequency divider that performs the function of each of the programmable frequency dividers 21 to 24 in a time-division manner may be provided. Also, the phase comparator 3
1 to 34 may be put together, and only one phase comparator that performs each function of the phase comparators 31 to 34 in a time-division manner may be provided.

Next, the four programmable frequency dividers 21 to 21
An example in which 24 are combined into one will be described as a second embodiment.

FIG. 3 shows the configuration of the second embodiment, and the differences from FIG. 1 will be described. The program frequency divider 9 is a frequency divider in which the four programmable frequency dividers 21 to 24 of FIG. Since there is one program divider 9,
One gate circuit 7 for synchronizing the frequency division start timing with the delay circuits 61 to 64 may be used.

FIG. 4 shows the structure of the program frequency divider 9,
It comprises a reference frequency divider 91 and a time division circuit 92. The reference frequency divider 91 has a configuration of a frequency extender system in which the allowable propagation delay time of the coincidence signal is increased, which is described in detail in Japanese Patent Publication No. 59-31060 by the same inventor, and will be briefly described here.

The reference frequency divider 91 comprises a counter circuit 911 and a coincidence circuit 912. The counter circuit 911 uses a predetermined division ratio m (m is an integer) as an initial value and
It counts down every time the output signal CV of O5 rises. This countdown is preset to an initial value when H (High) is input to the PE terminal. When the count value of the counter circuit becomes 2, the coincidence circuit 912 outputs H
Is output. This output is input to the PE terminal of the counter circuit 911. As a result, for example, when m = 5, the count of the counter circuit 911 is 5, 5, 4, 3, 2, 5,
5, 4, 3, 2,..., And the output signal P0 of the coincidence circuit 912 becomes H every 5 frequency division (every m frequency division). That is, the reference frequency divider 91 divides the output signal CV of the VCO 5 by m.

The reference frequency divider 91 is not limited to the frequency extender system, but may be any variable frequency divider that can divide the frequency at a predetermined frequency dividing ratio.

Next, the time division circuit 92 comprises first and second fixed frequency dividers 921 and 922 having a frequency division ratio of 2 and four AND gates 923, 924, 925 and 926. It is shown in FIG.

The first fixed frequency divider 921 includes a matching circuit 912
A signal P1 that divides the output signal P0 by 2 is output. Second
The fixed frequency divider 922 outputs a signal P2 that divides the output signal P1 of the first fixed frequency divider 921 by two.

The first AND gate 923 outputs a signal obtained by ANDing P0, P1 and P2. As a result, as shown in FIG. 5, a signal FB1 that rises every m × 4 frequency division is output.

The second AND gate 924 includes P0 and P1
And outputs a signal obtained by ANDing P2. As a result, as shown in FIG. 5, a signal FB2 whose phase is divided by m from the first AND gate 923 is output.

The third AND gate 925 comprises P0 and P1
, And outputs a signal obtained by ANDing the inversion of P2. As a result, as shown in FIG. 5, the first AND gate 923 outputs a signal FB3 having a phase shifted by m × 2.

The fourth AND gate 926 has P0 and P1.
, And a signal obtained by ANDing the inversion of P2. Thereby, as shown in FIG. 5, the first AND gate 92
A signal FB4 whose phase is shifted by m × 3 from 3 is output.

As described above, the program frequency divider 9 has the VCO
5, the output signal CV of No. 5 is divided by the division ratio of m × 4, and four signals shifted by the division of m can be output.

FIG. 6 shows the configuration of the third embodiment. In the third embodiment, the division ratio m × 4 (a multiple of 4) in the second embodiment is interpolated so that the division ratio can be set to an arbitrary integer. That is, the frequency division ratio is set to m × 4 + n (m is an integer, and n is any of 0, 1, 2, 3). 7 to 10 show n of 0, 1, 2, 3 (for example, n1
When H is n and n2 is L, then n = 01 in a binary system).

FIG. 6 is obtained by adding an interpolation circuit 93 to FIG. The interpolation circuit 93 includes a first fixed frequency divider 921, a second fixed frequency divider 922, an adder 931, a NAND gate 932, and two (fifth and sixth) AND gates 9.
33, 934 and an OR gate 935. The first and second fixed frequency dividers 922 are shared with the first and second fixed frequency dividers 922 of the second embodiment.

The adder 931 is connected to the division ratio input terminal of the counter circuit 911, and when the ADD terminal is at L (Low), the set division ratio m is used as it is in the counter circuit 911.
And when the ADD terminal is at the H level, the set dividing ratio m
A division ratio m + 1 obtained by adding 1 to the output is output to the counter circuit 911.

The NAND gate 932 receives P1 and P2 as inputs, and thereby outputs a signal P3 in which m out of m × 4 periods becomes H. This H period is m × 2 out of m × 4 cycles.
The period does not overlap with the period of H of P2 in which the period is H.

P3 is input to the fifth AND gate 933 together with the input signal n1. That is, when n1 is H, m ×
P3 in which the m-period becomes H among the four periods is selected. Also, P
2 is input to the sixth AND gate 934 together with the input signal n2. That is, when n2 is H, m × 2 out of m × 4 cycles
P2 whose cycle is H is selected. And the fifth AN
The output signal P4 of the D gate 933 and the sixth AND gate 9
The 34 output signal P5 is input to the OR gate 935.
P4 and P5 are ORed, and the signal P6 is added to the adder 931.
To control the addition of the adder 931.

As described above, m periods out of m × 4 periods are represented by H
Can be combined with those in which m × 2 periods in the m × 4 periods are set to H. With this combination, as shown in FIGS. 7 to 10, the period during which H is set in the m × 4 period is set to four periods of zero period, m period, m × 2 period, and m × 3 period.
Kind. Therefore, during the H period, the division ratio is 1
Because of the addition, the programmable frequency divider of the third embodiment has a frequency division ratio m × 4, a frequency division ratio m × 4 + 1, and a frequency division ratio m × 4 +
2. The frequency can be divided by the division ratio m × 4 + 3.

As described above, the four programmable frequency dividers 21 to 24 can be integrated into one.

In the above embodiment, the phase comparison is performed when the reference signal rises, but the phase comparison may be performed when the reference signal falls. Therefore, a normal phase comparator that performs a phase comparison when the reference signal rises and an opposite phase comparator that performs a phase comparison when the reference signal falls may be provided. In short, one of the reference signals
The phase comparison may be performed a plurality of times during the period.

The CPU 8 includes phase comparators 31-34.
It is preferable to control the phase comparators 31 to 34 so that when any one of them locks, the other three phase comparators are preset. In addition, when the frequency of the output signal CV is high, a prescaler method may be used together.

[0051]

According to the PLL frequency synthesizer of the present invention, since the phase comparison is performed a plurality of times within one cycle of the reference signal, the lock-up time is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a PLL frequency synthesizer according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the PLL frequency synthesizer of FIG.

FIG. 3 is a block diagram illustrating a configuration of a PLL frequency synthesizer according to a second embodiment.

FIG. 4 is a block diagram showing a configuration of a programmable frequency divider of FIG. 2;

FIG. 5 is a timing chart showing an operation of the programmable frequency divider of FIG. 2;

FIG. 6 is a block diagram illustrating a configuration of a programmable frequency divider according to a third embodiment.

7 is a timing chart showing an operation of the programmable frequency divider shown in FIG. 6 at a division ratio of 4 m.

8 is a frequency division ratio of 4m + 1 of the programmable frequency divider of FIG.
6 is a timing chart showing the operation of FIG.

9 is a division ratio of 4m + 2 of the programmable frequency divider of FIG. 6;
6 is a timing chart showing the operation of FIG.

10 shows a division ratio of 4 m + of the programmable frequency divider of FIG.
6 is a timing chart showing the operation of No. 3;

FIG. 11 is a block diagram showing a configuration of a conventional PLL frequency synthesizer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference oscillator 21-24 Programmable frequency divider 31-34 Phase comparator 4 Low-pass filter 5 Voltage controlled oscillator 61-64 Delay circuit 71-74 Gate circuit 9 Programmable frequency divider 91 Reference frequency divider 92 Time division circuit 93 Interpolation circuit

Claims (4)

[Claims] 1. A PLL frequency synthesizer for generating an output signal phase-locked to a reference signal, comprising: a reference oscillator for generating the reference signal; and a frequency divider for dividing the output signal to generate a feedback signal. Phase comparison means for comparing the phase of the feedback signal from the frequency divider with the phase of the reference signal from the reference oscillator at a first timing to generate an error signal; A low-pass filter that generates a control voltage in response to the control signal; and a voltage-controlled oscillator that generates the output signal in response to the control voltage from the low-pass filter. The phase comparison unit further includes a feedback from the frequency divider. A PLL frequency synthesizer for comparing a phase of a signal with a phase of a reference signal from the reference oscillator at a second timing different from the first timing to generate an error signal. . 2. A PLL frequency synthesizer for generating an output signal that is phase-locked to a first reference signal, comprising: a reference oscillator for generating the first reference signal; and a first reference signal from the reference oscillator. Reference signal generating means for generating a plurality of second reference signals having phases different from each other in response to a plurality of feedback signals corresponding to the plurality of second reference signals by dividing the output signal. A frequency divider that compares the phases of a plurality of feedback signals from the frequency divider with the phases of a plurality of second reference signals from the reference signal generator to generate an error signal; A PLL frequency synthesizer comprising: a low-pass filter that generates a control voltage in response to an error signal from a phase comparison unit; and a voltage-controlled oscillator that generates the output signal in response to a control voltage from the low-pass filter. The synthesizer. 3. A PLL frequency synthesizer for generating an output signal phase-locked to a first reference signal, wherein the reference oscillator generates the first reference signal; and a first reference signal from the reference oscillator. Reference signal generating means for generating a plurality of second reference signals having phases different from each other in response to the plurality of second reference signals; A plurality of frequency dividers for generating signals; and a phase for generating an error signal by comparing a phase of a feedback signal from the plurality of frequency dividers with a phase of a plurality of second reference signals from the reference signal generating means. PL comprising: a comparing unit; a low-pass filter that generates a control voltage in response to an error signal from the phase comparing unit; and a voltage-controlled oscillator that generates the output signal in response to a control voltage from the low-pass filter. L frequency synthesizer. 4. The phase comparison means is provided for each of the plurality of second reference signals, and compares a phase of a corresponding feedback signal with a phase of a corresponding second reference signal to generate an error signal. The PLL frequency synthesizer according to claim 3, comprising a plurality of phase comparators for generating the phase comparator.