JP2908293B2 - Digital phase locked loop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital phase locked loop circuit, and more particularly to a digital phase locked loop circuit mounted for clock synchronization of an LSI internal circuit.

[0002]

2. Description of the Related Art In recent years, the operating frequency of microprocessors mounted on workstations and high-end personal computers has exceeded 100 MHz, and there is a trend toward higher speeds. Therefore, in a system design using this kind of microprocessor, high-speed operation of 100 MHz or more is required for data transfer between LSIs. LSIs such as ASICs used in these systems corresponding to such high-speed operations tend to include phase-locked loop circuits (hereinafter, PLLs) for clock synchronization of internal circuits. The first reason is that, in high-speed operation, data transfer between LSIs becomes impossible due to clock skew which has not been a problem in conventional low-speed operation. To take. That is, by synchronizing the reference clock of each LSI using the built-in PLL, high-speed data transfer becomes possible. The second reason is to increase the internal processing speed by increasing the clock frequency inside the LSI to several times the system reference clock frequency using the PLL multiplication function. It is also suitable for coexistence with other low-speed operation LSIs in the system.

Conventionally, two types of PLLs of this type have been used: an analog type (hereinafter analog) and a digital type (hereinafter digital).

Referring to FIG. 5, which shows a block diagram of a conventional analog PLL, the conventional analog PLL includes a phase comparator 101, a charge pump 102, a loop filter 103, a voltage controlled oscillator (hereinafter, VCO) 104, , A frequency divider 105.

[0005] The general operation is well known and will not be described. The problem with mounting this analog PLL on an LSI is that the VCO 10
No. 4 is easily affected by noise and the like inside the LSI. As is well known, a VCO is an oscillator whose oscillation frequency changes in response to the supply of an analog control voltage. Therefore, if the power supply voltage of the transistor constituting the VCO fluctuates due to the influence of other circuits inside the LSI, or if noise is mixed in the VCO control signal line, the VCO is built in the LSI. There is a problem that the oscillation frequency fluctuates and causes jitter.
For this reason, it is difficult to mount all the components inside the LSI in the analog PLL, and the loop filter and the VCO, which are analog parts, need to be external to the LSI.

The digital PLL can greatly reduce the influence of noise interference from other circuits inside the LSI such as a power supply by using an up / down counter and a variable delay circuit composed of digital circuit elements instead of the VCO. As is well known, a digital circuit does not malfunction unless the noise level reaches a threshold level of a transistor constituting each circuit. Therefore, it can be easily mounted on an LSI.

Referring to FIG. 5, which shows a block diagram of a conventional digital phase locked loop circuit (digital PLL), the conventional digital PLL compares the phase of a reference clock C with the phase of a feedback signal FO and calculates the lead / A phase comparator 1 for outputting an up / down signal U / D in response to a delay, an n-bit up / down counter 2 for increasing / decreasing a count value N in response to the supply of the up / down signal U / D; , The delay value added to the reference clock C is varied in proportion to the count value N, and the output signal O and the feedback signal F
And a delay circuit 31 that outputs O.

Next, the operation of the conventional PLL will be described with reference to FIG. 6. The phase comparator 1 compares the reference clock C with the phase of the feedback signal FO, and the phase of the feedback signal FO advances. If it is, the up signal U is supplied to the up / down counter 2 and if it is late, the down signal D is supplied to the up / down counter 2. The determination is made by sampling the logic level of the feedback signal FO at the rising edge of the reference clock C. If the sampling result is "H", the up signal U, "L"
If so, it is determined that the down signal is D. The up-down counter 2 increases the count value N in response to the supply of the up signal U, and decreases the count value N in response to the supply of the down signal D to supply the same to the delay circuit 31. The delay circuit 3 varies the delay value in proportion to the count value N, and changes the phase of the output signal O, that is, the phase of the feedback signal FO by adding the delay value to the reference clock C. That is, as the count value N decreases, the delay value decreases, and as the counter value N increases, the delay value increases.

For example, if the phase of the feedback signal FO is advanced with respect to the reference clock C, the phase comparator 1 outputs the up signal U, and the up / down counter 2 increases or increases the count value N. As the counter value N increases, the delay circuit 31 increases the delay value added to the reference clock C, so that the phase of the feedback signal FO is delayed and the phase difference with the reference clock C decreases.

Conversely, if the phase of the feedback signal FO lags behind the reference clock C, the phase comparator 1 outputs a down signal D, and the up / down counter 2 decreases the count value N, that is, decreases. As the counter value N decreases, the delay circuit 31 decreases the delay value added to the reference clock C. As a result, the phase of the feedback signal FO advances and the phase difference from the reference clock C decreases.

By repeating the above operation, the phase difference between the reference clock C and the feedback signal FO decreases, and finally the phase difference becomes smaller than the minimum variable unit of the delay value of the delay circuit 31, that is, the delay step value. Then, the result of the phase comparison repeats up / down, and a phase synchronization (lock) state is established.

As described above, since the digital PLL is entirely constituted by a digital circuit, it is less susceptible to interference due to noise or the like which causes performance degradation such as jitter.
It can be easily mounted on SI.

However, since this digital PLL has a circuit configuration for adding a required delay to the reference clock, it can only obtain an output signal having the same frequency as that of the external reference clock, and does not have the above-mentioned multiplication function. Therefore, in addition to being used for phase synchronization with the internal clock of the LSI, when a clock having a frequency several times the above frequency is required for speeding up, a multiplying circuit must be provided separately.

[0014]

The above-mentioned conventional digital phase locked loop circuit can obtain only an output signal having the same frequency as that of the external reference clock from the circuit configuration for adding a required delay to the reference clock. When a clock having a frequency several times higher than the reference clock frequency is required, there is a disadvantage that a multiplying circuit must be provided separately.

[0015]

SUMMARY OF THE INVENTION A digital phase locked loop circuit of the present invention compares the phase of a reference clock signal with a first feedback signal to determine the lead and lag of the first feedback signal with respect to the reference clock signal. A first outputting an up signal and a down signal respectively corresponding to each;
And counts up and down respectively in response to the supply of the up signal and the down signal.
An up-down counter that outputs a count value of
Generating a first delay value proportional to the count value of the first clock signal and adding the first delay value to the reference clock signal to generate the first feedback signal.
A first loop circuit including a delay circuit, an up-counter that counts up the reference clock signal and outputs a second count value, and generates a second delay value proportional to the second count value. A second delay circuit that adds a second feedback signal to the reference clock signal to generate a second feedback signal, and a second phase that compares the phase of the reference clock signal with the second feedback signal to generate a phase comparison signal. A comparison circuit, and N-1 shifts whose phases are shifted by 1 / 2N (N is a positive integer of 2 or more ) of one cycle of the reference clock signal in response to the supply of the operation value corresponding to the phase comparison signal. A second loop circuit including a phase shift signal generating circuit for generating a phase signal; and performing a logical operation on the first feedback signal and the N-1 phase shift signals to obtain a frequency N of the reference clock signal. Logical operation circuit to generate double frequency output signal It is configured to include a.

[0016]

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which constituent elements common to those in FIG. The digital phase locked loop circuit (hereinafter referred to as a PLL) of the present embodiment shown in FIG. 1 has the same configuration as a conventional digital PLL, that is, includes a phase comparison circuit 1, an up / down counter 2, and a delay circuit 31, and is synchronized with a reference clock C. A first loop 11 for generating a feedback signal F1, a second loop 12 for generating a delay signal D2 whose phase is shifted by 1/4 cycle with respect to the feedback signal F1, and a feedback signal F1 and a delay signal D2
The exclusive OR (EXOR) of the output signal O and the output signal O
And an EXOR circuit 10 for generating the XOR2.

The second loop 12 compares the n-bit up counter 4 which counts the reference clock C and outputs the count value NU with the reference clock C and the feedback signal F2, and the comparison result indicates that the signal F2 corresponds to the advance of the signal F2. When switching from the up signal to the down signal corresponding to the delay, the phase comparison circuit 5 outputs the latch signals RA and RB for the first time and the next time, respectively, and the count value N in response to the supply of each of the latch signals RA and RB.
Latch circuits 6 and 7 for latching U and outputting holding signals A and B, respectively, receiving the holding signals A and B, and performing an operation (BA) / 4 required for delaying by 1/4 cycle from the reference clock C
And an operation circuit 8 that outputs an operation value E, and a first loop 1
An addition circuit 9 that adds the count value N of the up / down counter 1 and the operation value E and outputs an addition value S;
Delay circuits 31 and 32 are provided for generating a delay value proportional to each of the count values NU, adding the delay value to the reference clock C, and outputting a delay signal D2 and a feedback signal F2, respectively.

Next, the operation of the present embodiment will be described with reference to FIG. 1. First, the operation of the first loop 11 performs the same operation as the conventional one, and outputs the feedback signal F1. At the same time, the corresponding count value N is output to the adder 9. Second loop 1
2 is a phase-phase comparator 5 which outputs a reference clock C and a feedback signal F2.
And the phase of the feedback signal F2 is determined by sampling the logic level of the feedback signal F2 at the rising edge of the reference clock C, similarly to the phase comparator 1, and the corresponding up signal and down signal are respectively determined. Generate At first, the count value of the up counter 4 is 0 and the phase of the feedback signal F2 is advanced, so that an up signal is generated. On the other hand, the up counter 4 increases the count value NU in response to the supply of the reference clock C, and as the count value NU increases, the delay circuit 33 increases the delay value and delays the phase of the feedback signal F2. As a result, the phase comparison result of the phase comparison circuit 5 is delayed, and the up signal generated up to that point is switched to the down signal at a certain point. The phase comparison circuit 5 outputs the latch signal RA when switching from the up signal to the down signal. In response to the supply of the latch signal RA, the latch circuit 6 latches the count value NU.

When the phase comparison operation of the phase comparison circuit 5 is further repeated, the feedback signal F2 is further delayed with the increase of the count value NU, and the comparison result becomes an up signal at about half a cycle from the reference clock C of this delay. When the period reaches one cycle with a further delay, the comparison result switches from the up signal to the down signal again. The phase comparison circuit 5 outputs the latch signal RB at the second switching from the up signal to the down signal. In response to the supply of the latch signal RA, the latch circuit 7 latches the count value NU.

The arithmetic circuit 8 receives the holding signals A and B corresponding to the count value NU of each of the latch circuits 6 and 7, and performs an arithmetic operation (B−B) corresponding to the count value required for delaying one cycle from the reference clock C. A) is performed, and this is multiplied by 1/4 to output a calculation value E which is a corrected count value corresponding to a 1/4 cycle. The adder 9 adds the count value N and the operation value E, and supplies an addition value S to the delay circuit 32. The delay circuit 32 adds a delay proportional to the added value S to the reference clock C, and
2 is output.

Referring to FIG. 2 which is a time chart showing the timing relationship between the feedback signals F1 and F2 and the output signal O according to the present embodiment, the delay signal D2 is
1/4 period is delayed from 1. The EXOR circuit 10
In response to the supply of the feedback signal F1 and the delay signal D2, a double output signal O2, which is an exclusive OR of these signals F1 and D2, is output to the output terminal TO.

Next, referring to FIG. 3, which shows a second embodiment of the present invention for generating a quadrupled output signal, in which constituent elements common to FIG. This embodiment is different from the first embodiment in that
A second loop 13 corresponding to quadruple multiplication is provided in place of the second loop 12 corresponding to multiplication, and a four-input EXOR circuit 10A is provided instead of the two-input EXOR circuit 10.

The second loop 13 includes, in addition to the up counter 4 common to the first embodiment, the phase comparison circuit 5, the latch circuits 6, 7, the addition circuit 9, and the delay circuits 32, 33, Subtraction value B of holding signals B and A in place of arithmetic circuit 8
An adder 8A that outputs the added value G by dividing the value of −A by 1/8, an adder 14 that adds the calculated value G and the added value S of the output of the adding circuit 9 and outputs a added value T, And an adder 15 that adds the sum T and the sum T to output a sum V, generates a delay value proportional to each of the sums T and V, adds it to the reference clock C, and outputs the delay signals D3 and D4, respectively. Delay circuits 34 and 35 are provided.

The operation of the present embodiment will be described with reference to FIG. 3 and FIG. 4 showing the timing relationship of each signal of the present embodiment, with emphasis on the differences from the first embodiment.
The operation circuit 8A of the second loop 13 responds to the supply of the hold values A and B by performing an operation (BA) /
8 to output the operation value G. Each of the adders 914 and 15 adds the operation value G with the count value N and the addition values S and T, respectively, outputs the addition values S, T, and V, and supplies them to the delay circuits 32, 34, and 35, respectively. Delay circuit 3
2, 34, and 35 add delays corresponding to these added values to the reference clock C, and add 1/8, 2 /
Delayed signals D2, D3, D4 delayed by 8,3 / 8 cycles
Is output. The EXOR circuit 10A outputs the feedback signal F
In response to the supply of 1 and the delay signals D2, D3, and D4, an output signal O4, which is an exclusive OR of these signals F1, D2, D3, and D4, is output to the output terminal TO. that's all
Although the embodiment of the present invention has been described, the gist of the present invention is impaired.
It is obvious that the invention is not limited to these unless otherwise specified. Was
For example, if the output signal is to be multiplied by 3,
The operation circuit of (3) calculates the phase from the operation result of (BA) / 6.
Generate two signals shifted by 1/6, 2/6, respectively.
Obtaining an output of 3 times with an EXOR circuit is also within the scope of the present invention.
Clearly within.

[0025]

As described above, the digital phase locked loop circuit of the present invention comprises a first loop circuit for generating a first feedback signal, an up counter for outputting a second count, and a second counter for outputting a second count value. And a second delay circuit for generating a second feedback signal from the count value of N, and an N- phase shifter of 1/2 N period in response to the supply of the operation value corresponding to the phase comparison signal of the second phase comparison circuit. A second loop circuit including a phase-shift signal generation circuit for generating one phase-shift signal; and a logic operation circuit for performing a logic operation between the first feedback signal and the phase-shift signal. There is an effect that an output signal having a frequency N times as high as that of the synchronous signal can be supplied.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a digital phase locked loop circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart illustrating an example of an operation in the digital phase locked loop circuit according to the present embodiment.

FIG. 3 is a block diagram illustrating a digital phase locked loop circuit according to a second embodiment of the present invention.

FIG. 4 is a time chart showing an example of an operation in the digital phase locked loop circuit of the present embodiment.

FIG. 5 is a block diagram showing an example of a conventional analog phase locked loop circuit.

FIG. 6 is a block diagram showing an example of a conventional digital phase locked loop circuit.

[Explanation of symbols]

 1,5 Phase comparator 2 Up / down counter 4 Up counter 6,7 Latch circuit 8,8A Operation circuit 9,14,15 Addition circuit 10,10A EXOR circuit 11 First loop 12,13 Second loop 31,32,33 , 34,35 delay circuit

Claims (4)

(57) [Claims] 1. A phase comparison between a reference clock signal and a first feedback signal, wherein the first feedback signal is compared with the first clock signal.
A first phase comparison circuit for outputting an up signal and a down signal in response to the advance and delay of the feedback signal, and counting up and down respectively in response to the supply of the up signal and the down signal. An up / down counter that outputs a count value of 1; a first delay that generates a first delay value proportional to the first count value and adds the first delay value to the reference clock signal to generate the first feedback signal A first loop circuit including a circuit, an up-counter that counts up the reference clock signal and outputs a second count value, and generates a second delay value proportional to the second count value to generate a second delay value. A second delay circuit that adds a reference clock signal to generate a second feedback signal, and a second phase comparison that compares a phase between the reference clock signal and the second feedback signal to generate a phase comparison signal A circuit, and ＮN (N is a positive integer of 2 or more ) of one cycle of the reference clock signal in response to supply of an operation value corresponding to the phase comparison signal
A second loop circuit including a phase-shift signal generation circuit that generates N-1 phase-shift signals whose phases are shifted by phases, and a logic of the first feedback signal and the N-1 phase-shift signals A logic operation circuit for performing an operation to generate an output signal having a frequency N times the frequency of the reference clock signal. 2. The second phase comparison circuit compares the reference clock signal with the second feedback signal, and the phase comparison signal switches from a leading state of the second feedback signal to a lagging state. And a latch signal generating circuit for outputting first and second latch signals respectively at the first time and the next time, wherein the phase shift signal generating circuit responds to the supply of each of the first and second latch signals. First and second latch circuits for respectively latching the second count value and outputting first and second holding signals, and a predetermined operation in response to the supply of the first and second holding signals And an arithmetic circuit that outputs a first arithmetic value; a first adder circuit that adds the first arithmetic value and the first count value to output a first additional value; Generating a second delay value proportional to the sum of Digital phase-locked loop circuit according to claim 1, wherein the a third delay circuit for generating a phase shift signal. 3. An exclusive OR circuit for performing an exclusive OR operation of the first feedback signal and the (N−1) phase-shifted signals. 1
A digital phase locked loop circuit as described. 4. The phase shift signal generation circuit according to claim 1, wherein
A second operation circuit that executes a predetermined operation in response to the supply of the second holding signal and outputs a second operation value, and adds the second operation value and the first count value. A first addition circuit that outputs a first addition value; a second addition circuit that adds the first addition value and the second operation value to output a second addition value; A third adder circuit for adding the sum of the first and second calculated values and outputting a third added value; and a second and a second circuit proportional to each of the first, second, and third added values. And third, fourth, and fifth delay circuits that generate third and fourth delay values and add them to the reference clock signal to generate first, second, and third phase shift signals, respectively. The digital phase locked loop circuit according to claim 2, wherein