JPH10133217A - Liquid crystal display element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of stages, to improve an aperture ratio, to improve the performance of TFTs and to lower a gate driving voltage. SOLUTION: A TFT array substrate is formed with light shields 2 and source buses 4 of AlCu as a first layer, an insulating film 3 as a second layer, source electrodes S, drain electrodes D, pixel electrodes 5 and semiconductor layers 7 as a third layer and an insulating film 8 exclusive of the effective regions of the pixel electrodes as a fourth layer. Gate electrodes G, gate buses 9 and junctures 14 are formed by MoCr and AlCu thereon as a fifth layer. The source buses 4 and the source electrodes 5 are respectively connected through contact holes 10, 11 to the junctures 14. The light shields 2 are connected through the contact holes 12 to gate buses 9. The members of the first layer and the fifth layer are preferably anodically oxidized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a reduction in the number of steps and a reduction in power consumption.

[0002]

2. Description of the Related Art A liquid crystal display device (hereinafter referred to as LCD) has a thin film transistor (hereinafter referred to as TFT) corresponding to each pixel, a TFT array substrate in which pixel electrodes are formed in a matrix, and a glass substrate on the inner surface of a glass substrate. And a common electrode substrate having a common electrode formed on the inner surface thereof is disposed so as to oppose each other with a liquid crystal layer interposed therebetween. The performance and manufacturing cost of an LCD are largely determined by the TFT array substrate.

A TFT array substrate will be described with reference to FIGS. [1] A method for manufacturing a TFT array substrate will be described in the order of steps. (1) An Mo alloy (for example, MoCr) is entirely deposited on the glass substrate 1. (2) The Mo alloy is etched using the photolithography technique to form the light shield 2.

(3) An insulating film (for example, SiO ₂ ) over the entire surface of the substrate
3 is deposited. (4) A transparent conductive film (for example, ITO) is deposited on the entire surface of the substrate. (5) A Mo alloy (for example, MoCr) is deposited on the entire surface of the substrate. (6) The Mo alloy is etched using a photolithography technique to form a source bus (upper) 4b.

(7) IT using photolithography technology
O is etched to form a source bus (lower) 4a, a source electrode S, a pixel electrode 5, and a drain electrode D. (8) PH ₃ plasma treatment is performed on the entire surface of the substrate, and a
-Deposit Si. (9) The semiconductor layer 7 is formed by etching a-Si using a photolithography technique.

(10) An insulating film (for example, SiNx) on the entire surface of the substrate
8 is deposited. (11) The SiNx on the portion of the pixel electrode 5 which will become the effective display area is removed by etching using photolithography technology. (12) An Al alloy (for example, AlCu) and a Mo alloy (for example, MoCr) are deposited on the entire surface of the substrate (AlCu is on).

(13) Al using photolithography technology
The gate bus 9 and the gate electrode G are formed by etching Cu / MoCr. [2] Notable points are as follows. (1) The write shield 2, the source bus 4, and the gate bus 9 are formed by different processes and different materials.

(2) The write shield 2 is not connected to the power supply and floats. (3) The source bus (lower) 4a and the pixel electrode 5 are formed in the same layer. (4) The source bus (upper) 4b and the write shield 2 are not anodized. (5) Since the pixel electrode 5 and the source bus 4 are formed in the same layer without any intervening insulating film, a gap of about 4 μm or more must be provided between the two, so that the aperture ratio is reduced accordingly.

[0009]

The object of the present invention is to solve the following problems. Manufacturing costs are reduced by reducing the number of steps compared to the conventional case. Power consumption is reduced by increasing the aperture ratio. The display quality is improved by improving the performance of the TFT.

[0010] Power consumption is reduced by lowering the gate drive voltage.

[0011]

[Means for Solving the Problems]

(1) According to the first aspect of the present invention, the TFT array substrate has a light shield and a source bus formed of the same metal material as the first layer on the inner surface of the glass substrate, and the TFT array substrate is formed on the inner surface of the glass substrate on which the first layer is formed. A first insulating film (second layer) is formed, and on the first insulating film, a source electrode,
A drain electrode and a pixel electrode extended from the drain electrode are formed of a transparent conductive film, and a semiconductor layer is formed between and near the source electrode and the drain electrode. A second insulating film is formed as a fourth layer on the first insulating film on which the third layer is formed, and a fifth insulating film is formed on the second insulating film.
As a layer, a connecting portion for connecting the gate electrode, the gate bus, and the source electrode / source bus is formed of the same metal material.

The source electrode and the source bus are each connected to a connection for connecting the source electrode and the source bus through a contact hole, and the write shield is connected to the gate bus through the contact hole. (2) In the invention of claim 2, in the above (1), the first
The write shield and source bus of the layer or the gate electrode and gate bus of the fifth layer are anodized.

(3) According to the third aspect of the present invention, in the TFT array substrate, as a first layer on the inner surface of the glass substrate, the write shield and the source bus connecting portion disposed crossing the gate bus are made of the same metal material. A first insulating film (second layer) is formed on the inner surface of the glass substrate on which the first layer is formed, and a source electrode, a drain electrode, and a drain electrode are formed on the first insulating film as a third layer. A pixel electrode extended from the electrode is formed of a transparent conductive film, and a semiconductor layer is formed between and near the source electrode and the drain electrode. On the first insulating film on which the third layer is formed,
A second insulating film (fourth layer) is formed except for the effective display area of the pixel electrode, and a fifth layer is formed on the second insulating film as a gate electrode, a gate bus, and a source bus (however, crossing the gate bus). Are formed of the same metal material.

The source electrode is connected to the source bus through the contact hole, the source bus is connected to the source bus connection through the contact hole, and the write shield is connected to the gate bus through the contact hole. (4) In the invention according to claim 4, in (3), the first
Layer write shield and source bus connection, or fifth
The gate electrode, gate bus and source bus of the layer are anodized.

(5) In the fifth aspect of the present invention, the TFT array substrate is formed of the same metal material as the first layer on the inner surface of the glass substrate, wherein the write shield and the gate bus are connected to each other. A first insulating film (second layer) is formed on the glass substrate on which is formed a source electrode, a drain electrode, and a pixel electrode extended from the drain electrode as a third layer on the first insulating film. A semiconductor layer is formed between the source electrode and the drain electrode and in the vicinity thereof while being formed of the transparent conductive film. On the first insulating film on which the third layer is formed, a second insulating film (fourth layer) is formed.
The gate electrode and the source bus are formed of the same metal material as a fifth layer on the second insulating film, except for the effective display area of the pixel electrode.

The source electrode is connected to a source bus through a contact hole, and the gate bus is connected to a gate electrode through a contact hole. (6) In the invention according to claim 6, in (5), the first
The layer write shield and gate bus, or the fifth layer gate electrode and source bus are anodized.

(7) In the invention of claim 7, in (5), the gate electrode substantially overlaps the semiconductor layer and is formed in parallel with the source bus and in parallel with the gate bus. The formed portion forms an L shape. (8) According to the invention of claim 8, the (1), (3),
In any of (5), the write shield and the source bus, the write shield and the source bus connecting portion, or the write shield and the gate bus of the first layer are formed of Al or an Al alloy.

(9) In the ninth aspect of the present invention, (1),
In any one of (3) and (5), the gate electrode and the gate bus, or the gate electrode, the gate bus and the source bus, or the gate electrode and the source bus of the fifth layer are formed of M
It is formed from an o alloy and an Al alloy thereon.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

[1] First Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 and 2, parts corresponding to those in FIGS. 12 and 13 are denoted by the same reference numerals. (1-1) A method for manufacturing a TFT array substrate of Example 1 will be described in the order of steps.

(1) An Al alloy (for example, Al
Cu) is deposited on the entire surface. (2) Anodize the Al alloy. (3) The Al alloy is etched by using the photolithography technique, and the light shield (lower) 2a, the light shield (upper) 2b, the source bus (lower) 4a, and the source bus (upper).
4b is formed.

(4) An insulating film (for example, SiO ₂ ) over the entire surface of the substrate
3 is deposited. (5) A transparent conductive film (for example, ITO) is deposited on the entire surface of the substrate. (6) The source electrode S, the drain electrode D, and the pixel electrode 5 are formed by etching the ITO using the photolithography technique. (7) PH ₃ plasma treatment is performed on the entire surface of the substrate, and a
-Deposit Si.

(8) a-
The semiconductor layer 7 is formed by etching Si. (9) An insulating film (for example, SiNx) 8 is deposited on the entire surface of the substrate. (10) SiNx, SiO using photolithography technology
_{2. The} AlN oxide film is etched to remove SiNx on the portion of the pixel electrode 5 which will become the effective display area, and contact holes 10, 11, and 12 are formed.

(11) An Al alloy (for example, AlC
u) and a Mo alloy (eg, MoCr) (AlC
u is on). (12) AlCu / MoC using photolithography technology
r is etched to form a gate electrode (lower) Ga, a gate bus (lower) 9a, and a connection portion (lower) 4a for connecting the source bus 4 and the source electrode S.

(13) Anodize AlCu to form a gate electrode (upper) Gb, a gate bus 9b, and a connection (upper) 4b made of Al ₂ O ₃ . (1-2) Notable points include the following points. (1) The write shield 2 and the source bus 4 are conventionally formed in different processes, but are formed in the same process by the same anodized Al alloy.

(2) The gate bus 9 is anodized. (3) The write shield 2 and the gate bus 9 are connected in the contact hole 12 (FIG. 1C). (1-3) The features of the first embodiment are as follows. (1) In the prior art, the photolithography technique is used in steps (2), (6), (7), (9), and (1).
In contrast to the six steps 1) and (13), the number of steps is five in the embodiment, and the cost is reduced by reducing the number of steps.

(2) Since the source bus 4 is made of a low-resistance Al alloy, the wiring width can be reduced. Therefore, the aperture ratio becomes high. (3) Since the write shield 2 and the gate electrode G are connected, the TFT off-resistance can be increased. (4) Since the anodic oxide film Al ₂ O ₃ is formed on the surface of each electrode and the bus, the insulating property is excellent. This structure is effective in preventing short circuit between the source bus 4 and the gate bus 9, between the gate bus 9 and the common electrode of the opposite substrate, and between the write shield 2 and the drain electrode D and the source electrode S.

[2] Embodiment 2 Embodiments of the second and fourth aspects of the present invention will be described with reference to FIGS. (2-1) A method for manufacturing a TFT array substrate of Example 2 will be described in the order of steps. (1) An Al alloy (for example, AlCu) is deposited on the entire surface of the glass substrate 1. (2) Anodize the Al alloy.

(3) Al by photolithography
Etch the alloy to light shield 2 and source bath 4
A connecting portion 16 for connecting the two is formed. (4) An insulating film (for example, SiO ₂ ) 3 is deposited on the entire surface of the substrate. (5) A transparent conductive film (for example, ITO) is deposited on the entire surface of the substrate. (6) The drain electrode D, the source electrode S, and the pixel electrode 5 are formed by etching the ITO using the photolithography technique.

(7) PH ₃ plasma treatment is performed on the entire surface of the substrate, and a-Si is continuously deposited. (8) The semiconductor layer 7 is formed by etching a-Si using a photolithography technique. (9) An insulating film (for example, SiNx) 8 is deposited on the entire surface of the substrate. (10) SiNx / SiO using photolithography technology
_{The 2} / Al oxide film is etched to remove SiNx on the portion of the pixel electrode 5 which will be the effective display area. Further, contact holes 12, 18, 19 and 20 are formed.

(11) An Al alloy (for example, AlC
u) and a Mo alloy (eg, MoCr) (AlC
u is on). (12) AlCu / MoC using photolithography technology
The gate electrode G, the gate bus 9 and the source bus 4 are formed by etching r. (13) Anodize AlCu to form a gate electrode (upper) Gb, a gate bus (upper) 9b, and a source bus (upper) 4b made of Al ₂ O ₃ . (2-2) Notable points of the second embodiment are described below.

(1) The connection portion 16 between the write shield 2 and the source bus is formed of the same material by anodized Al alloy in the same process. (2) Almost all gate bus 9 and source bus 4 have the same Al
Formed in the same step with an alloy and anodized. (3) The write shield 2 and the gate bus 9 are connected in the contact hole 12 (FIG. 3C). (2-3) The features of the second embodiment are as follows.

(1) The number of processes is reduced to five, and the cost is reduced. (2) Since the source bus 4 is formed of a low-resistance Al alloy, the wiring width can be reduced. Therefore, the aperture ratio becomes high. (3) Since the write shield 2 and the gate electrode G are connected, the TFT off-resistance can be increased.

(4) Since the anodic oxide film is used, the insulating property is excellent. In the case of the second embodiment, between the source bus 4 and the common electrode,
This is effective in preventing a short circuit between the gate bus 9 and the common electrode and between the write shield 2 and the drain electrode D / source electrode S. [3] Third Embodiment A third embodiment of the present invention will be described with reference to FIGS. (3-1) The manufacturing method of Example 3 will be described in the order of steps.

(1) An Al alloy (for example, Al
Cu) is deposited on the entire surface. (2) The Al alloy is etched using photolithography technology to form the gate bus 9 and the write shield 2 in a connected state. (3) Anodize the gate bus 9 and the write shield 2. (4) An insulating film (for example, SiO ₂ ) 3 is deposited on the entire surface of the substrate.

(5) A transparent conductive film (for example, IT
O) is deposited. (6) The drain electrode D, the source electrode S, and the pixel electrode 5 are formed by etching the ITO using the photolithography technique. (7) PH ₃ plasma treatment is performed on the entire surface of the substrate, and a
-Deposit Si. (8) The semiconductor layer 7 is formed by etching a-Si using a photolithography technique.

(9) An insulating film (for example, SiNx) over the entire surface of the substrate
8 is deposited. (10) SiNx / SiO using photolithography technology
_{The 2} / Al oxide film is etched to remove SiNx on the portion of the pixel electrode 5 which will be the effective display area. Further, contact holes 23 and 24 are formed. (11) An Al alloy (for example, AlCu) and a Mo alloy (for example, MoCr) are deposited on the entire surface of the substrate (AlCu is on).

(12) Using photolithography technology, A
The gate electrode G and the source bus 4 are formed by etching lCu / MoCr. (13) Anodize AlCu. (3-2) Notable points are as follows. (1) The write shield 2 and the gate bus 9 are formed of the same Al alloy in the same process, and then are anodized.

(2) The write shield 2 and the gate bus 9
Are continuous (connected). (3) The gate electrode G and the source bus 4 are formed of the same Al alloy in the same step and are anodized. (4) The storage capacitor Cs is formed between the gate bus 9 and the pixel electrode 5 and between the pixel electrode 5 and the gate electrode G (FIG. 5).
C). (3-3) The features of the third embodiment are as follows.

(1) The number of processes is reduced to five, and the cost is reduced. (2) Since the source bus 4 is formed of a low-resistance Al alloy, the wiring width can be reduced. Therefore, the aperture ratio becomes high. (3) Since the write shield 2 and the gate electrode G are connected, the TFT off-resistance can be increased.

(4) Since the anodic oxide film is used, the insulating property is excellent. In the case of the third embodiment, a short circuit is prevented between the source bus 4 and the common electrode of the opposite substrate, between the gate bus 9 and the common electrode, between the write shield 2 and the drain electrode D / source electrode S, and between the source bus 4 and the gate bus 9. effective. (5) Since the storage capacitor is formed in a two-layer structure (SiO ₂ and SiNx), the electrode area required for forming the storage capacitor is reduced, resulting in a high aperture ratio.

[4] Comparison between Conventional Example and Each Example FIG. 7 shows a comparison between the steps and characteristics of the conventional example and each example. In the first embodiment, the write shield 2 and the source bus 4
In the second embodiment, the gate bus 9 and the source bus 4 are manufactured, and in the third embodiment, the write shield 2 and the gate bus 9 are manufactured in the same process using the same material (for example, AlCu). These are formed in separate layers in separate steps in the conventional example, and the number of steps is reduced, leading to cost reduction.

In the conventional example, the source bus and the pixel electrode are formed in the same layer, whereas in the present invention, both embodiments are formed in separate layers. Therefore, since there is no need to provide a gap between the two when viewed from above, the pixel electrode can be formed closer to the source bus than before, and the aperture ratio improves accordingly. Therefore, the brightness of the backlight required to obtain the same screen brightness as in the related art can be reduced, so that the power consumption of the backlight can be reduced.

FIG. 9 shows the result of comparing the drain current Id versus the gate voltage Vg characteristics of the TFT using the measurement system shown in FIG. It can be seen that when the write shield 2 is connected to the gate electrode G as in the present invention, the off-resistance of the TFT increases and the off-characteristics are improved. When the TFT requires an OFF current of 10 ^-12 A or less, and when the write shield is connected to the gate,
As shown in FIG. 11, the low level of the gate signal waveform
The voltage _VGL between the source signal waveform and the low level can be reduced by about 5 V as compared with the conventional case. Then, also about 5V smaller amplitude V _G of the gate signal waveform.

The storage capacitance of the TFT is Cs, the capacitance between the gate electrode G and the drain electrode D is C _GD , and the capacitance of the liquid crystal cell is C _LC.
Then, as shown in FIG. 10, the TFT includes the n-th source bus SB (n), the (n-1) -th gate bus GB (n-1), and the n-th gate bus GB (n-1).
It is electrically connected to gate bus GB (n). The difference [Delta] Vc of the optimum common voltage Vc and the source center voltage is given by _{ΔVc = {C GD / (C} LC + Cs + C GD)} V G. Therefore, when V _G is small, ΔVc also becomes small. ΔV
It is known that when c is small, the display quality is improved.
The power consumption of the gate driver and V _G is small is reduced.

[0045]

Since the write shield and the source bus, or the gate bus and the source bus, or the write shield and the gate bus are formed of the same material and the same layer, the number of photo steps is reduced. By performing anodization on Al or an Al alloy, insulation between layers is improved.

By employing Al or an Al alloy for the source bus, the resistance of the wiring can be reduced, and the driving voltage can be reduced. Since the source and the pixel are formed in different layers, the aperture ratio is improved. If the aperture ratio is improved, the backlight luminance required to obtain the same screen luminance as that of the related art becomes smaller, so that the power consumption of the backlight is reduced.

[0047] By connecting the light shield and the gate can be reduced the amplitude V _G of the gate voltage, it is possible to reduce the power consumption of the gate driver.

[Brief description of the drawings]

FIG. 1 is a sectional view of a TFT array substrate according to the first and second embodiments.

FIG. 2 is a plan view corresponding to FIG. 1;

FIG. 3 is a sectional view of a TFT array substrate according to the third and fourth embodiments.

FIG. 4 is a plan view corresponding to FIG. 3;

FIG. 5 is a sectional view of a TFT array substrate according to the fifth and sixth embodiments.

FIG. 6 is a plan view corresponding to FIG. 5;

FIG. 7 is a diagram comparing each embodiment of the present invention with a conventional example.

FIG. 8 is a connection diagram illustrating a measurement system of a TFT.

FIG. 9 is a graph showing drain current versus gate voltage characteristics of the TFT of the present invention.

FIG. 10 is a diagram showing an electric equivalent circuit of each pixel of the liquid crystal display element.

FIG. 11 is a diagram showing a gate signal waveform and a source signal waveform of a TFT.

FIG. 12 is a sectional view of a conventional TFT array substrate.

FIG. 13 is a plan view corresponding to FIG. 12;

Claims (9)

[Claims] 1. A TFT array substrate in which thin film transistors (hereinafter referred to as TFTs) and pixel electrodes corresponding to respective pixels are formed in a matrix on an inner surface of a glass substrate, and a common electrode is formed on an inner surface of the glass substrate. In a liquid crystal display element in which a common electrode substrate and a liquid crystal layer are disposed in close proximity to each other with a liquid crystal layer interposed therebetween, the TFT array substrate has a light shield and a source bus formed of the same metal material as a first layer on an inner surface of a glass substrate. A first insulating film is formed as a second layer on the inner surface of the glass substrate on which the first layer is formed, and a third layer is formed on the first insulating film as a third layer extending from the source electrode, the drain electrode, and the drain electrode. A pixel electrode formed of a transparent conductive film, a semiconductor layer is formed between and near the source electrode and the drain electrode, and the third layer is formed. A second insulating film is formed as a fourth layer on the first insulating film, and a connecting portion for connecting a gate electrode, a gate bus, and a source electrode / source bus as a fifth layer on the second insulating film. Are formed of the same metal material, the source electrode and the source bus are respectively connected to the connection part through a contact hole, and the light shield is connected to the gate bus through a contact hole. 2. The liquid crystal display device according to claim 1, wherein the write shield and the source bus of the first layer or the gate electrode and the gate bus of the fifth layer are anodized. 3. The T corresponding to each pixel is formed on an inner surface of a glass substrate.
FT and TF in which pixel electrodes are formed in a matrix
In a liquid crystal display element in which a T-array substrate and a common electrode substrate having a common electrode formed on the inner surface of a glass substrate are disposed to face each other with a liquid crystal layer interposed therebetween, First, as a first layer, a write shield and a source bus connecting portion disposed to cross the gate bus are formed of the same metal material, and a second layer is formed on the inner surface of the glass substrate on which the first layer is formed. A first insulating film is formed, and a source electrode, a drain electrode, and a pixel electrode extended from the drain electrode are formed as a third layer on the first insulating film by a transparent conductive film, and the source electrode and the drain electrode are formed on the first insulating film. A semiconductor layer is formed between and in the vicinity of the drain electrode, a second insulating film is formed as a fourth layer on the first insulating film on which the third layer is formed, excluding an effective display region of the pixel electrode; So As a fifth layer on the second insulating film, a gate electrode, a gate bus, and a source bus (except for a portion crossing the gate bus) are formed of the same metal material, and the source electrode is connected to the source bus through a contact hole. The liquid crystal display device according to claim 1, wherein the source bus is connected to the source bus connection through a contact hole, and the write shield is connected to the gate bus through a contact hole. 4. The liquid crystal display according to claim 3, wherein the write shield and source bus connection of the first layer or the gate electrode, gate bus and source bus of the fifth layer are anodized. element. 5. The T corresponding to each pixel on an inner surface of a glass substrate.
FT and TF in which pixel electrodes are formed in a matrix
In a liquid crystal display element in which a T-array substrate and a common electrode substrate having a common electrode formed on the inner surface of a glass substrate are arranged to face each other with a liquid crystal layer interposed therebetween, the TFT array substrate is formed on the inner surface of the glass substrate. First, a write shield and a gate bus are connected to each other and formed of the same metal material as a first layer, and a first insulating film is formed as a second layer on the glass substrate on which the first layer is formed. A source electrode, a drain electrode, and a pixel electrode extended from the drain electrode as a third layer on one insulating film,
A semiconductor layer is formed between the source electrode and the drain electrode and in the vicinity of the source electrode and the drain electrode, and a second insulating layer is formed as a fourth layer on the first insulating film on which the third layer is formed. A film is formed excluding the effective display area of the pixel electrode, a gate electrode and a source bus are formed of the same metal material as a fifth layer on the second insulating film, and the source electrode is formed through a contact hole. A liquid crystal display device connected to a bus, wherein the gate bus is connected to the gate electrode through a contact hole. 6. The liquid crystal display device according to claim 5, wherein the write shield and the gate bus of the first layer or the gate electrode and the source bus of the fifth layer are anodized. 7. The method according to claim 5, wherein the gate electrode comprises:
A liquid crystal display characterized by being formed in an L-shape by a portion substantially overlapping on the semiconductor layer and formed parallel to the source bus and a portion overlapping and parallel formed on the gate bus. element. 8. The method according to claim 1, wherein
A liquid crystal display device, wherein the first layer, the light shield and the source bus, the write shield and the source bus connection, or the write shield and the gate bus are made of Al or an Al alloy. 9. The method according to claim 1, wherein
A liquid crystal display element, wherein the gate electrode and the gate bus, or the gate electrode, the gate bus and the source bus, or the gate electrode and the source bus of the fifth layer are made of a Mo alloy and an Al alloy thereon.