JPH1013303A - Synchronous tracking circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous tracking circuit where synchronous tracking in the receiving station of a mobile communication system based on a spread spectrum system is executed with superior precision. SOLUTION: The correlation of an early PN(pseudo-noise) code S18e with a late PN code S181 in a receiving signal (in) is calculated in correlative circuits 12a and 12b so as to be outputted as correlative values S12a and S12b. The average of the correlative values S12a and S12b based on a first symbol number is calculated in complex averaging circuits 13a and 13b so as to be outputted as average values S13a and S13b. The absolute values of the average values S13a and S13b are calculated in absolute value circuits 14a and 14b so as to be outputted as absolute values S14a and S14b. The average of the absolute values S14a and S14b based on the second symbol number larger than the first one is calculated in averaging circuits 15a and 15b so as to be outputted as the average values S15a and S15b. The difference value S16 of the average values S15a and S15b is calculated in a difference circuit 16. A timing for outputting the PN codes 18e, 18l and 18m of an PN code generator 18 is changed based on the comparison result of the threshold values (m) and (n) of the difference value S16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization tracking circuit provided in a pilot signal receiving circuit of a mobile communication system based on a spread spectrum communication system.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one described in the following literature. Literature; Digital Mobile Communication Technology (1988-2-25), published by Japan Industrial Technology Center Co., Ltd., Chapter 4, "Spread Spectrum Communication", P.127-128. Fig. 2 shows the conventional synchronous tracking described in the literature. FIG. 3 is a configuration block diagram showing an example of the circuit, and FIG. 3 is a time chart of the signals in FIG. This synchronization tracking circuit performs
Are inputted. The correlator 1 receives the received signal IN and a late pseudo random signal (Pseudo Noise,
(Hereinafter referred to as a PN code.) A function of obtaining a correlation value S1 with S6b is provided. The correlator 2 receives the received signal IN and the rate PN
Early PN advanced in phase by one chip with respect to code S6b
It has a function of obtaining a correlation value S2 with the code S6a.
The output terminal of the correlator 1 is connected to the + input terminal of the difference circuit 3, and the output terminal of the correlator 2 is connected to the − input terminal of the difference circuit 3. The difference circuit 3 is a circuit that outputs an error voltage signal S3 that is a difference between the correlation value S1 and the correlation value S2. The output terminal of the difference circuit 3 is connected to the input terminal of the loop filter 4. The output terminal of the loop filter 4 is a voltage controlled oscillator (Voltage Controlled Oscillato).
r, hereinafter referred to as VCO) 5. The output terminal of the VCO 5 is connected to the input terminal of the PN code generator 6. The PN code generator 6 generates an early PN code S6 based on the frequency of the clock output from the VCO 5.
a and a function of generating the late PN code S6b. A first output terminal of the PN code generator 6 for outputting the early PN code S6a is connected to the correlator 2, and a second output terminal of the PN code generator 6 for outputting the late PN code S6b is connected to the correlator 1. Have been.

In this synchronous tracking circuit, a received signal IN transmitted through a spatial propagation path is input to two correlators 1 and 2. In the correlators 1 and 2, the received signal IN and the late PN code S
6b and the correlation with the Early PN code S6a are calculated, and correlation values S1 and S2 are generated. Correlation values S1, S2
Is input to the difference circuit 3, an error voltage signal S3 which is a difference between the correlation values S1 and S2 as shown in FIG. 3 is output. The error voltage signal S3 is input to the VCO 5 after being filtered by the loop filter 4. The VCO 5 generates a clock S5 having a frequency based on the voltage of the output signal S4 of the loop filter 4. The PN code generator 6 generates an early PN code S6a and a late PN code S6b based on the frequency of the clock S5. That is, the error voltage signal S3
When the error voltage signal S3> 0, that is, when the phase of the PN codes S6a and S6b is delayed, the VCO
5, the error voltage signal S3 <0, that is, the PN code S6a,
When the phase of S6b is advanced, the VCO 5 is controlled so as to delay the phase. Therefore, in this synchronous tracking circuit, by continuing these operations, the error voltage signal S
The phases of the PN codes S6a and S6b are locked so that 3 = 0, and the synchronization is maintained.

[0004]

However, the synchronization tracking circuit of FIG. 2 has the following problems. That is, when the power of the noise component is high, the signal-to-noise power ratio (hereinafter, referred to as the S / N ratio) deteriorates, so that the correlation between the received signal IN in the correlators 1 and 2 and the PN codes S6a and S6b is obtained. By increasing the correlation section, it is possible to increase the process gain and improve the accuracy of synchronous tracking. However, when the S / N ratio is poor and the fading speed is fast, if the correlation section is long, the fading speed cannot be followed. Further, if the correlation section is shortened, the process gain cannot be obtained. Therefore, in any case, the communication quality is degraded, and in the worst case, the synchronization may be lost and the communication may be interrupted.

[0005]

According to the present invention, there is provided a synchronization tracking circuit provided in a receiving station of a mobile communication system based on a spread spectrum system for synchronizing with a received signal. It is configured as follows. In other words, the synchronization tracking circuit is configured to generate an in-phase component (hereinafter, referred to as an I component) and a quadrature component (hereinafter, referred to as a Q component) of a received signal represented by a complex number transmitted through a spatial propagation path, and a first PN signal. A first correlation circuit for obtaining each correlation value for each symbol representing a unit of the received signal, and a phase delayed by one chip with respect to the I and Q components of the received signal and the first PN signal. A second correlation circuit for obtaining each correlation value with the second PN signal for each symbol; and a first symbol for integrating one correlation with each correlation value output from the first correlation circuit.
And a first averaging circuit for averaging the respective integration results using a transversal filter to obtain a first I component average value and a first Q component average value, respectively, and the second averaging circuit. The integration of one symbol is sequentially performed for each correlation value output from the correlation circuit of the number of times corresponding to the first number of symbols, and each integration result is averaged using a transversal filter to obtain a second I component average. Value and second
Is provided with a second averaging circuit for calculating the average value of the Q component.

The synchronization tracking circuit calculates an absolute value of a first complex number having the first I component average value and the first Q component average value as real and imaginary parts, respectively. An absolute value circuit, the second I component average value and the second Q
A second absolute value circuit for calculating an absolute value of a second complex number having a component average value as a real part and an imaginary part, respectively, and integrating the symbol of the first complex number for one symbol with the first complex number; Is sequentially performed for a second symbol number larger than the symbol number of
A third averaging circuit for averaging the respective integration results using a transversal filter to obtain a first average value, and integrating the integration of one symbol with respect to the absolute value of the second complex number to the second averaging circuit. And a fourth averaging circuit for averaging the respective integration results using a transversal filter to obtain a second average value, and the first average value and the second average value. And a difference circuit for calculating a difference value between the first threshold value and a second threshold value smaller than the first threshold value and the first threshold value. Is large, the first comparison result is output. If the difference value is between the first threshold value and the second threshold value, the second comparison result is output. A threshold circuit that outputs a third comparison result when the threshold value is smaller than a threshold value of 2. When the second comparison result is output from the value circuit, the first PN signal and the second PN signal are generated at a reference timing, and the first comparison result is output from the threshold circuit. The first PN at a later timing than when the second comparison result is output.
And when the third comparison result is output from the threshold circuit, the first PN signal and the second PN signal are generated at a timing earlier than when the second comparison result is output.
A PN signal generator for generating the PN signal and the second PN signal.

According to the present invention, since the synchronous tracking circuit is configured as described above, the first and second synchronous tracking circuits can be used in an inferior propagation path environment, for example, when the noise power is high and the fading speed is high. The average in the averaging circuit is the first
Following the fading speed by taking only the length based on the number of symbols, the average of the absolute values of the first and second complex numbers is calculated by the third and fourth averaging circuits based on the second number of symbols. The process gain is secured by taking only the length. Thereafter, a comparison result is output from the threshold circuit based on a difference value between the first average value and the second average value. Each PN signal is output from the PN signal generator at a timing based on the comparison result, and output to each correlator. Therefore, the above problem can be solved.

[0008]

FIG. 1 is a block diagram showing the configuration of a synchronization tracking circuit according to an embodiment of the present invention. The synchronization tracking circuit includes an input terminal 11 and first and second correlation circuits 12.
a, 12b, complex averaging circuits 13a, 13b as first and second averaging circuits, first and second absolute value circuits 14a, 14b, and third and fourth averaging circuits 15a, 15a,
15b, a difference circuit 16, a threshold circuit 17, and a PN code generator 18 which is a pseudo random signal generator. The input terminal 11 for inputting the reception signal in is connected to each first input terminal of the correlation circuits 12a and 12b.
The correlation circuit 12a has a function of obtaining, for each symbol, a correlation value S12a between the I component and the Q component of the received signal in and the Early PN code S18e as the first pseudo random signal. The correlation circuit 12b is a second pseudo random signal having a phase delayed by one chip with respect to the I component and the Q component of the received signal in and the Early PN code S18e.
It has a function of obtaining each correlation value S12b with the PN code S181 for each symbol. Correlation circuits 12a, 12
Each output terminal of b is connected to each input terminal of complex averaging circuits 13a and 13b, which are first and second averaging circuits.

The complex averaging circuit 13a includes a correlation circuit 12a
The integration for one symbol is sequentially performed on each correlation value S12a output from the above for a desired first number of symbols, and the integration results are averaged using a transversal filter to obtain a first I component average value. And the first Q component average value S
13a. Complex averaging circuit 13
b is each correlation value S12b output from the correlation circuit 12b.
, One symbol is sequentially integrated for the first number of symbols, and the integration results are averaged using a transversal filter to obtain a second I component average value and a second Q component average value S13b. It has a function to request.
Output terminals of the complex averaging circuits 13a and 13b are connected to input terminals of the first and second absolute value circuits 14a and 14b, respectively. The absolute value circuit 14a has a function of calculating an absolute value S14a of a first complex number having a first I component average value and a first Q component average value S13a as a real part and an imaginary part, respectively. The absolute value circuit 14b calculates the second I
It has a function of calculating an absolute value S14b of a first complex number having a component average value and a second Q component average value S13b as a real part and an imaginary part, respectively. Output terminals of the absolute value circuits 14a and 14b are connected to third and fourth averaging circuits 15a and 15b, respectively.
b is connected to each input terminal.

The averaging circuit 15a sequentially integrates the absolute value S14a for one symbol by the second symbol number larger than the first symbol number, and calculates each integration result by using a transversal filter. Each has a function of averaging to obtain a first average value S15a. The averaging circuit 15b sequentially integrates the absolute value S14b for one symbol by the second number of symbols, and averages each integration result using a transversal filter to obtain a second average value S15b. Has the required function.
The output terminal of the averaging circuit 15a is connected to the minus input terminal of the difference circuit 16, and each output terminal of the averaging circuit 15b is connected to the plus input terminal of the difference circuit 16. Difference circuit 1
6 is a difference value S1 between the average value S15a and the average value S15b.
6 is provided. An output terminal of the difference circuit 16 is connected to an input terminal of the threshold circuit 17. The threshold circuit 17 includes, for example, a comparator and an encoder that encodes an output signal of the comparator.
16 and a first threshold value m set in advance and the first threshold value m
The second threshold value n is compared with a smaller second threshold value n. Then, the threshold circuit 17 determines, according to the comparison result,
When the difference value S16 is larger than the threshold value m, the first comparison result S17a is output, and the difference value S16 is set to the threshold value m and the threshold value n.
And outputs a second comparison result S17b when
It has a function of outputting a third comparison result S17c when the difference value S16 is smaller than the threshold value n. Threshold circuit 1
The output terminal 7 is connected to the input terminal of a PN code generator 18 which is a pseudo random signal generator.

The PN code generator 18 compares the comparison results S17a,
It comprises a decoder for decoding S17b and S17c, a shift register, a counter and the like. Then, the PN code generator 18 outputs the second comparison result S 1 from the threshold circuit 17.
When 7b is output, it is early at the reference timing.
This circuit generates the PN code S18e and the late PN code S181. Also, the PN code generator 18 outputs the early PN code S18e and the late PN code S181 at a later timing when the first comparison result S17a is output from the threshold circuit 17 than when the second comparison result S17b is output. Is a circuit that generates Further, the PN code generator 18 outputs the early PN code S18e and the late PN code S18 at a timing earlier when the third comparison result S17c is output from the threshold circuit 17 than when the second comparison result S17b is output.
1 is a circuit that generates 1. The early PN code S18e and the late PN code S181 are used by the second circuits of the correlation circuits 12a and 12b.
Input terminals.
The PN code S18m whose phase is delayed by 1/2 chip with respect to the early PN code S18e is output to a demodulation circuit (not shown).

FIG. 4 is a schematic configuration diagram of the averaging circuit 15a in FIG. The averaging circuit 15a calculates the absolute value S1
Integration circuit 2 that integrates 4a and outputs output signal x (t)
1 is provided. The output side of the integrating circuit 21 has a weight coefficient K
It is connected to the adder 24 via a coefficient element 23-0 having ₀ . Further, on the output side of the integrating circuit 21, N (N; a natural number of 1 or more) delay elements 22-1 to 22-N
Are connected in series. Each output side of the delay element 22-1 to 22-N is connected to the adder 24 via respective coefficients elements 23-1 to 23-N, each having a weighting factor _K 1 ~K _N. The delay elements 22-1 to 22-N, the coefficient elements 23-0 to 23-N, and the adder 24 constitute a transversal filter. Output signal y of the averaging circuit
(T) is represented by the following equation (1): y (t) = K ₀ x (t) + K ₁ x (t−T) + K ₂ x (t−2T) +... + K _N x ( t-NT) · · · (1) where, T; sample time width K ₀ ~K _N; in the coefficient the equation (1), the coefficient _K 0 all ~K _N 1 / (N
+1), an average value is calculated.

The averaging circuit 15b has the same configuration. Further, the complex averaging circuits 13a and 13b have a configuration in which two circuits similar to the averaging circuit of FIG. 4 are combined to obtain the I component average value and the Q component average value, respectively. However, in the complex averaging circuits 13a and 13b, the value of N is smaller than the value of N in the averaging circuits 15a and 15b. Next, the operation of FIG. 1 will be described. A reception signal in (complex number) is input from the input terminal 11. In the correlation circuits 12a and 12b, the received signal in is multiplied by the early PN code S18e and the late PN code S181, and the results are cumulatively added and the correlation values S12a and S12b for one symbol (for example, 64 bits) are obtained. Is calculated. The complex averaging circuits 13a and 13b calculate the correlation value S12
a, the average of the first number of symbols of S12b is calculated and I
The component average value and the Q component average values S13a and S13b are obtained. The I component average value and the Q component average value S13a, S1
3b is input to the absolute value circuits 14a and 14b, respectively. The absolute value circuits 14a and 14b calculate the I component average value and Q
Since the component average values S13a and S13b are complex numbers, their absolute values S14a and S14b are calculated. Absolute value S
14a and 14b are input to averaging circuits 15a and 15b, respectively.

The averaging circuits 15a and 15b calculate the absolute value S1
Averages for the second symbols of 4a and S14b are calculated to obtain averages S15a and S15b. The average value S15a is input to the minus input terminal of the difference circuit 16, and the average value S15a
b is input to the + input terminal of the difference circuit 16. The difference circuit 16 calculates a difference value S16 between the average value S15a and the average value S15b, and outputs the difference value S16 to the threshold circuit 17. Threshold circuit 17
Compares the difference value S16 with preset threshold values m and n. When the difference value S16 is between the threshold value m and the threshold value n,
Since the phase shift of the received signal in is within the allowable range, the threshold circuit 17 sends the PN code
It instructs to generate PN codes 18e, 18l, 18m. When the difference value S16 is larger than the threshold value m, the phase of the received signal in is shifted toward the leading side, so the threshold circuit 17 outputs the PN code 18 to the PN code generator 18.
e, 181 and 18m are output at, for example, 1 /
Instruct to delay by 8 chips. Difference value S16
Is smaller than the threshold value n, the phase of the received signal in is shifted toward the lagging side, so that the PN code generator 18 sets the timing for generating the PN codes 18e, 18l, and 18m by, for example, １ ／ chip. Tell them to proceed. The PN code generator 18 generates the PN code 18 according to the instruction of the threshold circuit 17.
e, 181 and 18m, and
The PN codes 18e and 18l are output to the correlation circuits 12a and 12b, respectively, and the PN code S18m is output to a demodulation circuit (not shown).

As described in the above section, when the noise power is strong and the fading speed is fast, the communication quality is deteriorated regardless of whether the correlation length is long or short. To solve such a problem, in the present embodiment, the complex averaging circuit 1
The average of the absolute values S14a and S14b is averaged by the averaging circuit 15 by following the fading speed by taking the average in 3a and 13b only for the length based on the first number of symbols.
By taking only the length based on the second number of symbols in a and 15b, a process gain is obtained and the accuracy of synchronous tracking is improved. As described above, in the present embodiment, even when the noise power is large, the fading speed is high, and the accuracy of synchronization tracking is deteriorated to cause a malfunction, the length of averaging in the complex averaging circuits 13a and 13b is determined. Shorten to follow the fading speed, and its absolute value S14a,
By averaging S14b by the averaging circuits 15a and 15b, respectively, to obtain a process gain, the accuracy of synchronization tracking is improved, and good communication quality is maintained.
In the embodiment, the threshold circuit 17 includes a PN code generator 18.
To delay or advance the timing of outputting the PN codes 18e, 18l, and 18m by 1/8 chip for one symbol. For example, it is also possible to delay or advance the timing by 1/16 chip. Good.

[0016]

As described above in detail, according to the present invention, the first and second averaging circuits can be used in a poor propagation path environment such as when the noise power is high and the fading speed is high. By following the fading speed by taking only the length based on the first number of symbols, and averaging the absolute values of the first and second complex numbers by the third and fourth averaging circuits by the second averaging circuit. The process gain is ensured by taking only the length based on the number of symbols. Therefore, synchronization tracking can be accurately performed without loss of synchronization.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a synchronization tracking circuit showing an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional synchronization tracking circuit.

FIG. 3 is a time chart of FIG. 2;

FIG. 4 is a configuration diagram of an averaging circuit in FIG. 1;

[Explanation of symbols]

12a, 12b Correlation circuit 13a, 13b, 15a, 15b Averaging circuit 14a, 14b Absolute value circuit 16 Difference circuit 17 Threshold circuit 18 PN code generator (pseudo random signal generator)

Claims (1)

[Claims] 1. A synchronization tracking circuit provided in a receiving station of a mobile communication system based on a spread spectrum system for synchronizing with a received signal, comprising: an in-phase component of the received signal represented by a complex number transmitted through a spatial propagation path. And a first correlation circuit for obtaining a correlation value between the quadrature component and the first pseudo random signal for each symbol representing a unit of the received signal, and an in-phase component and a quadrature component of the received signal and the first pseudo-random signal. A second correlation circuit for obtaining, for each symbol, each correlation value with a second pseudo-random signal whose phase is delayed by one chip with respect to the random signal; and a correlation value output from the first correlation circuit. 1 for
Symbol integration is sequentially performed for a desired first number of symbols, and each integration result is averaged using a transversal filter to obtain a first in-phase component average value and a first quadrature component average value. Averaging circuit, and 1 for each correlation value output from the second correlation circuit.
The integration for symbols is sequentially performed for the first number of symbols, and the integration results are averaged using a transversal filter to obtain a second average value of the in-phase component and a second average value of the quadrature component. An averaging circuit; a first absolute value circuit that calculates an absolute value of a first complex number having the first in-phase component average value and the first quadrature component average value as a real part and an imaginary part, respectively; A second absolute value circuit that calculates an absolute value of a second complex number having a real part and an imaginary part respectively of a second in-phase component average value and the second quadrature component average value; and an absolute value of the first complex number. The integration of one symbol with respect to the value is sequentially performed for the second symbol number larger than the first symbol number, and the respective integration results are averaged using a transversal filter to obtain a first average value. Third
An integration circuit for one symbol is sequentially performed on the absolute value of the second complex number by the number of the second symbols, and each integration result is averaged using a transversal filter. A fourth averaging circuit for obtaining an average value of: a difference circuit for obtaining a difference value between the first average value and the second average value; and a first threshold value preset for the difference value; Comparing a second threshold value smaller than the first threshold value, and outputting a first comparison result when the difference value is larger than the first threshold value;
A second comparison result is output when the difference value is between the first threshold value and the second threshold value, and a third comparison result is output when the difference value is smaller than the second threshold value. And when the second comparison result is output from the threshold circuit, the first pseudo random signal and the second pseudo random signal are generated at a reference timing, and the threshold circuit When the first comparison result is output from
The first pseudo-random signal and the second pseudo-random signal are generated at a later timing than when the comparison result is output, and when the third comparison result is output from the threshold circuit, A pseudo-random signal generator that generates the first pseudo-random signal and the second pseudo-random signal at a timing earlier than when the comparison result of (2) is output. .