JPH1013240A - Circuit and method for serial digital interface signal transmission - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of a deteriorated signal pattern, such as consecutive same codes for a long time in a serial digital interface device for a digital video signal or the like. SOLUTION: Synchronization addition video data 2a are fed to an evaluation signal-generating section 3, which generates an evaluation signal 3a and a DC component shift detection circuit 4 and a consecutive same code detection circuit 5 check a DC component shift and consecutive identical codes. When the check result indicates excess in the permissible shift and consecutive same codes, an invalid packet addition circuit 7 inserts an invalid packed not effecting the video data to synchronization addition video data 6a, delayed by 1H (one horizontal period) by delay circuit 6, to change transmission data. When the shift and consecutive identical codes are within the permissible range, no invalid packet is inserted. An output 7a of the invalid packet addition circuit 7 is fed to a transmission signal-generating section 8, which generates a transmission scrambled NRZ-I signal 8a, and it is sent to a coaxial cable via a coaxial buffer circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial digital interface (SDI) signal transmission circuit and a transmission method used for serial transmission of digital video signals between video equipment for business use, broadcast stations, and the like. The present invention relates to a serial digital interface signal transmitting circuit and a transmitting method for preventing transmission of a serial signal having a biased spectrum.

[0002]

2. Description of the Related Art The specifications for serial transmission of digital video signals between video equipment for business use and broadcast stations are as follows.
MPTE 259M is known. FIG. 8 shows a conventional SMP
It is a block diagram of a serial digital interface (SDI) signal transmission circuit of the TE259M specification. A conventional serial digital interface (SDI) signal transmission circuit 800 includes a synchronization addition circuit 801, a P / S (parallel / serial) conversion circuit 802, and a scramble circuit 8
03, an NRZ-I conversion circuit 804, and a coaxial buffer circuit 805.

A serial digital interface (SD)
I) The signal transmission circuit 800 converts the luminance signal Y and the color difference signals Cb, Cr, which are digitized into 10 bits, into Cb,
Video data 800a arranged in the order of Y, Cr, Y is input. The synchronization adding circuit 801 adds vertical synchronization and horizontal synchronization timing reference signals SAV and EAV to the input video data 800a. As the timing reference signals SAV and EAV, a fixed pattern of 3FF, 000,000 in hexadecimal notation is used.

Video data 80 to which timing reference signals SAV and EAV for vertical synchronization and horizontal synchronization are added
1a is supplied to the parallel / serial conversion circuit 802. The parallel / serial conversion circuit 802 includes timing reference signals SAV and EAV for vertical synchronization and horizontal synchronization.
Is converted to serial data 802a preceding LSB. Serial data 80
2a is supplied to the scramble circuit 803.

FIG. 9 is a block diagram of a scramble circuit. The scramble circuit 803 includes a nine-stage D-type flip-flop circuit 80 operating in synchronization with the bit clock.
3a to 803i and two exclusive OR circuits 80
3j and 803k. This scramble circuit 80
3 indicates that the serial data 802a is G (x) = (x ⁹ + x
⁴ +1) pseudo-randomized by a generator polynomial,
Pseudo-randomized signal (scrambled signal) 803a
Is output.

FIG. 10 is a block diagram of the NRZ-I conversion circuit. The NRZ-I conversion circuit 104 includes a D-type flip-flop circuit 80 operating in synchronization with a bit clock.
4a and an exclusive OR circuit 804b. N
The RZ-I conversion circuit 804 outputs a signal 80 scrambled (pseudo-randomized) by the scramble circuit 803.
3a is subjected to NRZ-I conversion to obtain a scrambled NRZ
-Output the I signal 804a. Pseudorandomization by the generator polynomial G (x) = (x + 1) can be performed by the NRZ-I conversion. Therefore, the scramble circuit 803
And the NRZ-I conversion circuit generate the scrambled NRZ-I signal 804a as G (x) = (x ⁹ + x
^The signal is pseudo-randomized by a generator polynomial of ( ⁴ + 1) (x + 1).

As shown in FIG. 8, the NRZ-I conversion circuit 8
04 scrambled NRZ-I signal 80
4a is power-amplified by a coaxial buffer circuit 805 into a signal of a predetermined voltage level. The 270 Mbit / sec serial digital interface signal 805 a output from the coaxial buffer circuit 805 is output to the output BNC connector 80.
The signal is transmitted to the receiving circuit side via a coaxial cable (not shown) connected to 6.

FIG. 11 is a block diagram of a conventional serial digital interface (SDI) signal receiving circuit conforming to the SMPTE259M specification. A conventional serial digital interface (SDI) signal receiving circuit 900 includes a coaxial equalizing circuit 901, a 0/1 discriminating circuit 902,
Data reproduction circuit 903 and NRZ-I inverse conversion circuit 904
, Descrambling circuit 905 and TRS detecting circuit 90
6 and an S / P (serial / parallel) conversion circuit 907.

[0009] Input 2 to the input BNC connector 908
The 70 Mbit / sec serial digital interface signal 900 a is supplied to the coaxial equalizer 901.
Since the transmission loss of the coaxial cable increases at high frequencies, the waveform of the transmission signal may be degraded due to a decrease in the high frequency components. The coaxial equalization circuit 901 compensates for waveform deterioration due to high-frequency transmission loss of the coaxial cable. The output 901a of the coaxial equalizing circuit 901 is supplied to a 0/1 discriminating circuit 902, and a logic 0/1 is discriminated.

The 0/1 discrimination output 902a is supplied to a clock / data recovery circuit 903. The clock / data recovery circuit 903 operates on a 270 MHz signal synchronized with the serial digital video signal based on the 0/1 discrimination output 902a.
And the received data is reproduced based on the reproduced serial clock. Recovered received data (scrambled NRZ-I signal) 90
3a is supplied to the NRZ-I inverse conversion circuit 904.

The NRZ-I inverse conversion circuit 904 performs an inverse conversion of the NRZ-I conversion performed on the transmission side, and outputs a scrambled (pseudo-randomized) signal 904a. The scrambled (pseudo-randomized) signal 904 a output from the NRZ-I inverse conversion circuit 904 is supplied to an inverse scramble circuit 905. The descrambling circuit 905 descrambles the scrambled (pseudo-randomized) signal 904a, and adds the timing reference signals SAV and EAV to the video data 905a.
Is output. The video data 905a output from the descrambling circuit 905 is supplied to a TRS detection circuit 906.

The TRS detection circuit 906 has a fixed pattern 3FF00000,0 of the timing reference signal SAV / EAV.
00 and generates a timing reference signal SAV / EAV, and serial / parallel converts the serial video data (270 Mbit / sec NRZ data) 906 a from which the fixed pattern 3FF, 000,000 of the timing reference signal SAV / EAV is removed. The signal is supplied to the circuit 907.

[0013] The serial / parallel conversion circuit 907 is provided with a fixed pattern 3F of the timing reference signal SAV / EAV.
The serial video data (270 Mbit / sec NRZ data) from which F, 000,000 has been removed is
Timing reference signal SAV detected by S detection circuit 906
While synchronizing words based on / EAV, it converts and outputs 10-bit, 27 MHz parallel video data 900b.

As described above, in the serial digital interface of the SMPTE259M specification, the luminance signal Y and the color difference signals Cb and Cr digitized into 10 bits are arranged in the order of Cb, Y, Cr and Y, and the timing reference signal S
A parallel signal formed by adding AV and EAV is
Parallel / serial conversion is performed prior to LSB, and further converted to a scrambled NRZ-I signal.
is transmitted as a serial digital video signal of sec.
The serial digital interface (S
DI) allows video signals to be transmitted without degradation. Furthermore, the quality of video in program production has been significantly improved by digital video equipment such as digital VTRs.

In video transmission, the spectrum of the serial signal may be biased depending on the content of the video due to the correlation of the video signal and the like. Therefore, in the serial digital interface (SDI) of the SMPTE259M specification,
The data is pseudo-randomized on the transmitting side of the video signal by using the scramble circuit shown in FIG. 9, thereby preventing the spectrum of the transmitted serial signal from being biased.

In a serial digital interface (SDI) handling 270 Mbit / sec data, an inverting amplifier is frequently used in an analog signal processing circuit.
It is troublesome to always keep in mind the polarity of the signal. Therefore, the SMPTE259M serial digital interface (SDI) adopts the NRZ-I code,
By replacing 0/1 of data with inverted information of 0 → 1, 1 → 0, polarity free is realized.

As described above, in the SMPTE259M serial digital interface (SDI), G
By adopting a scrambled NRZ-I code based on a generator polynomial of (x) = (x ⁹ + x ⁴ +1) (x + 1), it is possible to realize a serial digital interface (SDI) signal having a polarity-free and uniformly distributed spectrum. I have.

[0018]

However, SMP
The following document discloses that a serial digital interface (SDI) conforming to the TE259M specification generates a serial signal having a spectrum bias for a specific video.

"Pathological Check"
Codes for SerialDigital
Interface Systems "by Tak
eoEguchi SMPTE Journal, Au
gust 1992, p553-p558 According to the above-mentioned document, the SDI serial signal for a flat field video signal of color difference signal (C) = 300h (h indicates hexadecimal notation) and luminance signal Y = 198h has a certain constant. As shown in FIG. 12 (a), one horizontal cycle period (correctly, 1440 word periods of the effective image) has a probability.
A serial signal in which one bit is logic 1 and the following 19 bits are logic 0, or as shown in FIG.
A serial digital interface (SDI) signal in which the logic of the signal in FIG. 12A is inverted appears.

A serial digital interface (SD
I) On the signal receiving side, an AC coupling circuit is used for a coaxial equalization circuit or the like. When a pathological signal as shown in FIG. In some cases, distortion occurs in the signal due to the low-frequency cutoff caused by the above, and an error occurs in the received signal.

Also, a serial digital interface (SDI) signal for a flat field video signal having a color difference signal (C) = 200 h and a luminance signal (Y) = 110 h has a certain probability with one horizontal period (precisely valid). As shown in FIG. 13, during a video 1440 word period, a serial digital interface (SD) in which 20 consecutive bits are logical 1 and 20 consecutive bits are logical 0
I) Signal appears.

Serial digital interface (SD
I) On the signal receiving side, since the original 270 MHz serial clock is recovered from the edge information of the received signal by the clock recovery circuit, a pathological signal as shown in FIG. 13 is input to the clock recovery circuit. In this case, the number of changing edges is extremely small, so that a bit slip may occur and an error may occur in a received signal.

The present invention has been made to solve such a problem, and has a serial digital interface (S).
DI) that prevents transmission of pathological serial digital interface (SDI) signals that may interfere with signal transmission.
DI) It is an object to provide a signal transmission circuit.

[0024]

In order to solve the above-mentioned problems, a serial digital interface signal transmission circuit and a transmission method according to the present invention are provided. The continuity is detected, and the data to be transmitted is changed when the DC component deviation is large or when the same code continuation occurs. As a result, it is possible to prevent transmission of a signal having a large DC component shift or a signal in which the same code sequence occurs frequently.

It is desirable to change the data by inserting an invalid packet into the data to be transmitted. This is because data such as video data can be transmitted accurately.

A serial digital interface signal transmission circuit and a transmission method according to the present invention generate two types of serial digital signals based on data to be transmitted,
The DC component shift and the same code continuation of the generated two types of serial digital signals are detected, and the serial digital signal having the smaller DC component shift and the same code continuity is selected and transmitted.

By selecting and transmitting a serial digital signal having a small amount of DC component deviation and the same number of consecutive identical codes, stable data transmission in which erroneous detection on the receiving side is less likely to occur can be realized. Further, the transmission distance can be extended.

It is desirable that the two types of serial digital signals are those in which an invalid packet is inserted and those in which no invalid packet is inserted. This is because data such as video data can be transmitted accurately.

In a circuit for transmitting a scrambled NRZ-I signal generated by converting synchronously added video data obtained by adding synchronous data to video data to serial data, performing scramble processing, and then performing NRZ-I conversion, The DC component shift amount and the same code continuation number of the generated scrambled NRZ-I signal were evaluated, and when the DC component shift amount and the same code continuation number were large, invalid packet data was inserted into the synchronization additional video data. The invalid packet-added scrambled NR generated by converting the invalid packet-added synchronous additional video data into serial data, performing scrambling, and then performing NRZ-I conversion
You may make it transmit a ZI signal.

Further, a scrambled NRZ-I signal and a scrambled NRZ-I signal with an invalid packet added thereto are
A type of scrambled NRZ-I signal is generated, and among these two types of scrambled NRZ-I signals, a DC component deviation amount and a scrambled NRZ-I signal having the smaller number of identical codes are selected. It may be configured to transmit.

[0031]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of a serial digital interface signal transmission circuit according to the present invention. The serial digital interface signal transmission circuit 1 according to the present invention includes a synchronization addition circuit 2, an evaluation signal generation unit 3, a DC component shift detection circuit 4, an identical code continuation detection circuit 5, and 1H (one horizontal period). Delay circuit 6
, An invalid packet adding circuit 7, and a transmission signal generation unit 8
, A coaxial buffer circuit 9 and an output BNC connector 10.

The evaluation signal generator 3 includes a P / S (parallel / serial) conversion circuit 11 and a scramble circuit 12
And an NRZ-I conversion circuit 13. The transmission signal generation unit 8 includes a P / S (parallel / serial) conversion circuit 21.
, A scramble circuit 22, and an NRZ-I conversion circuit 23
And

The serial digital interface signal transmission circuit 1 receives video data 1a in which luminance signals Y and color difference signals Cb and Cr digitized into 10 bits are arranged in the order of Cb, Y, Cr and Y. The synchronization addition circuit 2 applies vertical synchronization and horizontal synchronization timing reference signals SAV and EA to the input video data 1a.
V is added to generate synchronous additional video data 2a.
As the timing reference signals SAV and EAV, 16
A fixed pattern of 3FF, 000,000 is used in hexadecimal notation. The synchronization additional video data 2a is supplied to the evaluation signal generator 3 and the 1H (one horizontal period) delay circuit 6.

The evaluation signal generator 3 converts the synchronization-added video data 2a into serial data, performs scramble processing, and further performs NRZ-I conversion to generate a scrambled NRZ-I signal 3a. The synchronous additional video data 2a is supplied to a P / S (parallel / serial) conversion circuit 11
The P / S (parallel / serial) conversion circuit 11 converts the data into serial data 11a and supplies the serial data 11a to the scramble circuit 12.

As shown in FIG. 9, the scramble circuit 12 has nine stages of D-type flip-flops 803a to 803i operating in synchronization with a bit clock (not shown).
It consists of two exclusive OR circuits 803j and 803k. This scramble circuit 12 is used for serial data 1
The 1a pseudo randomized by the generator polynomial of ^{G (x) = (x 9} + x 4 +1), generates a pseudo randomization (scrambled) signal 12a. The pseudo-randomized (scrambled) signal 12 a is supplied to the NRZ-I conversion circuit 13.

As shown in FIG. 10, the NRZ-I conversion circuit 13 comprises a D-type flip-flop 804a operating in synchronization with a bit clock (not shown) and an exclusive OR circuit 804b. The NRZ-I conversion circuit 13 performs NRZ-I conversion on the pseudo-randomized (scrambled) signal 12a to generate a scrambled NRZ-I signal 3a. By the NRZ-I conversion, G (x) =
Pseudorandomization is performed by the generator polynomial (x + 1).

Therefore, the evaluation signal generation unit 3
G (x) = (x ⁹ + x ⁴ +1)
A pseudo-random scrambled NRZ-I signal 3a is generated by a generator polynomial (x + 1).

The scrambled NRZ-I signal 3a generated by the evaluation signal generator 3 is supplied to a DC component shift detector 4
And supplied to the same-code continuation detection circuit 5. The DC component shift detection circuit 4 outputs a scrambled NR signal every one horizontal cycle.
The DC component shift amount of the ZI signal 3a is obtained, and if the obtained DC component shift amount exceeds a preset allowable shift amount, a DC component shift detection signal 4a is output. The DC component shift detection signal 4a is supplied to the invalid packet adding circuit 7.

The same code continuation detection circuit 5 counts the number of the same code continuations of the scrambled NRZ-I signal 3a for each horizontal cycle, and when the coefficiented number of the same code continuations exceeds a preset allowable number of continuations. Is the same sign continuous detection signal 5a
Is output. The same-code consecutive detection signal 5a is supplied to the invalid packet adding circuit 7.

In FIG. 1, the DC component shift detection signal 4
a, the same sign continuous detection signal 5a is supplied to the invalid packet adding circuit 7, but the logical sum signal of the DC component shift detection signal 4a and the same sign continuous detection signal 5a is supplied to the invalid packet adding circuit 7. It is good also as composition supplied to.

The 1H (one horizontal period) delay circuit 6 delays the synchronization-added video data 2a by one horizontal period and outputs the delayed synchronization-added video data 6a. The delay synchronization additional video data 6a is supplied to the invalid packet adding circuit 7.

When the DC component shift detection signal 4a or the same code continuation detection signal 5a is supplied, the invalid packet adding circuit 7 inserts and outputs an invalid packet to the delay synchronization added video data 6a. When neither the DC component shift detection signal 4a nor the same code continuation detection signal 5a is supplied, the invalid packet adding circuit 7 outputs the delay synchronization added video data 6a as it is.

The data (delay synchronization additional video data or delay synchronization additional video data into which the invalid packet is inserted) 7 a output from the invalid packet adding circuit 7 is supplied to the transmission signal generation unit 8. The configuration of the transmission signal generator 8 is the same as that of the evaluation signal generator 3. The data 7a output from the invalid packet adding circuit 7 is converted into serial data 21a by a P / S (parallel / serial) conversion circuit 11, and the pseudo-random signal 2 is converted by a scramble circuit 22.
2a is generated, and the NRZ-I conversion circuit 23 generates the NRZ-I
The converted scrambled NRZ-I signal 8 for transmission
a is output.

The transmission scrambled NRZ-I signal 8a output from the transmission signal generator 8 is supplied to the output BNC connector 10 via the coaxial buffer circuit 9, and is connected to the output BNC connector 10. The signal is transmitted to a receiving circuit (not shown) via a coaxial cable (not shown).

In the SMPTE 259M, horizontal and vertical blanking periods of a video signal are used as an auxiliary signal area, and various data including an audio signal can be transmitted as an auxiliary signal packet to this auxiliary signal area. Details of the auxiliary signal packet are standardized in SMPTE 291M. An invalid packet is defined in SMPTE 291M. An invalid packet is a packet that does not transmit any information while being in the form of an auxiliary signal packet. Therefore, the information transmission of various data including video and audio is not affected at all by the existence of the invalid packet.

The pathological patterns shown in FIGS. 12 and 13 occur when data input to the scramble circuit is certain data. At this time, if the data input to the scramble circuit differs even by one bit,
The output pattern is completely different from the original nature of the scramble circuit, and the pathological patterns shown in FIGS. 12 and 13 no longer occur. Therefore, the occurrence of the pathological pattern shown in FIGS. 12 and 13 is detected before transmission, and when the pathological pattern occurs, a part of the video data supplied to the scramble circuit is changed. The occurrence of a pathological pattern can be prevented.

Therefore, in the serial digital interface signal transmission circuit 1 shown in FIG. 1, the scrambled NRZ-I signal 3a is generated by the evaluation signal generator 3 and the generated scrambled NRZ-I signal 3a is generated. Whether the pathological pattern is detected is detected by the DC component shift detection circuit 4 and the same code continuation detection circuit 5, and the synchronization-added video data is detected for the time required to detect the pathological pattern. 2a is delayed by a 1H (one horizontal period) delay circuit 6, and the synchronization-added video data 2a is converted to a scrambled NRZ signal.
When the DC component shift detection circuit 4 and the same code continuation detection circuit 5 detect that a pathological pattern is generated upon conversion to the -I signal, the synchronization-added video data 2a before scramble processing is performed. By changing some of the data, a pathological pattern is prevented from occurring.

In the serial digital interface signal transmission circuit 1 shown in FIG.
By inserting an invalid packet into the auxiliary signal area corresponding to the horizontal and vertical blanking periods of the video signal and partially changing the data of the synchronization-added video data supplied to the transmission signal generation unit 8, a pathological pattern occurs. Is prevented. Therefore, within the scope of the SMPTE259M standard,
The occurrence of a pathological pattern can be prevented without substantially affecting information transmission of the serial digital interface.

It is to be noted that, besides inserting an invalid packet, the value of the luminance data or the color difference data is changed to, for example, +1 or −1
By changing the value of the luminance data or the color difference data, for example, the occurrence of a pathological pattern may be prevented.

FIG. 1 shows a configuration in which two types of detection circuits are provided, that is, a DC component deviation detection circuit 4 and an identical code continuation detection circuit 5. However, either one of the detection circuits is provided, and the DC component deviation detection circuit is provided. Alternatively, the occurrence of a pathological pattern may be prevented based on the detection of consecutive identical codes. With such a configuration, the circuit scale of the serial digital interface signal transmission circuit 1 can be reduced.

FIG. 2 is a block diagram showing a specific example of the DC component shift detection circuit. DC component shift detection circuit 4
Comprises a counter circuit 41, a comparison circuit 42, and a set / reset flip-flop (RS-FF) 43. The counter circuit 41 is configured using a 15-bit up / down counter. This counter circuit 41
Determines the logic level of the scrambled NRD-I signal 3a in synchronization with the 270 MHz clock which is the bit clock (not shown) of the scrambled NRD-I signal 3a. In the case of 1, count up by 1
When the logical level of the RD-I signal 3a is 0, the countdown is performed by one. This counter circuit 41
Is configured to reset the count value to 0 based on a horizontal cycle reset signal HRS supplied at one horizontal cycle interval from a reset signal generation circuit (not shown).

Therefore, the counter circuit 41 performs an operation of counting up by 1 if the logical level of the scrambled NRD-I signal 3a is 1 and counting down by 1 if the logical level is 0. H
Repeat until RS is supplied. Here, the cycle of the horizontal cycle reset signal HRS is 17160 clocks (858 × 2 × 10) of a 270 MHz bit clock. As a result, the 15-bit output of the 15-bit up / down counter that constitutes the counter circuit 41 is output from the scrambled NRD-I after the horizontal cycle reset signal HRS.
The cumulative DC component of the signal 3a is shown in 2's complement format.

The count range of the accumulated DC component during the 17160 clock period takes the maximum value and the minimum value when the logic level of the scrambled NRD-I signal 3a is all 1 or 0, respectively. -171
It will be 60. However, in the SMPTE259M serial digital interface, since the prohibition code is provided in the video signal, the signal shown in FIG. 12 is the worst condition, and its value is 858 × (19-1) = 15444. The range actually counted is +15444 to -1.
5444. Therefore, counting can be performed in a two's complement format with a 15-bit up / down counter.

The accumulated DC component value 41a for one horizontal period counted by the counter circuit 41 is supplied to the comparison circuit 42. The comparing circuit 42 compares the accumulated DC component value 41a with a preset allowable shift amount, and when the cumulative DC component value 41a exceeds the allowable shift amount, outputs the allowable shift amount excess detection signal 42a. Occur. Here, the allowable shift amount is the accumulated DC component value under the worst condition, +15444 to -15444.
For example, +1544 to -1 which is a range of 10%.
544 are set. Therefore, when the cumulative DC component value 41a for each horizontal cycle exceeds the range of +15444 to -15444, the comparison circuit 42 outputs the allowable deviation amount excess detection signal 42a.

The allowable deviation amount excess detection signal 42a is supplied to the set input terminal S of the set / reset flip-flop (RS-FF) 43 to set the set / reset flip-flop (RS-FF) 43 to the set state. Thereby, the set-reset type flip-flop (RS-F
F) A DC component deviation detection signal 4a of logic level 1 is output from the Q output of 43. The reset input R of the set / reset flip-flop (RS-FF) 43 includes:
The horizontal cycle reset signal HRS is supplied, and the output of the DC component deviation detection signal 4a once output is stopped (reset) by the next horizontal cycle reset signal HRS.

FIG. 3 is a block diagram showing a specific example of the same code consecutive detection circuit. The same sign continuous detection circuit 5 shown in FIG. 3 detects the inversion of the logic level of the scrambled NRZ-I signal 3a and generates a reset pulse signal 51a accompanying the inversion of the logic level.
1 and the bit clock CLK of the scrambled NRZ-I signal 3a
A counter circuit 52 that increments (+1 counts) every time, a logical sum circuit 53 that generates a logical sum output 53a of a reset pulse signal 51a and a horizontal cycle reset signal HRS associated with a logical level inversion, and a count value of the counter circuit 52 52
a is compared with the allowable continuous number of the same code, and the count value 52
When a exceeds the allowable continuous number, a comparison circuit 54 for generating an allowable continuous number excess detection signal 54a, and a set-reset type which is set by the allowable continuous number excess detection signal 54a and reset by the horizontal period reset signal HRS. And a flip-flop circuit (RS-FF) 55.

By supplying the OR output 53a of the OR circuit 53 to the reset input terminal 52b of the counter circuit 52, the counter value 52a is reset to 0 by the horizontal cycle reset signal HRS and the reset pulse signal 51a accompanying the logic level inversion. I am trying to do it. The logic level inversion detection circuit 51 outputs the scrambled NRZ-I signal 3
When the logic level of a is inverted from 0 to 1 or from 1 to 0, the reset pulse signal 51a accompanying the logic level inversion
Occurs. The reset pulse signal 51a accompanying the inversion of the logic level is sent to the counter circuit 5 via the OR circuit 53.
The reset counter 52b is supplied to the reset input terminal 52b to reset the incremented counter value for each bit clock CLK to zero. Therefore, since the counter circuit 52 advances by every bit clock CLK until a new reset signal is supplied, the counter value 52a of the counter circuit 52 has the same number of consecutive numbers.

The comparison circuit 54 compares a counter value 52a indicating the number of consecutive identical codes with a preset allowable number of consecutive times. If the counter value 52a exceeds the allowable number of consecutive times, the comparator circuit 54 outputs an excess allowable number of continuous detection signal 54a. Occur. The set-reset type flip-flop circuit (RS-FF) 55 outputs an allowable continuous number excess detection signal 54 supplied to the set input terminal S.
The Q output is set to logic level 1 by a, and the same code continuation detection signal 5a indicating that the same code has continued for a predetermined number or more is output. Since the horizontal cycle reset signal HRS is supplied to the reset input terminal R of the set-reset type flip-flop circuit (RS-FF) 55,
The same-code consecutive detection signal 5a is reset every horizontal cycle. The horizontal cycle reset signal HRS is output from the OR circuit 5.
3, the counter value 52a is also reset every horizontal cycle.

Therefore, the continuous number of the same code is counted in each horizontal cycle, and when the number exceeds the allowable continuous number, the same code continuous detection signal 5a is output. The number of consecutive identical codes becomes maximum when the pathological pattern shown in FIG. 12 occurs. Accordingly, for example, the same code continuous number 15 corresponding to about 80% of the same code continuous number 19 at the time of occurrence of the pathological pattern shown in FIG. 12 is set as the allowable continuous number.

In FIG. 3, the scrambled NRZ-I
Scrambled NRZ-I signal 3 with signal 3a as input
The circuit configuration for counting the number of consecutive identical codes of a has been described.
Pseudorandomization (scramble) before RZ-I conversion
The signal 12a may be used as an input to count the number of consecutive identical codes. Alternatively, instead of counting the number of consecutive identical codes, the cumulative number of identical codes may be counted, and if the cumulative number of identical codes exceeds a predetermined number, it may be determined that the pattern is pathological. .

FIG. 4 is a block diagram showing another specific example of the same code consecutive detection circuit. 4 receives the pseudo-randomized (scrambled) signal 12a before the NRZ-I conversion, counts the cumulative number of the same code, and the cumulative number of the same code exceeds a predetermined number. In such a case, the same code consecutive detection output is generated. The same-code continuation detecting circuit 5A for detecting the continuation of the same code based on the accumulated number of the same code includes an up-counter circuit 56 and a comparison circuit 57.

The up counter circuit 56 is configured using a 14-bit up counter. The up-counter circuit 56 has a bit clock CLK of 270 MHz.
Pseudorandomized (scrambled) signal 12a
The logical level of the pseudo randomized (scrambled) signal 12a is counted up by 1 when the logical level is 0, and the counter value is held when the logical level of the pseudo randomized (scrambled) signal 12a is 1 To
It is configured to repeat the period (858 × 2 × 10 = 17160 clocks) until the next horizontal cycle reset signal HRS is supplied.

By this counting operation, the 14-bit count output value 56a of the up-counter circuit 56 changes the logic level of the pseudo-randomized (scrambled) signal 12a after the supply of the horizontal cycle reset signal HRS to 0.
Is the cumulative number of When the logic level of the pseudo-randomized (scrambled) signal 12a is 0 over the entire period of 17160 clocks, the same code accumulation number becomes the maximum value 171.
It will be 60. However, in the serial digital interface of the SMPTE259M specification, the prohibition code is provided for the video signal, so the signal shown in FIG. 12 is the worst condition, and the value is 858 × 19 = 16302, so that the 14-bit signal is used. It can be counted by a counter.

The comparison circuit 57 includes an up counter circuit 56
The count output value (same code cumulative number) 56a is compared with a preset allowable cumulative number. If the count output value (same code cumulative number) 56a exceeds the allowable cumulative number, the same code continuation detection signal 5a Is output. Here, the allowable cumulative number is 13041 which is, for example, 80% of the maximum value 17160 of the same code cumulative number. When the count output value (same code cumulative number) 56a exceeds the allowable cumulative number (for example, 13041), it is determined that a large number of consecutive identical codes have occurred, and the identical code consecutive detection signal 5a is output. .

FIG. 5 is a block diagram of the same code continuity detecting circuit which counts the number of times the same code continues for a predetermined number or more and detects the occurrence of the same code continuation frequently based on the number of times the same code continues. The same code continuation detection circuit 5B shown in FIG. 5 is the same as the same code continuation number counting circuit 58 and the same code continuation detection comparison circuit 59 that determines that the same code continuation number exceeds a preset allowable number. It comprises a code consecutive occurrence count circuit 60, and a same code consecutive occurrence detection comparison circuit 61 which outputs the same code consecutive detection signal when the number of consecutive identical codes exceeds a preset allowable number of occurrences.

The same code continuation number counting circuit 58 is constituted by using a 5-bit up counter. The same code continuation number counting circuit 58 determines the logical level of the pseudo-randomized (scrambled) signal 12a based on the 270 MHz bit clock CLK, and if the logical level of the pseudo-randomized (scrambled) signal 12a is 0, 1 Count up and generate a pseudo-randomized (scrambled) signal 12
When the logic level of a is 1, the counter value is reset to 0. Therefore, the same code consecutive number counting circuit 58 outputs the consecutive number 58a of the logic level 0 of the pseudo-randomized (scrambled) signal 12a.

The same code continuation detection comparing circuit 59 compares the same code continuation number 58a output from the same code continuation number counting circuit 58 with a preset allowable continuation number. If the number exceeds the allowable number, an allowable continuous number excess signal 59a is generated. In the pseudo randomized (scrambled) signal 12a of the SMPTE259M specification, when the signal shown in FIG.
And the maximum. Therefore, 15 which is about 80% of the maximum value 19 is set as the allowable continuous number.

The same code consecutive occurrence counting circuit 60 counts the number of occurrences of the allowable consecutive number excess signal 59a output from the same code consecutive detection comparing circuit 59. The same-code consecutive occurrence count circuit 60 outputs the horizontal cycle reset signal H
The count value is reset to 0 based on RS. Therefore, the same code continuation frequency counting circuit 56 determines that the number of continuations of the logic level 0 is 1 in one horizontal cycle period.
The number of occurrences of exceeding 5 is counted, and the counted number of occurrences 60a of consecutive identical codes is output.

The comparison circuit 61 for detecting consecutive occurrences of the same code is
The same-code consecutive occurrence count 60a output from the same-code consecutive occurrence count circuit 60 is compared with a preset allowable number of occurrences. If the same-code consecutive occurrence count 60a exceeds the allowable number of occurrences, the same code is output. The detection signal 5a is output. Here, the allowable number of occurrences is set to 42 which is, for example, about 5% of the whole (858).

Therefore, the same code continuity detecting circuit 5B shown in FIG. 5 is such that when the number of occurrences of a signal whose continuation of the same code exceeds 15 exceeds 42, a large number of continuations of the same code occur. And the same sign continuous detection signal 5
generates a.

In FIG. 5, the pseudo-randomized (scrambled) signal 12a before the NRZ-I conversion is supplied to the same code continuous detection circuit 5B, and the pseudo-randomized (scrambled) signal before the NRZ-I conversion is performed. Although the configuration for detecting the same code continuation of 12a has been shown, the scrambled NRZ-I signal 3a after the NRZ-I conversion is supplied to the same code continuation detection circuit 5B, and the scrambled NRZ-I signal 3a
May be configured to detect the same code continuation.

FIG. 6 is a block diagram of another serial digital interface signal transmission circuit according to the present invention. The serial digital interface signal transmission circuit 100 shown in FIG. 6 prepares a data sequence in which an invalid packet is not inserted and a data sequence in which an invalid packet is inserted, and compares the DC component shift and the same code continuation of both. By selecting and transmitting the smaller of the DC component deviation and the same code continuation, a signal in which the DC component deviation and the same code continuation are prevented is transmitted.

After the video data 1 a is added with the timing reference data SAV / EAV by the synchronization adding circuit 2, it is input to the two transmission signal generation units 200 and 300. The transmission signal generation unit 200 includes a P / S (parallel / serial) conversion circuit 201, a scramble circuit 202, and an NRZ-I conversion circuit 203, similarly to the evaluation signal generation unit 3 shown in FIG. Thus, a scrambled NRZ-I signal 200a to which no invalid packet is inserted is generated. The scrambled NRZ-I signal 200a into which no invalid packet is inserted is supplied to one input terminal 40 of the selection circuit 400 via a 1H (one horizontal period) delay circuit 204.
0a. The scrambled NRZ-I signal 200a into which no invalid packet is inserted is supplied to the DC component shift amount detection circuit 501 and the same code continuation number detection circuit 60.
1 is supplied.

The DC component shift amount detection circuit 501 obtains the DC component shift amount of the scrambled NRZ-I signal 200a in which no invalid packet is inserted for each horizontal cycle, and calculates the DC component shift amount 501a. It is supplied to the comparison circuit 700. Note that the DC component shift amount detection circuit 501 temporarily stores the value when the DC component shift amount becomes the maximum, and supplies the temporarily stored maximum DC component shift amount to the comparison circuit 700. You may.

The same code continuation number detection circuit 601 detects the same code continuation number of the scrambled NRZ-I signal 200a into which no invalid packet is inserted, and supplies the detected same code continuation number 601a to the comparison circuit 700. In addition,
The same code continuation number detection circuit 601 determines that the same code continuation has occurred when the number of continuations of the same code exceeds, for example, 15, and counts the number of occurrences of the same code continuation within one horizontal period. The number of occurrences of the same code consecutive
0 may be supplied.

The other invalid packet insertion transmission signal generator 3
00 denotes an invalid packet adding circuit 301 for inserting invalid packet data into the synchronous additional video data 2a, a P / S (parallel / serial) converting circuit 302 for converting video data with the invalid packet inserted into serial data,
A scramble circuit 303 that performs scramble processing on serial data and an NRZ-I conversion circuit 304 that performs NRZ-I conversion on the scrambled serial data to generate a scrambled NRZ-I signal 300a. Scrambled NRZ with invalid packet inserted
-I signal 300a is a 1H (one horizontal period) delay circuit 30
5 to the other input terminal 400b of the selection circuit 400. The scrambled NRZ-I signal 300a into which the invalid packet has been inserted is supplied to the DC component deviation detection circuit 5
02 and the same code continuation number detection circuit 602.

The DC component deviation amount detection circuit 502 outputs the scrambled NRZ-I signal 30 with the invalid packet inserted.
The DC component shift amount of 0a is obtained for each horizontal cycle, and the obtained DC component shift amount 502a is supplied to the comparison circuit 700. Note that the DC component shift amount detection circuit 502 temporarily stores the value when the DC component shift amount becomes the maximum, and supplies the temporarily stored maximum DC component shift amount to the comparison circuit 700. You may.

The same code continuation number detection circuit 602 outputs the scrambled NRZ-I signal 30 with the invalid packet inserted.
The same code consecutive number of 0a is detected, and the detected same code consecutive number 602a is supplied to the comparison circuit 700. The same code continuation number detection circuit 602 determines that the same code continuation has occurred when the number of continuations of the same code exceeds, for example, 15, and counts the number of occurrences of the same code continuation within one horizontal period. , May be supplied to the comparison circuit 700.

The comparison circuit 700 compares the DC component deviation amounts 501a and 502a of the two types of scrambled NRZ-I signals 200a and 300a, and also compares the same code consecutive numbers 601a and 602a of the two types of transmission signals. hand,
A selection command signal 700a for designating the smaller of the DC component deviation amount and the number of consecutive identical codes is supplied to the selection circuit 400.

In the case where the same code consecutive number detection circuits 601 and 602 sequentially output the result of detecting the same code consecutive number,
The comparison circuit 700 counts the number of consecutive identical codes sequentially output as 1
A temporary storage circuit that temporarily stores the data over a horizontal period, and an arithmetic circuit that calculates the fitness as a transmission signal based on the continuous number of a series of identical codes temporarily stored in the temporary storage circuit. A signal to be transmitted is selected based on the obtained degree of suitability as a transmission signal. Also, for example, only the consecutive number of consecutive identical codes exceeding 15 is extracted from the consecutive number of consecutive identical codes temporarily stored in the temporary storage circuit, and the number of occurrences of consecutive identical codes exceeding 15 is counted, for example. A signal to be transmitted may be selected based on the counted number of occurrences.

The selection circuit 400 has a selection command signal 700a
Scrambled NRZ-I signal 20 specified by
The delay signals 204a and 305a of 0a and 300a are selected and supplied to the coaxial buffer circuit 9. As a result, the DC signal deviation amount and the transmission signal having the smaller number of consecutive identical codes are transmitted to a receiving circuit (not shown) via the output BNC connector 10.

The comparison circuit 700 weights the DC component shift amount and the same code continuation number, respectively, to obtain two types of scrambled NRZ-I signals 200a, 3
The transmission suitability of 00a may be determined, and a signal to be transmitted may be selected based on the determined transmission suitability.

In FIG. 6, the DC component shift amount detection circuits 501 and 502 and the same code continuation number detection circuits 601 and 60 are used.
2 shows the configuration in which two types of detection circuits are provided. However, any one type of detection circuit is provided, and a signal to be transmitted based on the comparison result of the DC component shift amount or the comparison result of the same code continuation number is provided. May be selected. With such a configuration, the circuit scale of the serial digital interface signal transmission circuit 100 can be reduced.

In FIG. 6, each detection circuit 501, 50
2, 601 and 602, the measurement data of the DC component deviation amount and the same number of consecutive codes are supplied, and the comparison circuit compares and judges the measurement data to select a signal to be transmitted. Circuits 501, 502, 601, 60
2 is configured to output whether or not the deviation amount of the DC component exceeds the allowable deviation amount and whether or not the continuous number of the same code exceeds the allowable continuous number. Alternatively, the signal to be transmitted may be selected based on whether or not the allowable continuous number is satisfied.

Further, FIG. 6 shows a configuration in which the same code consecutive number is detected based on scrambled NRZ-I converted signals 200a and 300a after NRZ-I conversion.
The configuration may be such that the same code consecutive number is detected based on the scrambled signal before NRZ-I conversion.

FIG. 7 is a block diagram of a DC component shift amount detection circuit for detecting the maximum value of the DC component shift amount. The DC component shift amount detection circuit 700 includes an up / down counter circuit 701, an absolute value conversion circuit 702,
It comprises a comparison circuit 703 and a maximum value register 704.

The up / down counter circuit 701 has 15
It is configured using a bit up / down counter.
The count value of the up / down counter circuit 701 is reset to 0 by the horizontal cycle reset signal HRS. The up / down counter circuit 701 determines the logic level of the scrambled NRZ-I signal 700a based on the bit clock CLK, and counts up by 1 if the logic level is 1, and counts down by 1 if the logic level is 0. The operation is changed to the next horizontal cycle reset signal HR.
Period until S is supplied (858 × 2 × 10 = 171)
(60 clocks) is repeated. By this up / down counting operation, the 15-bit count output value 701a of the up / down counter circuit 701 becomes the accumulated DC component of the scrambled NRZ-I signal 700a after the reset of the count value based on the horizontal cycle reset signal HRS by two. It is shown in complement format.

The counting range of the accumulated DC component during the 17160 clock period takes the maximum value and the minimum value when the logic level of the scrambled NRZ-I signal 700a is all 1 and all 0, respectively. -1
7160. However, in the serial digital interface of the SMPTE259M specification, the prohibition code is provided for the video signal, so the signal shown in FIG. 12 is the worst condition, and its value is 858 × (19−
1) = 15444, the range of the accumulated DC component that can actually occur is +15444 to -15444, and 1
A 5-bit up / down counter enables counting in 2's complement format.

The absolute value conversion circuit 702 outputs the most significant bit (M) of the 15-bit count output value (cumulative DC component value) 701a output from the up / down counter circuit 701.
If SB) is 0, the lower 14 bits are output as is,
If the most significant bit (MSB) is 1, 10 in binary notation
By outputting a value obtained by subtracting the lower 14 bits from 000000000 (4000 in hexadecimal notation), the accumulated DC component value of the 15-bit 2's complement format is converted into a 14-bit absolute value.

The comparison circuit 703 includes an absolute value conversion circuit 702
Is compared with the stored value 704a of the maximum value register 704. If the absolute value 702a of the cumulative DC component is larger than the stored value 704a of the maximum value register 704, the cumulative DC component The absolute value of 7
02a is stored in the maximum value register 704 (update of the stored value of the maximum value register 704).
Is the absolute value 702a of the accumulated DC component.
If the value is larger than the value stored in the maximum value register 704,
04a is held. The maximum value register 704 clears the stored value of the maximum value register 704 to 0 based on the horizontal cycle reset signal HRS.

Therefore, from the maximum value register 704, the maximum value 70 of the absolute value of the accumulated DC component for each horizontal cycle
4a is output. Therefore, the serial digital interface signal transmission circuit calculates the maximum value 704a of the accumulated DC component.
To determine how much the DC component of the scrambled NRZ-I signal (serial digital interface signal) has deviated, based on the It is possible to prevent the transfer from becoming large.

The embodiment of the present invention employs SMPTE259
Although the transmission circuit and the transmission method of the serial digital interface signal of the component video signal according to the M specification have been described, the transmission circuit and the transmission method according to the present invention are also applied to the serial digital interface signal of the composite video signal of the NTSC or PAL system. be able to.

Although the serial digital interface for video signals has been described, the present invention can be applied not only to video signals but also to data transmission systems such as SDDI. Although data transmission using a coaxial cable has been described, the present invention can be applied to other transmission systems such as optical fiber and wireless communication.

[0094]

As described above, the serial digital interface signal transmission circuit and the transmission method according to the present invention detect the DC component shift and the same code continuation of a serial digital signal generated based on data to be transmitted. When the DC component deviation is large or when the same code sequence occurs, the data to be transmitted is changed. Therefore, it is possible to prevent the transmission of a signal having a large DC component deviation amount or the same code consecutive number.

By changing the data by inserting an invalid packet into the data to be transmitted, the data can be transmitted without changing the contents of the data to be transmitted.

A serial digital interface signal transmitting circuit and a transmitting method according to the present invention generate two types of serial digital signals based on data to be transmitted,
The DC component deviation and the same code continuation of the two types of generated serial digital signals are detected, and the serial digital signal with the smaller DC component deviation and the same code continuation is selected and transmitted. It is possible to transmit a serial digital signal with a smaller amount of shift and the same number of consecutive codes. Therefore, stable data transmission in which erroneous detection is less likely to occur on the receiving side is possible. Further, the transmission distance can be extended.

[Brief description of the drawings]

FIG. 1 is a block diagram of a serial digital interface signal transmission circuit according to the present invention.

FIG. 2 is a block diagram showing a specific example of a DC component deviation detection circuit.

FIG. 3 is a block diagram showing a specific example of the same code consecutive detection circuit.

FIG. 4 is a block diagram showing another specific example of the same code continuation detection circuit.

FIG. 5 is a block diagram of a same-code continuation detecting circuit configured to count the number of times that the same code continues for a predetermined number or more, and to detect the same code continuation frequently based on the number of times the same code is continuously generated.

FIG. 6 is a block diagram of another serial digital interface signal transmission circuit according to the present invention.

FIG. 7 is a block diagram of a DC component deviation detection circuit configured to detect the maximum value of the DC component deviation.

FIG. 8 is a block diagram of a conventional serial digital interface (SDI) signal transmission circuit of the SMPTE259M specification.

FIG. 9 is a block diagram of a scramble circuit.

FIG. 10 is a block diagram of an NRZ-I conversion circuit.

FIG. 11 is a block diagram of a conventional serial digital interface (SDI) signal receiving circuit of the SMPTE259M specification.

FIG. 12 is an explanatory diagram showing a waveform of a pathological serial digital interface signal (1:19).

FIG. 13 is an explanatory diagram showing a waveform of a pathological serial digital interface signal (20:20).

[Description of Signs] 1,100 serial digital interface signal transmission circuit, 2 synchronization addition circuit, 3 evaluation signal generation unit, 4
DC component shift detection circuit, 5, 5A, 5B same-code continuation detection circuit, 6, 204, 305 1H (1 horizontal cycle) delay circuit, 7, 301 invalid packet addition circuit, 8 transmission signal generation unit, 200 transmission signal Generation unit (first transmission signal generation unit), 300 invalid packet insertion transmission signal generation unit (first transmission signal generation unit), 400 selection circuit, 50
1,502,700 DC component shift amount detection circuit, 60
1,602 Same code consecutive number detection circuit

Claims (41)

[Claims] 1. A serial digital interface signal transmission circuit for converting data to be transmitted into a serial digital signal and transmitting the serial digital signal, wherein the serial digital interface detects that the DC component deviation of the serial digital signal exceeds a preset allowable deviation amount. A DC component shift detection circuit, and a data change circuit that changes the data before conversion to the serial digital signal based on the DC component shift detection output of the DC component shift detection circuit, When the shift detection circuit detects that the DC component shift of the serial digital signal exceeds the allowable shift amount, the data changed by the data change circuit is converted into a serial digital signal and transmitted. A serial digital interface signal transmission circuit characterized by the above-mentioned. 2. The serial digital signal according to claim 1, wherein the serial digital signal is a scrambled NRZ-I signal generated by performing NRZ-I conversion after performing scramble processing on the data. Interface signal transmission circuit. 3. The serial digital interface signal transmission circuit according to claim 1, wherein said data change circuit is an invalid packet adding circuit for inserting invalid packet data into said data to be transmitted. 4. A serial digital interface signal transmission circuit for converting data to be transmitted into a serial digital signal and transmitting the serial digital signal, wherein the serial digital signal detects that the number of consecutive identical codes of the serial digital signal exceeds a preset allowable number of consecutive signals. An identical code continuity detection circuit; and a data change circuit that changes the data before conversion to the serial digital signal based on the identical code continuation detection output of the same code continuation detection circuit. When it is detected that the number of consecutive identical codes of the serial digital signal exceeds the allowable number of consecutive signals, the data changed by the data changing circuit is converted into a serial digital signal and transmitted. Interface signal transmission circuit. 5. The serial digital signal according to claim 4, wherein the serial digital signal is a scrambled NRZ-I signal generated by performing NRZ-I conversion after performing scramble processing on the data. Interface signal transmission circuit. 6. The serial digital interface signal transmission circuit according to claim 4, wherein said data change circuit is an invalid packet adding circuit for inserting invalid packet data into said data to be transmitted. 7. A serial digital interface signal transmitting circuit for converting data to be transmitted into a serial digital signal and transmitting the serial digital signal, wherein the serial digital interface detects that the DC component deviation of the serial digital signal exceeds a preset allowable deviation amount. A DC component deviation detection circuit, a DC component deviation detection circuit for detecting that the same code continuation number of the serial digital signal has exceeded a preset allowable number, and a DC component deviation detection circuit of the DC component deviation detection circuit. A data change circuit that changes the data before conversion to the serial digital signal based on the shift detection output or the same sign continuation detection output of the same sign continuation detection circuit. If it is detected that the DC component deviation of the digital signal exceeds the allowable deviation amount, or When it is detected by the circuit that the number of consecutive identical codes of the serial digital signal exceeds the allowable consecutive number, the data changed by the data changing circuit is converted into a serial digital signal and transmitted. Serial digital interface signal transmission circuit. 8. The serial digital signal according to claim 7, wherein the serial digital signal is a scrambled NRZ-I signal generated by performing NRZ-I conversion after performing scramble processing on the data. Interface signal transmission circuit. 9. The serial digital interface signal transmission circuit according to claim 7, wherein said data change circuit is an invalid packet adding circuit for inserting invalid packet data into said data to be transmitted. 10. A serial digital interface signal transmitting circuit for transmitting a scrambled NRZ-I signal generated by subjecting video data to scramble processing and then performing NRZ-I conversion, comprising: A DC component deviation detection circuit for detecting that the component deviation exceeds a preset allowable deviation amount; and an invalid packet addition circuit for inserting an invalid packet into the video data to generate invalid packet additional data. When the DC component shift detection circuit detects that the DC component shift of the scrambled NRZ-I conversion data exceeds the allowable shift amount, the invalid packet generated by the invalid packet adding circuit is used. Invalid packets obtained by scrambling the additional video data and performing NRZ-I conversion Scrambled NRZ- of the additional video data
A serial digital interface signal transmission circuit configured to transmit an I signal. 11. A scrambled N obtained by subjecting video data to scramble processing and then performing NRZ-I conversion.
A serial digital interface signal transmitting circuit for transmitting an RZ-I signal, wherein the same code continuous detection circuit detects that the same code continuous number of the scrambled NRZ-I signal exceeds a preset allowable continuous number; An invalid packet adding circuit that inserts invalid packets into data to generate invalid packet added video data; and the same code continuity detection circuit causes the same code continuation number of the scrambled NRZ-I signal to exceed an allowable continuation number. When it is detected that the invalid packet added video data generated by the invalid packet adding circuit is scrambled, the NRZ-I converted scrambled NRZ-I signal of the invalid packet added video data is transmitted. Serial digital device characterized by being configured to Interface signal transmission circuit. 12. A scrambled N obtained by subjecting video data to scramble processing and then performing NRZ-I conversion.
A serial digital interface signal transmission circuit for transmitting an RZ-I signal, comprising: a DC component deviation detection circuit for detecting that a DC component deviation of the scrambled NRZ-I signal exceeds a preset allowable deviation amount; An identical code continuity detection circuit for detecting that the number of consecutive identical codes of the scrambled NRZ-I signal exceeds a preset allowable number of consecutive packets; and an invalid packet-added video data by inserting an invalid packet into the video data. And an invalid packet adding circuit that generates a DC component deviation detection circuit that detects that the DC component deviation of the scrambled NRZ-I signal exceeds an allowable deviation amount, or The same code continuation detection circuit causes the same code continuation number of the scrambled NRZ-I signal to exceed the allowable number Is detected, the scrambled NRZ-I converted signal of the invalid packet-added video data obtained by performing scramble processing on the invalid packet-added video data generated by the invalid packet adding circuit and further performing NRZ-I conversion. A serial digital interface signal transmission circuit configured to transmit the signal. 13. A first transmission signal generator for generating a first serial digital signal from data to be transmitted, and a second transmission signal generator for generating a second serial digital signal from data to be transmitted. A DC component shift detection circuit for detecting a DC component shift of the first and second serial digital signals; and a serial digital signal having a smaller DC component shift based on a detection output of the DC component shift detection circuit. A serial digital interface signal transmitting circuit for transmitting a serial digital signal having a smaller DC component shift, comprising a selecting circuit for selecting a signal. 14. The serial digital signal according to claim 13, wherein the serial digital signal is a scrambled NRZ-I signal generated by performing NRZ-I conversion after performing scramble processing on the data. Interface signal transmission circuit. 15. A first transmission signal generator for generating a first serial digital signal from data to be transmitted, and a second transmission signal generator for generating a second serial digital signal from data to be transmitted. An identical code continuation detection circuit for detecting the same code continuation of the first and second serial digital signals; and selecting a serial digital signal having less same code continuation based on a detection output of the same code continuation detection circuit. A serial digital interface signal transmitting circuit for transmitting a serial digital signal having a smaller number of consecutive same codes, comprising a selecting circuit. 16. The serial digital signal according to claim 15, wherein the serial digital signal is a scrambled NRZ-I signal generated by performing NRZ-I conversion after performing scramble processing on the data. Interface signal transmission circuit. 17. A first transmission signal generator for generating a first serial digital signal from data to be transmitted, and a second transmission signal generator for generating a second serial digital signal from data to be transmitted. A DC component shift detection circuit for detecting a DC component shift of the first and second serial digital signals; and a same code continuation detection circuit for detecting the same code continuation of the first and second serial digital signals. A DC component shift based on the detection output of the same sign continuation detection circuit and the detection output of the same sign continuation detection circuit, and a selection circuit for selecting a serial digital signal having a smaller number of same sign continuations. And a serial digital interface signal transmission circuit for transmitting a serial digital signal having the same number of consecutive same codes. 18. The serial digital signal according to claim 17, wherein the serial digital signal is a scrambled NRZ-I signal generated by performing NRZ-I conversion after performing scramble processing on the data. Interface signal transmission circuit. 19. The first serial digital signal includes:
The second serial digital signal is generated by subjecting the data to a predetermined conversion, and the second serial digital signal is generated by performing a predetermined conversion to invalid packet additional data obtained by adding invalid packet data to the data. 18. The serial digital interface signal transmission circuit according to claim 17, wherein: 20. A synchronous adding circuit for adding synchronous data to video data to generate synchronous additional video data, and converting the synchronous additional video data into serial data, performing scrambling, and performing NRZ-I conversion to scramble. A first transmission signal generating unit for generating an NRZ-I signal; and an invalid packet adding circuit for inserting invalid packet data into the synchronous additional video data to generate invalid packet additional synchronous additional video data. A second transmission signal generation unit that converts the packet-added synchronization-added video data into serial data, performs scramble processing, and further performs NRZ-I conversion to generate an invalid packet-added scrambled NRZ-I signal; DC component of scrambled NRZ-I signal generated by transmission signal generator First to detect deviation
And a second DC component deviation detection circuit for detecting the DC component deviation of the invalid packet-added scrambled NRZ-I signal generated by the second transmission signal generator. And the DC component shift amount of the scrambled NRZ-I signal detected by the first DC component shift amount detection circuit and the invalid packet added scrambled signal detected by the second DC component shift amount detection circuit. A comparison circuit for comparing the DC component shift amount of the NRZ-I signal with a selection circuit for selecting and transmitting a scrambled NRZ-I signal having a smaller DC component shift amount based on the comparison result of the comparison circuit; And a serial digital interface signal transmitting circuit. 21. A synchronous addition circuit for generating synchronous additional video data by adding synchronous data to video data, and converting the synchronous additional video data into serial data, performing scrambling, and performing NRZ-I conversion to scramble. A first transmission signal generating unit for generating an NRZ-I signal; and an invalid packet adding circuit for inserting invalid packet data into the synchronous additional video data to generate invalid packet additional synchronous additional video data. A second transmission signal generation unit that converts the packet-added synchronization-added video data into serial data, performs scramble processing, and further performs NRZ-I conversion to generate an invalid packet-added scrambled NRZ-I signal; Same code of scrambled NRZ-I signal generated by transmission signal generator The first to detect the number of continuations
A second same code continuation number detection circuit that detects the same code continuation number of the invalid packet added scrambled NRZ-I signal generated by the second transmission signal generation unit; The same number of the same code continuation number of the scrambled NRZ-I data detected by the first same code continuation number detection circuit and the invalid packet added scrambled NRZ-I signal detected by the second same code continuation number detection circuit. A comparison circuit that compares the number of consecutive codes, and a selection circuit that selects and transmits a scrambled NRZ-I signal having a smaller number of consecutive identical codes based on a comparison result of the comparison circuit. Serial digital interface signal transmission circuit. 22. A synchronous addition circuit for adding synchronous data to video data to generate synchronous additional video data, converting the synchronous additional video data into serial data, performing scrambling, and performing NRZ-I conversion to scramble. A first transmission signal generating unit for generating an NRZ-I signal; and an invalid packet adding circuit for inserting invalid packet data into the synchronous additional video data to generate invalid packet additional synchronous additional video data. A second transmission signal generator for converting the packet-added synchronous additional video data into serial data, performing scrambling, and performing NRZ-I conversion to generate an invalid packet-added scrambled NRZ-I signal; The scrambled NRZ- generated by the data serial conversion circuit A first DC component shift amount detection circuit for detecting the DC component shift amount of the I signal; and a second DC component shift amount detection circuit for detecting the same code continuation number of the scrambled NRZ-I signal generated by the first transmission signal generation unit. 1
A second DC component shift amount detection circuit for detecting a DC component shift amount of the invalid packet-added scrambled NRZ-I signal generated by the second transmission signal generation unit; A second identical code continuation number detection circuit that detects the same code continuation number of the invalid packet added scrambled NRZ-I signal generated by the second transmission signal generation unit; and each of the DC component deviation amount detection circuits. And a comparison circuit for comparing the DC component deviation amount and the same code continuation number based on the detection output of each of the same code continuation number detection circuits, respectively, a DC deviation amount is small based on the comparison result of the comparison circuit, And a selecting circuit for selecting and transmitting the scrambled NRZ-I signal having the smaller number of consecutive same codes, and transmitting the serial digital interface signal. circuit. 23. Data to be transmitted is converted into a serial digital signal, and a DC component deviation of the serial digital signal is detected. If the DC component deviation is large, the data to be transmitted is changed and then converted to a serial digital signal. And transmitting the serial digital interface signal. 24. The serial digital interface signal transmission method according to claim 23, wherein the data is changed by inserting invalid packet data into the data to be transmitted. 25. Data to be transmitted is converted into a serial digital signal, and the same code continuation of the serial digital signal is detected. A method for transmitting a serial digital interface signal, comprising converting the signal into a signal and transmitting the signal. 26. The serial digital interface signal transmission method according to claim 25, wherein the data is changed by inserting invalid packet data into the data to be transmitted. 27. Data to be transmitted is converted into a serial digital signal to detect DC component deviation and the same code continuation of the serial digital signal, and suitable for transmission based on the DC component deviation and the same code continuation detection result. A method for transmitting a serial digital interface signal, comprising: judging whether or not a signal is transmitted and, if the signal is not suitable for transmission, changing data to be transmitted, converting the data to a serial digital signal, and transmitting the signal. 28. The serial digital interface signal transmission method according to claim 27, wherein the data is changed by inserting invalid packet data into the data to be transmitted. 29. The serial digital interface signal transmission method according to claim 27, wherein the serial digital signal is generated by performing NRZ-I conversion after performing scramble processing on the data. 30. The serial digital interface signal transmitting method according to claim 27, wherein the data is changed by inserting invalid packet data into the data to be transmitted. 31. Two kinds of serial digital signals are generated from data to be transmitted, and a DC component shift of the two kinds of generated serial digital signals is detected, and a serial digital signal having a smaller DC component shift is generated. A method for transmitting a serial digital interface signal, comprising transmitting the signal. 32. The serial digital interface signal transmission method according to claim 31, wherein the serial digital signal is generated by performing NRZ-I conversion after performing scramble processing on the data. 33. The two types of serial digital signals are generated by subjecting the data to a predetermined conversion, and generated by subjecting the data to invalid packet added data obtained by adding invalid packet data to the data. 32. The serial digital interface signal transmission method according to claim 31, wherein: 34. Two types of serial digital signals are generated from data to be transmitted, the same code continuation of the generated two types of serial digital signals is detected, and the serial digital signal with the same code continuity is transmitted. A method for transmitting a serial digital interface signal, comprising: 35. The serial digital interface signal transmission method according to claim 34, wherein the serial digital signal is generated by performing NRZ-I conversion after performing scramble processing on the data. 36. The two types of serial digital signals, which are generated by subjecting the data to a predetermined conversion, and generated by subjecting the data to invalid packet additional data obtained by adding invalid packet data to the predetermined conversion. 35. The serial digital interface signal transmission method according to claim 34, wherein 37. Two types of serial digital signals are generated from data to be transmitted, and the DC component shift and the same code continuation of the generated two types of serial digital signals are detected, and the DC component shift and the same code continuation are detected. A serial digital interface signal transmitting method, characterized by transmitting a serial digital signal having a smaller number. 38. The serial digital interface signal transmission method according to claim 37, wherein the serial digital signal is generated by performing scramble processing on the data and then performing NRZ-I conversion. 39. The two types of serial digital signals, which are generated by subjecting the data to a predetermined conversion, and generated by subjecting the data to invalid packet additional data obtained by adding invalid packet data to the predetermined conversion. 38. The serial digital interface signal transmission method according to claim 37, wherein: 40. A signal suitable for transmission based on conversion of video data into serial data, performing predetermined signal processing to generate a serial digital interface signal, and based on the DC component shift or the same code continuation of the generated serial digital interface signal. Is evaluated, and if the signal is inappropriate for transmission, an invalid packet is inserted into the video data to generate invalid packet-added video data, and the invalid packet-added video data is converted into serial data to perform predetermined signal processing. Transmitting a serial digital interface signal generated by performing the method. 41. Converting video data into serial data, performing predetermined signal processing to generate a first serial digital interface signal, and inserting an invalid packet into the video data to generate invalid packet-added video data. The invalid packet-added video data is converted to serial data and subjected to predetermined signal processing to generate a second serial digital interface signal, and the DC component deviation or the same code continuation of the first and second serial digital interface signals is compared. A signal suitable for transmission, and transmitting the selected serial digital interface signal.