JPH1012491A - 4-terminal multilayer capacitor - Google Patents

4-terminal multilayer capacitor

Info

Publication number
JPH1012491A
JPH1012491A JP8166994A JP16699496A JPH1012491A JP H1012491 A JPH1012491 A JP H1012491A JP 8166994 A JP8166994 A JP 8166994A JP 16699496 A JP16699496 A JP 16699496A JP H1012491 A JPH1012491 A JP H1012491A
Authority
JP
Japan
Prior art keywords
electrode
capacitor
internal
multilayer capacitor
terminal multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8166994A
Other languages
Japanese (ja)
Inventor
Norimasa Asakura
教真 朝倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP8166994A priority Critical patent/JPH1012491A/en
Priority to US08/815,279 priority patent/US5815367A/en
Priority to SG1997000772A priority patent/SG72732A1/en
Publication of JPH1012491A publication Critical patent/JPH1012491A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To obtain a 4-terminal multilayer capacitor which exhibits excellent attenuation characteristics over a wide frequency band. SOLUTION: A 4-terminal multilayer capacitor 1 is composed of a dielectric sheet 2 which has an inner inductor electrode 3 which connects an input outer electrode and an output outer electrode electrically to each other, dielectric sheet 2 which have inner capacitor electrodes 5 connected electrically to the input outer electrode and inner capacitor electrodes 6 electrically connected to the output outer electrode on their surfaces, dielectric sheets 2 which have inner grounding electrodes 4 connected to a grounding outer electrode on their surfaces, etc., and those dielectric sheets 2, etc., are piled up in layers and backed integrally.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、4端子型積層コン
デンサ、特に、電子機器等のノイズ除去のために用いら
れる4端子型積層コンデンサに関する。
The present invention relates to a four-terminal multilayer capacitor, and more particularly to a four-terminal multilayer capacitor used for removing noise in electronic equipment and the like.

【0002】[0002]

【従来の技術】電子機器等のノイズ除去のために、2端
子型積層コンデンサや4端子型積層コンデンサが用いら
れている。特に、4端子型積層コンデンサは図8に示す
ように、内部グランド電極53を表面に設けた誘電体シ
ート52と、内部コンデンサ電極54を表面に設けた誘
電体シート52と、保護層用誘電体シート52等にて構
成されている。
2. Description of the Related Art A two-terminal type multilayer capacitor and a four-terminal type multilayer capacitor have been used for removing noise from electronic equipment and the like. In particular, as shown in FIG. 8, the four-terminal multilayer capacitor includes a dielectric sheet 52 having an internal ground electrode 53 on its surface, a dielectric sheet 52 having an internal capacitor electrode 54 on its surface, and a dielectric material for a protective layer. It is composed of a sheet 52 and the like.

【0003】各誘電体シート52は積み重ねられて一体
的に焼成されることにより、図9に示すコンデンサ51
が得られる。コンデンサ51の両端部には入力外部電極
56及び出力外部電極57が形成され、手前側及び奥側
の側面部にグランド外部電極58,59が形成されてい
る。図10はコンデンサ51の電気等価回路図である。
この4端子型積層コンデンサ51の共振周波数は、一般
に2端子型積層コンデンサより高くなり、高周波域で高
減衰を得ることができる。
Each of the dielectric sheets 52 is stacked and integrally fired to form a capacitor 51 shown in FIG.
Is obtained. Input external electrodes 56 and output external electrodes 57 are formed on both ends of the capacitor 51, and ground external electrodes 58 and 59 are formed on the front and rear side surfaces. FIG. 10 is an electrical equivalent circuit diagram of the capacitor 51.
The resonance frequency of the four-terminal multilayer capacitor 51 is generally higher than that of the two-terminal multilayer capacitor, and high attenuation can be obtained in a high frequency range.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、従来の
4端子型積層コンデンサ51は、高周波域において高減
衰が得られるものの、2端子型積層コンデンサの共振周
波数付近においては2端子型積層コンデンサより減衰量
が劣っていた。そこで、本発明の目的は、高周波域での
高減衰を確保しつつ、2端子型積層コンデンサの共振周
波数域においても、優れた減衰特性を有する4端子型積
層コンデンサを提供することにある。
However, in the conventional four-terminal multilayer capacitor 51, although high attenuation is obtained in a high frequency range, the attenuation is smaller than the two-terminal multilayer capacitor near the resonance frequency of the two-terminal multilayer capacitor. Was inferior. Accordingly, an object of the present invention is to provide a four-terminal multilayer capacitor having excellent attenuation characteristics even in the resonance frequency range of a two-terminal multilayer capacitor while ensuring high attenuation in a high frequency range.

【0005】[0005]

【課題を解決するための手段】以上の目的を達成するた
め、本発明に係る4端子型積層コンデンサは、(a)入
力外部電極に電気的に接続された第1の内部コンデンサ
電極と、(b)出力外部電極に電気的に接続された第2
の内部コンデンサ電極と、(c)二つのグランド外部電
極に電気的に接続され、前記第1及び第2の内部コンデ
ンサ電極との間にそれぞれ静電容量を形成する内部グラ
ンド電極と、(d)前記入力外部電極と前記出力外部電
極間を電気的に接続した内部インダクタ電極と、を備え
たことを特徴とする。
In order to achieve the above object, a four-terminal multilayer capacitor according to the present invention comprises: (a) a first internal capacitor electrode electrically connected to an input external electrode; b) a second electrically connected output external electrode
(C) an internal ground electrode electrically connected to the two ground external electrodes and forming a capacitance between the first and second internal capacitor electrodes, respectively; An internal inductor electrode electrically connected between the input external electrode and the output external electrode is provided.

【0006】[0006]

【作用】内部インダクタ電極が有するインダクタンスに
よって、共振周波数は、従来の4端子型積層コンデンサ
の共振周波数より低い周波数になる。そして、第1及び
第2の内部コンデンサ電極と内部グランド電極との間に
形成した二つの静電容量によって、高減衰の周波数帯域
の幅が広がる。
The resonance frequency is lower than the resonance frequency of the conventional four-terminal multilayer capacitor due to the inductance of the internal inductor electrode. The width of the high-attenuation frequency band is widened by the two capacitances formed between the first and second internal capacitor electrodes and the internal ground electrode.

【0007】[0007]

【発明の実施の形態】以下、本発明に係る4端子型積層
コンデンサの実施形態について添付図面を参照して説明
する。各実施形態において同一部品及び同一部分には同
じ符号を付した。 [第1実施形態、図1〜図4]図1に示すように、4端
子型積層コンデンサ1は、内部インダクタ電極3を表面
に設けた誘電体シート2、内部グランド電極4を表面に
設けた誘電体シート2、内部コンデンサ電極5,6を表
面に設けた誘電体シート2、保護層としての誘電体シー
ト2等から構成されている。各誘電体シート2は例えば
セラミック材料からなる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a four-terminal multilayer capacitor according to the present invention will be described with reference to the accompanying drawings. In each embodiment, the same components and the same portions are denoted by the same reference numerals. [First Embodiment, FIGS. 1 to 4] As shown in FIG. 1, a four-terminal multilayer capacitor 1 has a dielectric sheet 2 provided with an internal inductor electrode 3 on its surface, and an internal ground electrode 4 provided on its surface. It is composed of a dielectric sheet 2, a dielectric sheet 2 provided with internal capacitor electrodes 5 and 6 on its surface, a dielectric sheet 2 as a protective layer, and the like. Each dielectric sheet 2 is made of, for example, a ceramic material.

【0008】内部インダクタ電極3は蛇行形状をしてお
り、両端部3a,3bがそれぞれシート2の左右の縁部
に露出している。内部グランド電極4はシート2上に広
面積に形成されており、端部4a,4bがそれぞれシー
ト2の手前側及び奥側の縁部に露出している。内部コン
デンサ電極5,6はシート2の左寄りの位置及び右寄り
の位置に形成されており、それぞれの一方の端部5a,
6aがシート2の左右の縁部に露出している。電極3〜
6は、Ag,Ag−Pd,Ni等からなり、印刷、スパ
ッタリングあるいは真空蒸着等の方法により形成され
る。
The internal inductor electrode 3 has a meandering shape, and both ends 3a and 3b are exposed at the left and right edges of the sheet 2, respectively. The internal ground electrode 4 is formed in a wide area on the sheet 2, and ends 4 a and 4 b are exposed at front and rear edges of the sheet 2, respectively. The internal capacitor electrodes 5 and 6 are formed at the leftward position and the rightward position of the sheet 2, and have one end portions 5a and 5a, respectively.
6a are exposed at the left and right edges of the sheet 2. Electrodes 3 ~
Reference numeral 6 is made of Ag, Ag-Pd, Ni, or the like, and is formed by a method such as printing, sputtering, or vacuum evaporation.

【0009】各誘電体シート2は、図1に示すように積
み重ねられた後、焼成されて積層体とされる。図2に示
すように、この積層体の左右両端部にそれぞれ入力外部
電極10及び出力外部電極11が形成され、手前側及び
奥側の側面部にグランド外部電極12,13が形成され
ている。入力外部電極10は内部インダクタ電極3の端
部3a及び内部コンデンサ電極5の端部5aに電気的に
接続され、出力外部電極11は内部インダクタ電極3の
端部3b及び内部コンデンサ電極6の端部6aに電気的
に接続され、グランド外部電極12,13はそれぞれ内
部グランド電極4の端部4a,4bに電気的に接続され
ている。
The dielectric sheets 2 are stacked as shown in FIG. 1 and then fired to form a laminate. As shown in FIG. 2, an input external electrode 10 and an output external electrode 11 are formed on both left and right ends of the laminate, and ground external electrodes 12 and 13 are formed on the front and rear side surfaces. The input external electrode 10 is electrically connected to the end 3a of the internal inductor electrode 3 and the end 5a of the internal capacitor electrode 5, and the output external electrode 11 is connected to the end 3b of the internal inductor electrode 3 and the end of the internal capacitor electrode 6. 6a, and the ground external electrodes 12, 13 are electrically connected to the ends 4a, 4b of the internal ground electrode 4, respectively.

【0010】以上の構成からなる4端子型積層コンデン
サ1は、図3に示すように、従来の一つのコンデンサを
二つのコンデンサ、すなわち、内部コンデンサ電極5と
内部グランド電極4からなるコンデンサC1並びに内部
コンデンサ電極6と内部グランド電極4からなるコンデ
ンサC2に分離し、両コンデンサC1,C2間を内部イ
ンダクタ電極3にて電気的に接続した構成となってい
る。
As shown in FIG. 3, the four-terminal multilayer capacitor 1 having the above-described structure is different from the conventional one capacitor in two capacitors, that is, the capacitor C1 including the internal capacitor electrode 5 and the internal ground electrode 4 and the internal capacitor. The capacitor is separated into a capacitor C2 including a capacitor electrode 6 and an internal ground electrode 4, and both capacitors C1 and C2 are electrically connected by an internal inductor electrode 3.

【0011】図4は、静電容量が0.15μFの4端子
型積層コンデンサ1の減衰特性を測定した結果をグラフ
にしたものである(実線21参照)。図4には比較のた
め、同じ静電容量の従来の2端子型積層コンデンサの減
衰特性(点線22参照)及び従来の4端子型積層コンデ
ンサの減衰特性(点線23参照)を併せて記載してい
る。内部インダクタ電極3が有するインダクタンスによ
って、第1実施形態のコンデンサ1の共振周波数は、従
来の4端子型積層コンデンサの共振周波数より低い周波
数になっている。そして、コンデンサC1,C2によっ
て、高減衰の周波数帯域幅が広がっている。
FIG. 4 is a graph showing the results of measuring the attenuation characteristics of the four-terminal multilayer capacitor 1 having a capacitance of 0.15 μF (see the solid line 21). FIG. 4 also shows, for comparison, the attenuation characteristics of a conventional two-terminal multilayer capacitor having the same capacitance (see dotted line 22) and the attenuation characteristics of a conventional four-terminal multilayer capacitor (see dotted line 23). I have. Due to the inductance of the internal inductor electrode 3, the resonance frequency of the capacitor 1 of the first embodiment is lower than the resonance frequency of the conventional four-terminal multilayer capacitor. The capacitors C1 and C2 widen the frequency band of high attenuation.

【0012】[第2実施形態、図5〜図7]図5に示す
ように、第2実施形態の4端子型積層コンデンサ31は
内部インダクタ電極32及び内部コンデンサ電極33,
34を残して前記第1実施形態のコンデンサ1と同様の
ものである。内部インダクタ電極32は蛇行部32a,
32b,32cから成り、その両端部32d,32eが
それぞれシート2の左右の縁部に露出している。内部コ
ンデンサ電極33は蛇行部32aと32bに電気的に接
続され、内部コンデンサ電極34は蛇行部32bと32
cに電気的に接続されている。
[Second Embodiment, FIGS. 5 to 7] As shown in FIG. 5, a four-terminal multilayer capacitor 31 of a second embodiment has an internal inductor electrode 32 and an internal capacitor electrode 33,
Except for 34, it is the same as the capacitor 1 of the first embodiment. The internal inductor electrode 32 has a meandering portion 32a,
The two ends 32d and 32e are exposed to the left and right edges of the sheet 2, respectively. The internal capacitor electrode 33 is electrically connected to the meandering portions 32a and 32b, and the internal capacitor electrode 34 is connected to the meandering portions 32b and 32b.
c is electrically connected.

【0013】各誘電体シート2は、図5に示すように積
み重ねられた後、焼成されて積層体とされる。図6に示
すように、この積層体の左右両端部にそれぞれ入力外部
電極36及び出力外部電極37が形成され、手前側及び
奥側の側面部にグランド外部電極38,39が形成され
ている。入力外部電極36は内部インダクタ電極32の
端部32d及び内部コンデンサ電極5の端部5aに電気
的に接続され、出力外部電極37は内部インダクタ電極
32の端部32e及び内部コンデンサ電極6の端部6a
に電気的に接続され、グランド外部電極38,39はそ
れぞれ内部グランド電極4の端部4a,4bに電気的に
接続されている。
Each dielectric sheet 2 is stacked as shown in FIG. 5 and then fired to form a laminate. As shown in FIG. 6, an input external electrode 36 and an output external electrode 37 are formed on both left and right ends of the laminate, and ground external electrodes 38 and 39 are formed on the side surfaces on the near side and the far side. The input external electrode 36 is electrically connected to the end 32d of the internal inductor electrode 32 and the end 5a of the internal capacitor electrode 5, and the output external electrode 37 is connected to the end 32e of the internal inductor electrode 32 and the end of the internal capacitor electrode 6. 6a
The ground external electrodes 38 and 39 are electrically connected to the ends 4a and 4b of the internal ground electrode 4, respectively.

【0014】以上の構成からなる4端子型積層コンデン
サ31は、図7に示すように、従来の一つのコンデンサ
を二つのコンデンサ、すなわち、内部コンデンサ電極5
と内部グランド電極4から成るコンデンサC1並びに内
部コンデンサ電極6と内部グランド電極4から成るコン
デンサC2に分離し、両コンデンサC1,C2間を内部
インダクタ電極32から成るインダクタンスと内部コン
デンサ電極33,34,4から成るコンデンサC3,C
4にて構成されたLC回路にて電気的に接続した構成と
なっている。この4端子型積層コンデンサ31は、前記
第1実施形態のコンデンサ1より、更に低周波側に共振
周波数がシフトする効果が得られる。
As shown in FIG. 7, the four-terminal type multilayer capacitor 31 having the above-described structure is different from the conventional one capacitor in two capacitors, that is, the internal capacitor electrode 5.
And a capacitor C1 composed of the internal ground electrode 4 and a capacitor C2 composed of the internal capacitor electrode 6 and the internal ground electrode 4. Between the capacitors C1 and C2, an inductance composed of the internal inductor electrode 32 and internal capacitor electrodes 33, 34, 4 are provided. Capacitors C3 and C
4 are electrically connected by the LC circuit configured. The four-terminal multilayer capacitor 31 has the effect of shifting the resonance frequency to a lower frequency side than the capacitor 1 of the first embodiment.

【0015】[他の実施形態]なお、本発明に係る4端
子型積層コンデンサは前記実施形態に限定するものでは
なく、その要旨の範囲内で種々に変更することができ
る。前記実施形態において、内部インダクタ電極と内部
グランド電極間に発生する浮遊容量を抑えるために、ス
ペーサ用誘電体シートを、内部インダクタ電極を設けた
誘電体シートと内部グランド電極を設けた誘電体シート
の間に挿入してもよい。また、内部インダクタ電極と内
部グランド電極を、積層方向の任意の位置に一対以上構
成した構造とし、電極配置の対称性をもたせたり、イン
ダクタンス成分を調整した構造としてもよい。
[Other Embodiments] The four-terminal multilayer capacitor according to the present invention is not limited to the above embodiment, but can be variously modified within the scope of the gist. In the embodiment, in order to suppress the stray capacitance generated between the internal inductor electrode and the internal ground electrode, the spacer dielectric sheet is formed of a dielectric sheet provided with the internal inductor electrode and a dielectric sheet provided with the internal ground electrode. It may be inserted between them. Further, a structure in which a pair of the internal inductor electrode and the internal ground electrode are arranged at an arbitrary position in the laminating direction may be employed to provide a symmetrical arrangement of the electrodes or to adjust the inductance component.

【0016】さらに、前記実施形態は個産品の場合を例
にして説明したが、量産時の場合には複数個のコンデン
サを備えたマザー基板にて製作し、所望のサイズに切り
出して製品とすることができる。また、前記実施形態
は、シートを積み重ねた後、一体的に焼結するものであ
るが、必ずしもこれに限定されない。シートは予め焼結
されたものを用いてもよい。また、印刷等の方法により
ペースト状の誘電体材料や導電体材料を順に塗布、乾燥
して重ね塗りすることによって、積層構造を有するコン
デンサを得てもよい。
Further, the above embodiment has been described by taking the case of individual products as an example. However, in the case of mass production, it is manufactured on a mother board provided with a plurality of capacitors, and cut into a desired size to obtain a product. be able to. In the above embodiment, the sheets are stacked and then integrally sintered, but the present invention is not necessarily limited to this. The sheet may be a sheet sintered in advance. Alternatively, a capacitor having a laminated structure may be obtained by sequentially applying a paste-like dielectric material or a conductive material by a method such as printing, drying, and applying again.

【0017】[0017]

【発明の効果】以上の説明で明らかなように、本発明に
よれば、内部インダクタ電極と第1及び第2の内部コン
デンサ電極と内部グランド電極を設けたので、二つの静
電容量と内部インダクタ電極が有するインダクタンスに
よって、従来の4端子型積層コンデンサに比べ、高周波
数域での減衰を同等に維持しながら、かつ、共振周波数
は、より低い周波数にすることができる。この結果、広
い周波数帯域で優れた減衰特性を有する4端子型積層コ
ンデンサを得ることができる。
As is apparent from the above description, according to the present invention, since the internal inductor electrode, the first and second internal capacitor electrodes and the internal ground electrode are provided, two capacitances and an internal inductor are provided. Due to the inductance of the electrodes, the resonance frequency can be lower than that of the conventional four-terminal multilayer capacitor while maintaining the same attenuation in the high frequency range. As a result, a four-terminal multilayer capacitor having excellent attenuation characteristics in a wide frequency band can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る4端子型積層コンデンサの第1実
施形態を示す分解斜視図。
FIG. 1 is an exploded perspective view showing a first embodiment of a four-terminal multilayer capacitor according to the present invention.

【図2】図1に示した4端子型積層コンデンサの外観を
示す斜視図。
FIG. 2 is a perspective view showing an appearance of the four-terminal multilayer capacitor shown in FIG.

【図3】図2に示した4端子型積層コンデンサの電気等
価回路図。
3 is an electrical equivalent circuit diagram of the four-terminal multilayer capacitor shown in FIG.

【図4】図2に示した4端子型積層コンデンサの減衰特
性を示すグラフ。
FIG. 4 is a graph showing attenuation characteristics of the four-terminal multilayer capacitor shown in FIG. 2;

【図5】本発明に係る4端子型積層コンデンサの第2実
施例を示す分解斜視図。
FIG. 5 is an exploded perspective view showing a second embodiment of the four-terminal multilayer capacitor according to the present invention.

【図6】図5に示した4端子型積層コンデンサの外観を
示す斜視図。
FIG. 6 is an exemplary perspective view showing the appearance of the four-terminal multilayer capacitor shown in FIG. 5;

【図7】図6に示した4端子型積層コンデンサの電気等
価回路図。
FIG. 7 is an electric equivalent circuit diagram of the four-terminal multilayer capacitor shown in FIG. 6;

【図8】従来の4端子型積層コンデンサの分解斜視図。FIG. 8 is an exploded perspective view of a conventional four-terminal multilayer capacitor.

【図9】図8に示した4端子型積層コンデンサの外観を
示す斜視図。
FIG. 9 is a perspective view showing an appearance of the four-terminal multilayer capacitor shown in FIG. 8;

【図10】図9に示した4端子型積層コンデンサの電気
等価回路図。
10 is an electric equivalent circuit diagram of the four-terminal multilayer capacitor shown in FIG.

【符号の説明】[Explanation of symbols]

1,31…4端子型積層コンデンサ 3,33…内部インダクタ電極 4…内部グランド電極 5,6…内部コンデンサ電極 10,36…入力外部電極 11,37…出力外部電極 12,13,38,39…グランド外部電極 1, 31 4-terminal multilayer capacitor 3, 33 Internal inductor electrode 4, Internal ground electrode 5, 6 Internal capacitor electrode 10, 36 Input external electrode 11, 37 Output external electrode 12, 13, 38, 39 Ground external electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 入力外部電極と出力外部電極と二つのグ
ランド外部電極を有した4端子型積層コンデンサにおい
て、 前記入力外部電極に電気的に接続された第1の内部コン
デンサ電極と、 前記出力外部電極に電気的に接続された第2の内部コン
デンサ電極と、 前記二つのグランド外部電極に電気的に接続され、前記
第1及び第2の内部コンデンサ電極との間にそれぞれ静
電容量を形成する内部グランド電極と、 前記入力外部電極と前記出力外部電極間を電気的に接続
した内部インダクタ電極と、 を備えたことを特徴とする4端子型積層コンデンサ。
1. A four-terminal multilayer capacitor having an input external electrode, an output external electrode and two ground external electrodes, wherein: a first internal capacitor electrode electrically connected to the input external electrode; A second internal capacitor electrode electrically connected to the electrode; and a second internal capacitor electrode electrically connected to the two ground external electrodes to form capacitance between the first and second internal capacitor electrodes, respectively. A four-terminal multilayer capacitor comprising: an internal ground electrode; and an internal inductor electrode that electrically connects the input external electrode and the output external electrode.
JP8166994A 1996-03-11 1996-06-27 4-terminal multilayer capacitor Pending JPH1012491A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP8166994A JPH1012491A (en) 1996-06-27 1996-06-27 4-terminal multilayer capacitor
US08/815,279 US5815367A (en) 1996-03-11 1997-03-10 Layered capacitors having an internal inductor element
SG1997000772A SG72732A1 (en) 1996-03-11 1997-03-11 Layered capacitors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8166994A JPH1012491A (en) 1996-06-27 1996-06-27 4-terminal multilayer capacitor

Publications (1)

Publication Number Publication Date
JPH1012491A true JPH1012491A (en) 1998-01-16

Family

ID=15841420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8166994A Pending JPH1012491A (en) 1996-03-11 1996-06-27 4-terminal multilayer capacitor

Country Status (1)

Country Link
JP (1) JPH1012491A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003008153A (en) * 2001-06-19 2003-01-10 Taiyo Yuden Co Ltd Electronic circuit device and low-pass filter
JP2007124172A (en) * 2005-10-27 2007-05-17 Ube Ind Ltd High-frequency low pass filter
JP2007221472A (en) * 2006-02-16 2007-08-30 Tdk Corp Noise filter, and noise filter mounting structure
KR100761624B1 (en) 2005-06-13 2007-09-27 티디케이가부시기가이샤 Laminated capacitor
US8650526B2 (en) 2012-03-07 2014-02-11 Murata Manufacturing Co., Ltd. Method and program for creating equivalent circuit for three-terminal capacitor
KR101382154B1 (en) * 2006-12-07 2014-04-07 티디케이가부시기가이샤 Multilayer electronic component
KR20150052507A (en) * 2013-11-06 2015-05-14 삼성전기주식회사 Multi-layered ceramic capacitor and mounting circuit thereof
KR20150127984A (en) * 2014-05-08 2015-11-18 삼성전기주식회사 Multi-layered chip component and board for mounting the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003008153A (en) * 2001-06-19 2003-01-10 Taiyo Yuden Co Ltd Electronic circuit device and low-pass filter
KR100761624B1 (en) 2005-06-13 2007-09-27 티디케이가부시기가이샤 Laminated capacitor
JP2007124172A (en) * 2005-10-27 2007-05-17 Ube Ind Ltd High-frequency low pass filter
JP2007221472A (en) * 2006-02-16 2007-08-30 Tdk Corp Noise filter, and noise filter mounting structure
KR101382154B1 (en) * 2006-12-07 2014-04-07 티디케이가부시기가이샤 Multilayer electronic component
US8650526B2 (en) 2012-03-07 2014-02-11 Murata Manufacturing Co., Ltd. Method and program for creating equivalent circuit for three-terminal capacitor
KR20150052507A (en) * 2013-11-06 2015-05-14 삼성전기주식회사 Multi-layered ceramic capacitor and mounting circuit thereof
KR20150127984A (en) * 2014-05-08 2015-11-18 삼성전기주식회사 Multi-layered chip component and board for mounting the same

Similar Documents

Publication Publication Date Title
US7466535B2 (en) Multilayer capacitor
JP3106942B2 (en) LC resonance components
US7508647B2 (en) Multilayer capacitor
JP3470566B2 (en) Multilayer electronic components
US5815367A (en) Layered capacitors having an internal inductor element
JPH01295407A (en) Inductor, composite component including inductor and manufacture thereof
JPH1012490A (en) Through-type layer-built capacitor array
JP2002237429A (en) Laminated lead-through capacitor and array thereof
JPH1012491A (en) 4-terminal multilayer capacitor
JP3067612B2 (en) Stacked bandpass filter
JPH0955335A (en) Laminated type through capacitor
JP3204085B2 (en) Stacked noise filter
JPH0653048A (en) Chip type lc filter
JP3075003B2 (en) Stacked noise filter
JP3134841B2 (en) Multilayer noise filter for differential transmission line
JP2000151324A (en) Laminated type noise filter
JP2607853Y2 (en) LC composite parts array
JP2982558B2 (en) Multilayer feedthrough capacitors
JP3134640B2 (en) Multilayer electronic components with built-in capacitance
JPH036094A (en) Inductor and composite component containing conductor and manufacture thereof
JP3449090B2 (en) Electronic components with built-in inductor
JPH07254528A (en) Laminated noise filter
JPH0729737A (en) Chip inductor
JP3419187B2 (en) Multilayer type LC resonance component
JP3139270B2 (en) LC composite parts

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 8

Free format text: PAYMENT UNTIL: 20080714

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 9

Free format text: PAYMENT UNTIL: 20090714

LAPS Cancellation because of no payment of annual fees