JPH10124316A - Multithread processor independently processing plural instruction flows and flexibly controlling processing performance by the same instruction flows - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multithread processor which dynamically realizes the processing performance needed by instruction flows and to improves the total throughput. SOLUTION: This processor is equipped with instruction decoding parts 1 to 3 which decode instructions, specify function units to execute the instructions, and output instruction issue requests, a priority control part 60 which controls the priority levels of instruction flows that can be set by the instruction flows with instructions in the instruction flows, and an instruction issue arbitration part 40 which determines instructions to be issued to the function units according to the priority when more than one instruction decoding part output instruction issue requests to one function unit. Consequently, the processing performance needed by the instruction flows can dynamically and properly be actualized and the total throughput can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for efficiently using a plurality of operation units by issuing instructions from a plurality of instruction streams in parallel.

[0002]

2. Description of the Related Art As a conventional example, there is a multi-thread processor for simultaneously processing a plurality of instruction streams in one processor. For information on the multithreaded processor method, see "A Multithreaded Processor Architecture with
Simultaneous Instruction Issuing, "In Proc. Of IS
S'91: International Symposium on Supercomputing, Fu
kuoka, Japan, pp.87-96, November 1991.

FIG. 15 is a block diagram showing the configuration of this conventional multithread processor. In the figure, a multi-thread processor includes an instruction cache 50
0, 3 instruction fetch units 501, 3 decoding units 502, 12 standby stations 50
Comprising three or four instruction scheduling units 504, four functional units 505, and a register set 506;
It is configured to simultaneously and independently execute three instruction streams corresponding to the combination of the instruction fetch unit and the instruction decoding unit in FIG. Here, the instruction flow corresponds to a processing flow by a combination of an instruction fetch unit and an instruction decoding unit.

In FIG. 1, an instruction fetch unit 50 is provided.
1 is an instruction cache 5 which stores instructions of different instruction flows.
Read from 00. The decoding unit 501 decodes the instructions of the respective instruction streams, and the standby station 5 connected to the functional unit 505 capable of processing the instructions.
03 stores an instruction decoding result (hereinafter simply referred to as an instruction).

[0005] The instruction scheduling unit 504 includes:
An appropriate command is selected from the standby station 503 and sent to the free functional unit 505. When the instruction decoding results of different instruction streams for one functional unit are stored in the standby station 503, the instructions are selected in a fixed order. This ensures fairness between the command streams.

The functional units 505 are arithmetic units for executing instructions, respectively, and execute instructions from the standby station 503 using the register set 506. Each functional unit may be the same, but is often provided for each type of operation such as a load / store unit, an integer operation unit, a floating point operation unit, a multiplication / division unit, and the like.

[0007] The multi-thread structured as described above
The operation of the processor will be briefly described. In the multi-thread processor shown in the figure, three instruction fetch units 501 and three decoding units 502 are provided, so that three instruction streams can be fetched and decoded in parallel. Regarding the correspondence between the three instruction streams and the programs in the instruction cache 500 (or the main memory (not shown)), one program corresponds to one instruction stream (three instruction streams are generated from three programs). Or one program corresponds to a plurality of instruction streams (three instruction streams are generated from one program). The latter is, for example, a case where one image processing program is simultaneously executed as a plurality of instruction streams for different image data.

[0008] The instructions decoded by the decoding unit 502 are:
The instruction is issued to the functional unit corresponding to the instruction via the standby station 503 and the instruction scheduling unit 504. Each functional unit executes the issued instruction regardless of the instruction stream. As described above, a characteristic of the multi-thread processor is that a plurality of instruction streams are simultaneously executed by sharing a computing unit.

Although a multi-thread processor handles a plurality of instruction streams inside one processor, a unit for executing one instruction stream is called a logical processor.
Each of the logical processors has a decoding unit, an instruction sequence control mechanism, a register set, and the like so as to handle an instruction stream independently. Functional units and cache memories used by a plurality of logical processors are shared between the logical processors.

On the other hand, the whole processor will be called a physical processor with respect to a logical processor. When comparing a multithreaded processor with an existing superscalar processor, the superscalar processor is multiplexed (pluralized) with only functional units, so that only one instruction stream can be processed simultaneously. Therefore, pipeline interlock frequently occurs due to dependencies between instructions, and as a result, the use efficiency of the functional unit does not increase and it is difficult to improve the performance. On the other hand, the above-described multi-thread processor can increase the efficiency of use of each functional unit and improve performance by executing a plurality of instruction stream instructions in parallel.

[0011]

However, the configuration of the multi-thread processor has the following problems. First, because multiple logical processors share a functional unit, instructions issued from multiple instruction streams may compete in the functional unit, and thus, during a certain period of time, a particular logical processor In some cases, the number of instructions issued by another logical processor may be extremely small as compared with the number of instructions issued by other logical processors, and the performance of the specific logical processor is extremely reduced. Also, when the load between logical processors is significantly different, even if instruction flows having the same processing content (generated from the same program) are assigned to each logical processor, processing is delayed by a specific instruction flow. And the end time of the process varies, and the speed may not increase as a whole.

Secondly, even if different instruction streams are assigned to the logical processors, and there is a case where it is desired to execute a specific instruction stream faster, even if the processing speed of the specific logical processor is relatively increased, an instruction cache or the like can be used. Since the shared resources cannot be occupied, the overall performance is reduced. For example, this is the case where an urgent interrupt process or the like occurs.

In view of the above problems, an object of the present invention is to provide a multi-thread processor capable of flexibly adjusting the processing performance of each instruction flow among a plurality of instruction flows and improving the overall processing efficiency. The purpose is to do.

[0014]

A multi-thread processor that achieves the above object is provided in correspondence with a plurality of functional units each executing an instruction and an instruction stream, decodes each instruction, and executes the instruction. A plurality of instruction decoding means for designating a functional unit to be issued and generating an instruction issuance request for requesting that the decoded instruction be issued to the functional unit, and holding the priority of the instruction flow for each instruction flow Holding means, and control means for determining a decoded instruction to be issued to the functional unit according to the priority held by the holding means when two or more instruction issuance requests simultaneously designate one functional unit And is provided.

According to this configuration, the instruction to be issued to each functional unit (the result of decoding the instruction) is determined according to the priority, so that the load variation among a plurality of instruction streams can be flexibly determined according to the priority. Adjustments can be made, and the processing performance required for each instruction stream can be appropriately realized, and the overall processing efficiency can be improved. Here, the holding unit further holds a flag group that can be set by the instruction and indicates whether the instruction flow should be stopped or executed for each instruction flow, and the control unit includes: an arbitration unit that makes the determination; If a flag indicating the instruction flow is set, a stop means for stopping the instruction flow by making the above-described determination excluding the instruction issue request of the instruction flow corresponding to the flag may be provided.

According to this configuration, when the instruction stream is in an idle state or a waiting state in its execution process, the instruction stream can be stopped. That is, as a result, other instruction streams can be executed with priority, and the overall processing performance can be further improved.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

<Structure of Multithread Processor> FIG. 1 is a block diagram showing the structure of a main part of a multithread processor according to an embodiment of the present invention. This multi-thread
The processor includes instruction decoding units 1 to 3 and a functional unit A2.
0, functional unit B21, functional unit C22, functional unit D23, instruction issue determination unit 30, instruction issue arbitration unit 4
0, an instruction issuance prohibition unit 50, a priority control unit 60, and an instruction selection unit 70, and arbitrates instruction issuance to each functional unit according to the execution state of the logical processor, the priority of the instruction flow, and external factors. Is configured.

Further, the present multi-thread processor includes:
Although the instruction cache, instruction fetch unit, register file, and the like shown in FIG. 15 are naturally provided, they are omitted from FIG. 1 because they are the same as the conventional example. Similarly, the detailed configuration of the functional unit such as the number of pipeline stages is not related to the present invention, and the description is omitted. In this embodiment, for the sake of simplicity, it is assumed that each instruction decoding unit decodes one instruction per instruction stream, and that only one instruction can be issued at a time.

In FIG. 1, instruction decoding units 1 to 3 decode instructions in the instruction stream, respectively. As a result of the decoding, an instruction issuance request is sent to the instruction issuance determination unit 30 and instruction contents (operations and the like) are sent to the instruction selection unit 70. Is output. Here, the instruction issuance request includes a flag for requesting instruction issuance (hereinafter, referred to as a request flag) and information indicating a type of a functional unit in which the instruction is to be executed (hereinafter, referred to as a functional unit number).
The instruction decoding units 1 to 3 independently decode the instruction stream, and thus correspond to the above logical processors. In the present embodiment, three instruction decoding units are provided in order to incorporate three logical processors in one physical processor. Or later,
The logical processors corresponding to the instruction decoding units 1 to 3 are called logical processors 1 to 3 to distinguish them. Similarly, instruction streams corresponding to the logical processors 1 to 3 are referred to as instruction streams 1 to 3, respectively.

Functional units A20, B21, C22, D
23 (hereinafter referred to as functional units A, B, C, and D)
In response to an instruction (decoding result) issued from the instruction decoding units 1 to 3 via the instruction selection unit 70, the instruction execution, that is, data access processing and arithmetic processing are performed. The functions of each functional unit may be all the same, but the processing contents will be exemplified for easy understanding.

That is, the functional unit A is a load store unit for processing a memory access instruction, the functional unit B is an integer operation unit for processing an integer operation, and the functional unit C is for performing addition and subtraction of floating point and conversion between integer and floating point. The floating-point unit and the functional unit D are floating-point units that perform multiplication and division of floating-point. Further, in the present embodiment, the functional unit B has a function of processing an instruction relating to the setting of the priority as one processing content of the integer operation. These functional units are components of the logical processors 1 to 3, but one-to-one with the logical processors.
, But is shared by the logical processors 1 to 3. Each functional unit is in a state in which an instruction can be received (hereinafter simply referred to as read) depending on whether or not the instruction is being processed.
y or not accepted (hereinafter simply n
ot ready) to the instruction issuance determination unit 30.

The instruction issuance judging section 30 includes instruction decoding sections 1 to 3
From the instruction issuance request (the above-mentioned request flag and functional unit number), determine the functional unit to which the instruction is to be issued, further notify from each functional unit whether or not it is ready, and control the priority. Upon receiving a notification from the unit 60 indicating whether each logical processor is in a stopped state or in an executing state, it is determined whether or not an instruction can be issued for each of the functional units A to D.

The instruction issuance arbitration unit 40 is provided for each logical processor specified by the priority control unit 60 when there are a plurality of instruction issuance requests determined to be can be issued to one functional unit and there is a conflict. A plurality of instruction issuance requests are arbitrated according to the priority, and one instruction to be issued is determined.
The instruction issuance prohibition unit 50 finally determines whether or not to issue the instruction based on the arbitration result of the instruction issuance arbitration unit 40, and instructs the instruction selection unit 70 on the instruction to be issued as a result of the determination. . Specifically, when an urgent process is requested for each logical processor, the issuance of an instruction in the instruction stream of the logical processor is temporarily prohibited. Instruct 70. The instruction issuance prohibition unit 50 temporarily prohibits instruction issuance because the above-mentioned urgent processing occurs after the processing by the instruction issuance determination unit 30 and the instruction issuance arbitration unit 40, and the highest priority is given to this. To do that. The instruction issuance prohibition unit 50 can prohibit the issuance of the instruction after the instruction issuance arbitration unit 40 determines the instruction to be issued. Can be effectively prohibited. For example, even when the urgent process occurs late in the machine cycle period, it can be effectively prohibited.

The priority control unit 60 manages the priority of each logical processor, and manages information indicating whether the logical processor is in the execution state or the halt state. The priority is notified, and the instruction issuance determination unit 30 is notified as to whether or not the execution state is set. further,
The priority control unit 60 has a function of giving priority to the logical processor for a predetermined number of continuous cycles when a specific instruction is executed (hereinafter, referred to as a continuous cycle priority function).
In order to manage the priority and the information indicating whether or not the state is the execution state, the priority control unit 60 includes three control registers, that is, a priority specification register, an internal interrupt register, and an exclusive stop register. The values of these registers are set according to the instructions in the instruction stream.

The instruction selecting unit 70 receives instructions (operations and the like) decoded by the instruction decoding units 1 to 3 in accordance with the instruction issuing unit designating the issuing unit's instruction decoding unit and the issuing destination functional unit from the instruction issuance inhibiting unit 50. To functional units A to
Issue to D. <Priority control unit 60: priority specification register> FIG.
4 is an explanatory diagram showing a bit configuration of a priority specification register (hereinafter referred to as a PRI register) incorporated in the priority control unit 60.

As shown in the figure, the PRI register stores MYID, PRI
3, each field of PRI2, PRI1, and MYPRI, and holds information indicating the priority of each logical processor and whether or not the logical processor is in a stopped state. The MYID field is set when a read instruction of this PRI register is executed in the logical processor.
This is a field indicating the ID of the logical processor that has executed the read instruction. For example, when the read instruction is executed in the logical processor 3, an ID (for example, 100) indicating the logical processor 3 is read.

The PRI3 field is a field indicating the priority of the logical processor 3 and whether or not the logical processor 3 is in a stopped state. PR
I2 and PRI1 fields are logical processors 2 and 1 respectively.
Is similar to PRI3. The MYPRI field is a field indicating the priority of the logical processor executing the read instruction when the read instruction of the PRI register is executed in the logical processor. For example, when the read instruction is executed in the logical processor 1, the contents of the PRI1 field are copied to the MYPRI field and read.

FIG. 4 is an explanatory diagram showing the lower two bits of each of the PRI3 to PRI1 fields in the PRI register. In the figure, PRI3 to PRI1 are abbreviated as PRIx, and the bit positions in the field are added in []. Where x
Indicates a logical processor number (or thread number).
PRIx [1: 0] is low (lowest), middle (middle),
Represents three levels of highest priority. The reason why the two bits indicate the three levels of priority is that it is possible to individually set PRIx [1] for the supervisor mode and PRIx [0] for the user mode. The setting of the priority is performed by the functional unit B according to the following dedicated instruction (mnemonic notation). "Inc pri"; This instruction raises the priority, that is, sets PRIx [1] to 1 in the supervisor mode and sets PRIx [0] to 1 in the user mode. "Dec pri"; This instruction lowers the priority, that is, sets PRIx [1] to 0 in the supervisor mode and sets PRIx [0] to 0 in the user mode.

These instructions, unlike ordinary data transfer instructions between registers, do not require operands and are composed of only operation codes. Therefore, the same instruction can be used in any instruction stream. For example,
This is useful when a plurality of instruction streams are generated from one program, and different data are shared between the instruction streams so as to be processed in parallel.

Further, since the priority of the instruction stream to which the instruction belongs is changed by the one functional unit, it is possible to prevent the priority of a different instruction stream from being rewritten by mistake and to prevent malfunction. For example, when the same image processing is performed on image data for each color of an RGB color image,
When one image processing program is executed independently and simultaneously as three instruction streams, information can be hidden (the program need not distinguish any one of RGB) and the independence of the instruction stream is guaranteed. As a result, the reliability of the OS and the entire system is improved.

According to these instructions and the bit assignments shown in the figure, even if, for example, the mode is changed from the user mode to the supervisor mode and the priority is changed, the previous priority is preserved when returning to the user mode. Will be. For example, even if an interrupt occurs in user mode and the system temporarily transitions to supervisor mode, PRIx [1] is restored before interrupt processing returns to user mode, so that the priority in user mode can be changed. Will be saved.

FIG. 5 is an explanatory diagram showing the bit allocation of the upper one bit of each of the PRI3 to PRI1 fields in the field PRI register indicating the priority order. As shown in the figure, PRIx
[2] indicates whether the logical processor is in an execution state or a stopped state. The setting from the execution state to the stop state is performed by the functional unit B according to the following dedicated instruction (mnemonic notation). "Halt"; This instruction puts the issuing logical processor in a halt state. That is, PRIx [2] of the logical processor is set to 1. When a stop state by this instruction is distinguished from a stop state by another instruction, it is called a self-stop state.

Release of self-stop state (return to execution state)
Is not due to instructions but to interrupt inputs to the logical processor. That is, in the multi-thread processor, the interrupt processing is generated for each logical processor, and is released when an interrupt (external interrupt, internal interrupt, etc.) occurs for the logical processor in the self-stop state. <Priority control unit 60: internal interrupt register> FIG.
FIG. 3 is an explanatory diagram showing a bit configuration of an internal interrupt register (hereinafter, referred to as an IR register) built in the priority control unit 60. The internal interrupt referred to here is an interrupt between logical processors, that is, an interrupt from one logical processor to another logical processor. The logical processor to which the internal interrupt has been applied is released from the self-stop state when in the self-stop state, and is used, for example, when processing is performed synchronously between the logical processors or when synchronous communication is performed.

As shown in the figure, the IR register has a MYID field and IR3 to IR1 bits and is a register for requesting an internal interrupt to another logical processor.
The MYID field is the same as that of FIG. The IR3 bit is a bit by which another logical processor requests the logical processor 3 for an internal interrupt. When this bit is turned ON, PR3 [2] is set to 0 and IR3 is returned to OFF under the control of the instruction decoding unit 3 which has received the interrupt request. Here, the self-stop state of the logical processor 3 is released by setting PR3 [2] to 0.

The IR2 and IR1 bits are also interrupt request bits for the logical processors 2 and 1, respectively, and are the same as the IR3 bit. The setting of the IR3 to IR1 bits is performed according to a normal register transfer instruction. In a normal register transfer instruction, it is necessary to write directly to the bit positions of IR3 to IR1, so each instruction stream needs to distinguish its own logical processor ID from the logical processor ID of the interrupt destination. , The operation of the logical processor ID is enabled in each instruction stream. <Priority Control Unit 60: Exclusion Stop Register> FIG.
FIG. 4 is an explanatory diagram showing a bit configuration of an EXCL register (abbreviated). Here, exclusive stopping means stopping a logical processor other than a certain processor. However, 2
No more than one logical processor can be in the exclusive halt state at the same time.

As shown in the figure, the EXCL register has a MYID field and each bit of EXCL3 to EXCL1, and requests that only one logical processor be put into an execution state and other logical processors be put into a stopped state. Register. The MYID field is the same as in FIGS. 3 and 6, and a description thereof will be omitted. The EXCL3 bit indicates that the logical processor 3 is performing an exclusive stop when this bit is ON. In this case, only the logical processor 3 can execute,
The logical processor 2 and the logical processor 1 are stopped.

The same applies to each bit of EXCL2 and EXCL1.
These bits EXCL3 to EXCL1 are set and released by the functional unit B in accordance with the following dedicated instruction (mnemonic notation). "Excsv": This instruction is an instruction to set exclusive suspension for the issuing logical processor, that is, to suspend all logical processors other than the issuing logical processor. For example, logical processor 1
Executes this instruction, EXCL1 turns ON, EXCL2 and EXCL2
EXCL3 is set to OFF. Even if a plurality of logical processors issue this instruction at the same time, all logical processors do not stop operating. This is because this instruction is executed only by the functional unit B, and is limited to one at the time of execution. "Retex": This instruction is an instruction to release the exclusive suspension of the issuing logical processor, that is, to return all other logical processors to the original state. For example, when the logical processor 1 executes this instruction, EXCL1 is set to OFF.

Like these incpr instructions and decpr instructions, these instructions can use the same instruction in any instruction stream that does not require an operand. PRI register above, IR
The three control registers, the register and the EXCL register, each have one physical entity.
Since the ID field and the MYPRI field of the PRI register indicate the value of the own logical processor, it is seen from each logical processor that a different register exists for each logical processor. Also, since the addressing of these control registers is the same from all logical processors, even if the same instruction is executed, the IDs of the respective logical processors themselves are respectively determined.
And priorities. <Instruction Issue Determination Unit 30> FIG. 8 is a block diagram showing a more detailed configuration example of the instruction issue determination unit 30 of FIG. The instruction issuance determination unit 30 includes a stop determination unit 310, a distribution unit 32
0, an issue determination unit 330 is provided.

The stop judging section 310 includes three sets of NOR circuits and AND circuits corresponding to the instruction decoding sections 1 to 3, respectively. Each set of the NOR circuit and the AND circuit receives the above-mentioned instruction issue request (request flag and functional unit number) from the instruction decoding unit, and the self-stop state (PRIx [2] of the PRI register is ON for each logical processor) ) Or when stopped due to exclusive stop (EXCLx bit is ON),
The signal of the request flag (hereinafter, referred to as a request presence / absence signal) is forcibly turned off, and if it is in the execution state and has not been stopped by the exclusive stop, the request presence / absence signal is output as it is.

The distribution unit 320 has three demultiplexers corresponding to the instruction decoding units 1 to 3, respectively. Each demultiplexer distributes the request presence / absence signal input via the stop determination unit 310 to the functional units that should execute the instruction according to the functional unit number. As a result, a request presence / absence signal is output from each instruction decoding unit for each functional unit.

The issuance judging section 330 comprises functional units A to D
Are provided with four sets of AND circuit groups corresponding to the above. Each AND circuit group outputs the request presence / absence signal distributed by the distribution unit 320 as it is when the functional unit is in the above-described ready state, and outputs it as OFF when the functional unit is in the not-ready state. Here, a ready_n signal (n is A, B, C or D) indicating that the corresponding functional unit is in a ready state indicates that the corresponding functional unit is in a state capable of accepting an instruction. Functional unit
This is a 3-bit signal output from x. Issue determination unit 3
30 output signals (1A-3A, 1B-3B, 1C-3C, 1D-3
D) is valid (instruction can be issued) when both are logic "1". For example, the output signal 1A is issued by the instruction decoding unit 1 and the destination is the functional unit A, and the output signal 3B is issued by the issuer. Means the instruction decoding unit 3 and the issue destination is the functional unit B. <Instruction Issue Arbitration Unit 40> FIG. 9 is a block diagram showing a more detailed configuration example of the instruction issue arbitration unit 40 of FIG. The instruction arbitration unit 40 includes arbitration units 40A to 40D corresponding to the functional units A to D, respectively. Since each arbitration unit performs the same operation, the arbitration unit 40A will be described as a representative here. The arbitration unit 40A includes a priority order determination unit 41A and a determination assistance unit 42A.

The priority determining section 41A is provided with an issuing determining section 33.
In response to the signals 1A, 2A, and 3A output from 0 and the priority order PRI1 [1: 0], PRI2 [1: 0], and PRI3 [1: 0] of each logical processor, a valid request presence / absence signal is received. The one with the highest priority is output. FIG. 10 shows a control logic for realizing this function in the priority order determination unit 41A. FIG.
In (a), the priority order of the logical processors 1 to 3 specified in the PRI1, PRI2, and PRI3 fields in the PRI register is PR.
If I1>PRI2> PRI3, that is, at the priority level, (PRI1,
Inputs 1A, 2A, 3A when PRI2, PRI3) = (High, Medium, Low)
And outputs 1A ', 2A', and 3A '. Although not shown, if the priority is PR1>PR3> PR2, PR2>
If PR1> PR3, PR2>PR3> PR1, if PR3>PR1> PR2
In the case of, also in the case of PR3>PR2> PR1, the same control logic is obtained simply by replacing any of the signal names, so that the description is omitted.

In FIG. 10B, the priority order is PRI1 = PRI2
> PRI3, that is, at the priority level (PRI1, PRI2, PR
I3) = (high, high, medium), (high, high, low) or (medium, medium,
Low). Although not shown, when the priority is PR1 = PR3> PR2, when PR2 = PR1> PR3, PR2 = P
If R3> PR1, PR3 = PR1> PR2, then PR3 = PR2> PR1
In any case, the same control logic is obtained simply by replacing the signal names, so that the description is omitted. Also, when two or more valid signals have the highest priority among the input signals, such as an output signal with a dashed line in the drawing, the priority determination unit 41A temporarily determines that these signals are "1". "Is output.

In FIG. 10C, the priority order is PRI1> PRI2
= PRI3, ie (PRI1, PRI2, PRI3) = (high,
The case of (medium, middle), (high, low, low) or (medium, low, low) is shown. Although not shown, the priority order is PR1
> PR3 = PR2, PR2> PR1 = PR3, PR2> PR3 = P
In the case of R1, in the case of PR3> PR1 = PR2, and in the case of PR3> PR2 = PR1, the same control logic is obtained by simply rewriting any signal name, so that the description is omitted.

When the priority order is PRI1 = PRI2 = PRI3, and there are two or more valid input signals, the priority order judging section 41A outputs all valid signals as "1" for the time being. . The determination assisting unit 42A determines that the logical processors having the same priority set in the PRI register issue an instruction issue request at the same time, that is, in the output (1A ', 2A', 3A ') of the priority determining unit 41A. "1" is 2
If there are more than one, it is determined which is to be set to "1" in order to adjust the instruction issuance among the logical processors.
For example, the determination assisting unit 42A (1) changes the logical processor that sets “1” every cycle (one cycle or several cycles) (2) gives priority to the logical processor that could not issue an instruction before (3) fixed One is decided beforehand.
Further, these may be switched. <Instruction Issuance Prohibition Unit 50> FIG. 11 is a block diagram showing a more detailed configuration example of the instruction issuance prohibition unit 50 of FIG. The instruction issuance prohibition unit 50 includes prohibition units 50A to 50D corresponding to the functional units A to D, respectively, and an issuance notification unit 55. Since each prohibition unit performs the same operation, the prohibition unit 50A will be described as a representative here.

The prohibition unit 50A, when an external interrupt request, an internal interrupt request, an access exception such as a cache miss or a memory access error, or a trap instruction occurs as an urgent process, identifies the logical processor ID of the source of the occurrence. A prohibition control unit 5 that detects and controls to prohibit instruction issuance to the logical processor for one cycle.
1A and the arbitration unit 40A according to the instruction of the prohibition control unit 51A.
To output an instruction issue instruction (1AAA to 3AAA) to the instruction selecting unit 70 based on the result of gating the output signals (1AA to 3AA)
And an OR circuit for notifying the functional unit A of the instruction issuance.

The issuance notifying section 55 is composed of three OR circuits corresponding to the instruction decoding sections 1 to 3, and is provided with prohibiting sections 51A to 51D.
Each time an instruction issuance instruction is output from the logical processor, an issuance notification is output to notify the corresponding instruction decoding unit that the next instruction may be issued. <Functional Unit B> The functional unit B is configured to execute the above-described various dedicated instructions and instructions for reading the PRI register, the EXCL register, and the IR register, in addition to executing the integer operation instruction.

In the present embodiment, the above-mentioned dedicated instructions are executed by the functional unit B, but may be executed by other functional units. In FIG.
FIG. 4 is an explanatory diagram showing the contents of execution of the dedicated instruction and the read instruction by the functional unit B. In the figure, “x” indicates the logical processor number of the issue source of the instruction, and “y” indicates the ID of the logical processor other than the issue source of the instruction. This logical processor number is notified to the functional unit B by a signal (1BBB to 3BBB in FIG. 11) output from the prohibition unit 50B.

As shown in the figure, the functional unit B has “in
For the "c pri" instruction, the PRIx [1] bit of the PRI register is set to 1 in the supervisor mode, and PRIx [0] in the user mode.
Set the bit to 1. For the "dec pri" instruction,
In the supervisor mode, PRIx [1] is set to 0, and in the user mode, the PRIx [0] bit is set to 0.

For the "halt" instruction, 1 is set to the PRIx [2] bit of the PRI register of the logical processor.
For the “excsv” instruction, the EXCLx bit and the EXCLy bit of the EXCL register are set to 1 and 0, respectively. For example, when the logical processor 2 is a source of this instruction, the functional unit B sets the EXCL2 bit to 1, and sets the EXCL3 and EXCL1 bits to 0.

For the "retex" instruction, the EXCLx bit is set to "0". As described above, different bits in the register are operated according to the logical processor that issued the instruction, even if the dedicated instruction is the same instruction. For each mov instruction shown in FIG. 12, the functional unit B executes as follows.

The "mov PRI, R0" instruction is an instruction for transferring the contents of the PRI register to the R0 register. In response to this instruction, the functional unit B executes the instruction as follows. PR
For the MYID field (= PRI [31:29]) in the I register, the logical processor ID of the issue source of the instruction is R0 [31: 2
Write to each bit of [9]. PRI [11: 3] (=
For each bit of the PRI3, PRI2, and PRI1 fields), the data is read out and transferred to [11: 3] in the R0 register.

As for PRI [2: 0] (= MYPRI field), PRIx corresponding to the logical processor ID of the instruction issue source in the PRI3, PRI2, and PRI1 fields is written to each bit of R0 [31:29]. . The “mov IR, R0” instruction is an instruction to transfer the contents of the IR register to the R0 register. In response to this instruction, the functional unit B writes the logical processor ID of the issue source of the instruction into each bit of R0 [31:29] for the MYID field (= IR [31:29]) in the IR register. IR
For each bit of [2: 0] (= IR3, IR2, IR1 bits),
The value is read and written to each bit of R0 [2: 0].

The "mov EXCL, R0" instruction is an instruction for transferring the contents of the EXCL register to the R0 register. The execution contents of the functional unit B for this instruction are described in the above "mov IR, R
This is similar to “0” except that the transfer source is the IR register. By executing the above read instruction,
Each logical processor can obtain the value of its own logical processor ID and the state of other logical processors (priority, self-stop state, exclusive stop state, etc.) from the read MYID field. <Detailed Configuration of Priority Control Unit 60> FIG. 13 is a block diagram showing a detailed configuration of the priority control unit 60.

The priority control unit 60 controls the PRI register 6
1, IR register 62, EXCL register 63, selector 6
4. A continuous cycle priority unit 69 is provided. PRI register 6
1, the IR register 62 and the EXCL register 63 have already been described with reference to FIG. 3, FIG. 6 and FIG.
Here, the hardware configuration will be described.

These registers 61 to 63 are connected to the internal bus of the multi-thread processor, and read and write to the functional unit B via the internal bus.
Upper 3 bits of these registers (MYID field)
Does not have a function of holding data, and transparently outputs the logical processor ID to the internal bus when a register read instruction is executed. At this time, the logical processor ID
Is a signal output from the prohibition unit 50B (1B in FIG. 11).
BB to 3BBB).

The lower 3 bits of the PRI register 62 are P
When the read instruction of the RI register is executed, the output of the selector 64 is transparently output to the internal bus. The selector 64 selects the PRI3, PRI2, and PRI1 fields in the PRI register 62 corresponding to the logical processor ID of the instruction issuing source and executes “MYPRI” in the IR register 62 when executing the read instruction of the PRI register. Field to the internal bus.

The continuous cycle priority section 69 has a function of temporarily changing the priority to a higher level while a specific instruction sequence is executed. Here, the specific instruction sequence refers to an instruction sequence that needs to be executed in a continuous cycle, for example, when reading and writing a resource shared with another logical processor. An example of a specific instruction sequence is shown below. However, instructions are expressed in mnemonics. The following is a comment indicating the content of the instruction. LOOP:; Label aldst MEM [100], R0; Also called an atomic (Atomic LoaD STart) instruction.

Transfer data in memory (address 100) to RO test R0; if R0 = 0, set zero flag to 1; beq LOOP; if zero flag is 1, branch to label LOOP store R1, MEM [100]; The specific instruction sequence for transferring the data of the register R1 to the memory 100 reads the address 100 of the memory,
If the read data is 0, the data in the register R1 is written to address 100 of the memory. If the read data is not 0, it indicates a loop process of repeatedly reading until the read data becomes 0. The specific instruction sequence needs to be executed in a continuous cycle when, for example, the memory 100 is used as a shared resource of a plurality of logical processors. In other words, while one logical processor is executing the specific instruction sequence, the other logical processor
Address 00 must not be rewritten.

In order to guarantee that such a specific instruction sequence is executed in a continuous cycle, the continuous cycle priority unit 69 detects the start of execution of the first instruction of the specific instruction sequence by one functional unit. During a predetermined number of consecutive cycles from the execution cycle of the instruction, the priority of the priority control unit 60 is set so that the priority of the logical processor (instruction stream) issuing the instruction is higher than the other logical processors. Change temporarily. <Continuous cycle priority section 69> Continuous cycle priority section 69
Corresponds to the specific instruction detecting unit 65 and the counter 6 as shown in FIG.
6, a comparator 67 and a selector 68.

In the figure, a specific instruction detecting unit 65 detects that the execution of the first instruction of the specific instruction sequence (hereinafter referred to as a specific instruction) has been started. In the above specific instruction sequence example, al
The dst instruction is detected as a specific instruction. More specifically, the specific instruction detecting unit 65 notifies the instruction decoding units 1 to 3 that the specific instruction has been decoded, and outputs the specific instruction to the instruction issue prohibiting unit 50.
Receives the notification that the issuance has been issued to the one functional unit, and detects the start of execution of the specific instruction by receiving both the notifications.

The counter 66 counts the number of cycles required to execute the specific instruction sequence when the start of execution of the specific instruction is detected. In the above example, the counter 66 counts three cycles required to execute the three instructions following the aldst instruction. Therefore, when the start of execution of the specific instruction is detected, the initial value 3 is loaded and the counter 66 counts down to zero. Thereby, it becomes 0 in the execution cycle of the above store R1, MEM [100].
When the specific instruction sequence is in a loop process, the counter 66 starts counting from the initial value 3 every time an aldst instruction is detected.

The comparator 67 determines whether or not the count value of the counter 66 matches 0. That is, it is determined whether or not the period is a continuous cycle of the specific instruction sequence.
The selector 68 is a 6-bit 4-input / 1-output selector, and is used to temporarily change the priority order during a continuous cycle. FIG. 14 is an explanatory diagram showing the relationship between the selection signal input to the selector 68 and the output value. Although the input value of the selector 68 is omitted in FIG. 13, “PRI [11: 3] (= PRI
3 [1: 0], PRI2 [1: 0], PRI1 [1: 0] "," 110000 "," 00110
0 ”and“ 000011 ”.

According to the figure, when the output of the selector 68 is normal, that is, not during a continuous cycle (when the count value = 0), the PRI [11:
3] (= PRI3,2,1 field) The priority specified is output. In the case of a continuous cycle period (when the count value does not match 0), the selector 68 determines “110000” if the issuing source of the specific instruction is the logical processor 3, “001100” if the issuing source of the logical processor 2 is Processor 1
If so, replace "000011" with "PRI [11: 3] (= PRI3 '[1: 0], PRI
2 '[1: 0], PRI1' [1: 0] ".

Thus, during the continuous cycle, the priority is temporarily changed so that the priority of the logical processor that issues the specific instruction is the highest. The operation of the multi-thread processor configured as described above according to the present embodiment will be described. <Operation of Setting Priority, Self-Stop State, and Exclusive Stop> In the multi-thread processor of the present embodiment, the incpr instruction and the decpr instruction are used for setting and changing the priority for each instruction stream (logical processor), and the halt is used for the self-stop. Instruction, e for exclusive stop
Dedicated instructions called xcsv instruction and retex instruction are prepared. These dedicated instructions need to be appropriately set in advance in the program that generates the instruction stream.

For example, in a part of a program to be processed with a higher priority, in
What is necessary is just to set a cpr instruction and a decpr instruction immediately after. The incpr instruction and the decpr instruction set as described above are executed by the functional unit B as follows. That is, depending on which of the logical processors 1 to 3 is the issuing source, the functional unit B targets the PRIx [0] bit in the user mode for the corresponding PRx field of the PRI register and sets the supervisor mode to the supervisor mode. In the case of, 1 or 0 is set for PRIx [1]. Thus, the priority can be dynamically changed for each logical processor as needed.

In a program part to be processed by stopping other logical processors and operating only its own logical processor, an excsv instruction is set immediately before the program part and a retex instruction is set immediately after the program part. Become. These instructions are also executed by the functional unit B in the same manner as described above. Conversely, in order to give priority to another logical processor and stop its own logical processor, a halt instruction is set. This instruction is also executed by the functional unit B. However, the stopped state of the logical processor is released by an interrupt request to the logical processor, so that an interrupt request needs to be input as appropriate. For example, an internal interrupt between logical processors depends on the IR register. In other words, the logical processor that issues the interrupt registers the IR register and
Reads the PRI register or EXCL register and reads its own MYI
After reading D and further determining the IRx bit corresponding to the interrupt destination logical processor, an internal interrupt request is set in the IR register by a normal transfer instruction. <Overall Operation> For example, when an instruction issuance request (a request flag and a number of a functional unit B) is output to the functional unit B as a result of the decoding by the instruction decoding unit 1, the logical processor 1 is in a self-stop state or is in a state of another logical processor. In the stop state due to the exclusive stop, the stop determination unit 310 in the instruction issue determination unit 30 does not output the request flag itself as invalid. This allows the other logical processors 2 and 3 to use the functional unit.

When the logical processor 1 is neither in the self-stop state nor in the stop state due to the exclusive stop of the other logical processors, it is distributed to the functional unit B in the distribution unit 320 in the instruction issue determination unit 30, and B
If is in the ready state with respect to the logical processor 1, the issuance determination unit 330 determines that issuance is possible.

Next, the instruction issuance arbitration unit 40 receives the instruction issuance request for each functional unit from the instruction issuance determination unit 30 and uses the priority order for each logical processor from the priority order control unit 60 to execute the function unit. Determine the logical processor that can be issued to. For example, when only the instruction issuance request from the instruction decoding unit 1 is output to the functional unit B (when only 1B among 1B to 3B in FIG. 9 is valid), the instruction issuance arbitration unit 40 Instruction issue request is valid (1BB in Fig. 9)
Only 3BB is valid for 1BB).

For example, the instruction decoding unit 1 decodes the instruction to the functional unit A, the instruction decoding unit 2 decodes the instruction to the functional unit B, the instruction decoding unit 3 decodes the instruction to the functional unit C, and When all the functional units are in the ready state, the instruction issue arbitration unit 40 makes all three instruction issue requests valid. on the other hand,
The instruction decoding unit 1 decodes an instruction for the functional unit A,
When the instruction decoding unit 2 also decodes the instruction for the functional unit A (when 1A and 2A in FIG. 9 are simultaneously effective), only one of the instructions can be issued, and therefore the priority determination unit 41
A determines the priority order from the PRI register in the priority order control unit 60, and issues an instruction from a higher priority order. If the priority of the logical processor 1 and the priority of the logical processor 2 are the same in this case, only one of the instruction issuance requests is validated by the determination assisting unit 42A.

Further, the instruction issuance prohibiting unit 50 is adapted to issue an instruction to an instruction determined to be issued by the instruction issuance arbitration unit 40 when an urgent process occurs in any of the logical processors. Ban. The instruction issuance determination unit 30 and the instruction issuance prohibition unit 50 both have a function of excluding an instruction issuance request from candidates for instruction issuance.
Functions are shared for the following reasons.

That is, the cause of the fact that the instruction cannot be accepted at an early stage is determined by the instruction issuance determination unit 3.
0, the instruction of the logical processor that cannot be accepted can be judged as being unissueable and excluded from the candidates for instruction issuance. However, if the cause is not known only at a late stage, the instruction If it is attempted to remove the instruction, the final decision as to whether or not the instruction can be issued is delayed, which affects the frequency of the processor.

For example, when it is assumed that the process from the instruction issue determination to the instruction issue prohibition is performed in one cycle, the instruction issue determination unit 30 is notified of the instruction issue disable factor at the end of the cycle. Must be removed from the list of candidates. In this case, it is necessary to take a sufficiently long cycle length, which is a major factor that hinders the improvement of the clock frequency. Therefore, the instruction issuance prohibition unit 50 prohibits the issue of the instruction issuance prohibition factor that is known only at a late stage. Of course, when the instruction issuance of the logical processor which is the instruction issuance prohibition unit 50 is prohibited, even if an instruction from another logical processor can be issued, the instruction is not issued instead. This is because instructions to be issued have already been narrowed down to one for each of the functional units A to D.

Thereafter, the instruction selecting section 70 sets the instruction decoding section 1
The instruction contents and operations decoded by the instruction issue instruction are issued from the instruction issue prohibition unit 50 (1AAA to 3AA in FIG. 11).
A, 1BBB to 3BBB, 1CCC to 3CCC, 1DDD to 3DDD). In the present embodiment, a case has been described in which the number of logical processors is three and the number of functional units is four, but it is naturally possible to change these numbers arbitrarily.

Further, the contents of the PRI register may be shared by a plurality of registers. For example, each PRIx [2] bit for self-stop and each PRIx [1: 0] field for priority may be separate registers. Conversely, all or some of the PRI register, the IR register, and the EXCL register may be configured as one register.

Further, the specific instruction detecting section 65 may detect the start of the execution of the specific instruction by receiving the notification from the functional unit which has started executing the instruction. In the present embodiment, an example in which the present invention is applied to a case where a plurality of logical processors compete for instruction issuance with respect to a functional unit has been described. If applicable. This will be described as another embodiment. <Other Embodiments> In this embodiment, priorities among logical processors can be used for arbitration when accessing resources shared by a plurality of logical processors. An example is shown below.

FIG. 2 is a block diagram showing a configuration of a multi-thread processor according to another embodiment of the present invention. The multi-thread processor includes a cache memory 100, instruction decoding units 111 to 113, a register group 131
To 133, the instruction fetch control unit 140, the instruction issuance control unit 150, the priority control unit 60, and the functional units A20 to D
23, a register control unit 170 is provided. FIG.
The components with the same numbers as are omitted because they are the same.
The different points will be mainly described.

In FIG. 2, the cache memory 100
Is a cache memory for the program from which the instruction stream is generated. The instruction decoding units 111 to 113 are the same as the instruction decoding units 1 to 3 in FIG. 1, respectively, except that they are controlled by the instruction fetch control unit 140. The register groups 131 to 133 are register files each including a plurality of registers, and are provided in the instruction decoding units 111 to 113 in one-to-one correspondence. Accordingly, the logical processors 1 to 3 also correspond one-to-one.

The instruction fetch control unit 140 differs from the instruction issuance arbitration unit 40 and the instruction issuance prohibition unit 50 shown in FIG. 1 in that arbitration and inhibition of contention of an instruction fetch request instead of an instruction issuance request are different. Except for the same function. That is, when the designation of the priority order for each logical processor is input from the priority order control unit 60, and a plurality of instruction decoding units simultaneously issue instruction fetch requests to the cache memory 100, the instruction fetch request is made according to the priority order. When determining the fetch order or stopping the execution of a specific logical processor, the instruction fetch from the instruction decoding unit of the logical processor is stopped.

The instruction issuance control unit 150 describes the instruction issuance determination unit 30, the instruction issuance arbitration unit 40, the instruction issuance prohibition unit 50, and the instruction selection unit 70 shown in FIG. 1 as one constituent element. The description is omitted because it is equivalent to the function described above. The register control unit 170 is similar to the instruction issuance determination unit 30 and the instruction issuance arbitration unit 40 shown in FIG. 1 except that the contention of the register access request is stopped and arbitrated instead of the instruction issuance request. Has functions. That is, when the designation of the priority order for each logical processor or the like is input from the priority order control unit 60 and a plurality of functional units simultaneously output data write requests to the same register group, The instruction issuance control unit determines the writing order.

With the above configuration, arbitration and stop according to the priority order can be performed not only in the case of contention of the logical processor for the functional unit but also for the contention of the instruction fetch request to the cache memory and the contention of the data access request to the register group. Can be implemented. In the above embodiment,
Although the number of instruction streams and the number of logical processors are three and the number of functional units is four, any number may be used.

Although the priority level is 2 bits and 3 levels, any number of priorities may be used. Further, the control register has a 32-bit width, but may have another bit width. Also, when a branch occurs simultaneously in a plurality of logical processors, resources shared for address calculation and cache can be arbitrated according to the priority order as in the other embodiments.

Further, in the above embodiment, the PRI register is configured to change the priority order exclusively by a dedicated instruction. However, the PRI register may be configured to be set and changed by hardware other than the dedicated instruction. In this case, the priority of each instruction stream is changed at a predetermined timing, or the state of the instruction stream is monitored and the external priority or internal factor of hardware is used as a trigger to change the priority. It may be.

In the above embodiment, when two or three priorities are the same in the priority order judging section 41A of FIG. 9, all of them are enabled and output once. May be output. In that case, the determination assisting unit 42A can be deleted. Although the determination assisting unit 42A of FIG. 9 is provided after the priority order determining unit 41A, the priority order controlling unit 60A
And a priority determining unit 41A, the priority may be dynamically changed when there are a plurality of the same priority.

Further, in the above embodiment, the MYPRI field in the PRI register outputs the priority of the issuer of the read instruction of the PRI register. In the same manner, for example, the MYDATA field is provided.
Data indicating a state (status data, error information, etc.) may be output for each logical processor. The urgent process detected by the prohibition unit 50A may be various events or various exception processes. Here, the various events are an external interrupt, an internal interrupt, and the like. Various types of exception processing include access exceptions such as cache misses and memory access errors, trap instructions, operation exceptions, and operation execution errors.

In the above embodiment, each instruction decoding section decodes one instruction per instruction stream, and can issue only one instruction at a time. However, the present invention is not limited thereto, and the instruction decoding unit may decode a plurality of instructions for one instruction stream and issue a plurality of instructions at the same time.

[0087]

As described above, the multi-thread processor according to the present invention comprises:
A plurality of functional units each executing an instruction and a plurality of instruction units are provided corresponding to the instruction stream, each of which decodes an instruction, designates a functional unit to execute the instruction, and issues the decoded instruction to the functional unit. A plurality of instruction decoding means for creating an instruction issue request to be performed, a holding means for retaining the priority of the instruction stream for each instruction stream, and two or more instruction issue requests simultaneously specifying one functional unit. And a control means for determining a decoded instruction to be issued to the functional unit in accordance with the priority held in the holding means.

According to this configuration, an instruction to be issued to each functional unit (instruction decoding result) is determined in accordance with the priority, so that a variation in load among a plurality of instruction streams can be flexibly determined according to the priority. Adjustments can be made, and the processing performance required for each instruction stream can be appropriately realized, and the overall processing efficiency can be improved. Here, the holding unit further holds a flag group that can be set by the instruction and indicates whether the instruction flow should be stopped or executed for each instruction flow, and the control unit includes: an arbitration unit that makes the determination; If a flag indicating the instruction flow is set, a stop means for stopping the instruction flow by making the above-described determination excluding the instruction issue request of the instruction flow corresponding to the flag may be provided.

According to this configuration, when the instruction stream is in an idle state or a waiting state during its execution, the instruction stream can be stopped. That is, as a result, other instruction streams can be executed with priority, and the overall processing performance can be further improved. Here, the control unit may further determine, when an urgent process occurs for any of the instruction streams, an instruction belonging to the instruction stream and determined to be issued by the control unit. And a prohibition unit for temporarily prohibiting the issuance of an instruction to a functional unit.

According to this configuration, when an urgent process occurs for a certain instruction stream (logical processor),
The issuing means of the logical processor is temporarily prohibited by the prohibition means. In other words, instruction issuance is temporarily prohibited for the number of cycles required until the process shifts to urgent processing. This makes it possible to speed up the transition to the interrupt processing. \ u Moreover, the prohibition means can prohibit the issuance of the instruction after the instruction to be issued is determined by the arbitration means. Can be effectively prohibited. For example, there is an effect that even when an urgent process occurs late in a machine cycle, the process can be effectively prohibited.

Here, one of the functional units receives the dedicated instruction for changing the priority, and changes the priority of the instruction stream to which the dedicated instruction belongs among the priorities held in the holding means. You may comprise. Here, the dedicated instruction is
It consists only of an operation code instructing to raise or lower the priority. One of the functional units, when a decoding result of the dedicated instruction is issued, determines the instruction decoding means that issued the dedicated instruction, and determines The priority of the instruction stream corresponding to the executed instruction decoding means may be increased or decreased.

According to this configuration, the dedicated instruction does not require the ID of the instruction stream or the operand indicating the bit position for specifying the instruction stream. The priority of the instruction stream can be easily changed. Further, since the priority of the instruction stream to which the instruction belongs is changed by the one functional unit, the priority of a different instruction stream is not erroneously rewritten, and a malfunction can be prevented. For example, RGB
When the same image processing is performed on the image data for each color of a color image, that is, when one image processing program is executed independently and simultaneously as three instruction streams, the information is concealed (the program discriminates any one of RGB). No need to do)
And the independence of the instruction flow can be guaranteed. As a result, the reliability of the OS and the entire system is improved.

Here, the holding means includes a control register having a read-only first field, and one of the functional units issues the read command when a decoding result of the control register read command is issued. It may be configured to determine the instruction decoding means that has performed the processing and output the ID of the instruction stream corresponding to the instruction decoding means to the internal bus as read data of the first field.

According to this configuration, when one program is executed independently and simultaneously as three instruction streams as described above, three virtual programs, which are actually one program, are executed in parallel. Will be. Each virtual program (or instruction stream)
Can easily know the ID of the instruction stream itself by reading the first field.

Here, the holding means has a control register, and the control register further has an individual field for each instruction stream for holding data unique to the instruction stream, and a second field exclusively for reading. When executing the read instruction of the control register, one of the functional units further reads an individual field for each instruction stream, and reads a unique field of an instruction stream corresponding to an instruction decoding unit that has issued the read instruction. The data may be output to the internal bus as read data of the second field.

According to this configuration, the virtual program (or instruction stream) can easily know its own priority by reading the second field. Here, the holding means has a priority field for holding a priority for each instruction stream, and the priority field is composed of a small field indicating a priority for each execution mode of the instruction stream. First, when the decoding result of the dedicated instruction is issued, the instruction decoding means that issued the dedicated instruction is determined, and the priority field of the instruction stream corresponding to the determined instruction decoding means is used for the current execution mode. May be configured to raise or lower the priority of the small field of.

According to this configuration, the priorities can be set independently in the execution mode, for example, the user mode and the supervisor mode, and when returning to another mode, the original priority remains unchanged. Can be saved. Here, the multi-thread processor further includes a specific instruction detecting means for detecting that one of the functional units has started executing the specific instruction, a specific instruction detecting means for issuing a result of decoding the specific instruction, and a specific instruction detecting means for detecting the specific instruction. When the start of execution is detected, the priority of the instruction stream corresponding to the instruction decoding means that has issued the specific instruction is temporarily changed for a predetermined period. A temporary change unit that changes the priority of the instruction stream to a higher priority than other instruction streams may be provided.

According to this configuration, since the temporary change means temporarily changes the priority, it is possible to guarantee that the instruction sequence starting with the specific instruction in the instruction stream is executed in a continuous cycle. . Here, the multi-thread processor further includes exclusive stop data holding means for holding exclusive stop data indicating whether or not another instruction stream should be exclusively stopped for each instruction stream, and the stop means further comprises: The instruction decoding unit corresponding to the instruction stream stopped by the exclusive stop data may stop notifying the arbitration unit of the instruction issuance request.

According to this configuration, one instruction stream can forcibly stop processing another instruction stream. Therefore, it is possible to adjust the processing performance between instruction streams in a large range. Further, a multi-thread processor that achieves the above object is a multi-thread processor that simultaneously and independently executes a plurality of instruction streams in parallel, comprising: an instruction cache that temporarily stores instructions of the plurality of instruction streams; A plurality of instruction fetch means for fetching an instruction of the instruction stream from the instruction cache; a priority specifying means for specifying a priority for each of the plurality of instruction streams; and two or more instruction cache means. An instruction fetch control means for arbitrating the instruction fetch request according to the priority of the priority control circuit when the instruction fetch request is issued at the same time.

According to this configuration, when instruction fetch requests from a plurality of instruction fetch units compete with the instruction cache, arbitration is performed in accordance with the priority. There is an effect that the processing performance of the program can be dynamically adjusted.
In addition, a multi-thread processor that achieves the above object includes a plurality of functional units that execute an instruction and a plurality of functional units that fetch an instruction from an instruction cache, decode the instruction, specify a functional unit to execute the instruction, and output an instruction issue request. A multi-thread processor having the same number of register sets as the instruction decoding unit and the same number of instruction streams as the instruction decoding unit simultaneously and independently. Holding means for holding the priority of an instruction stream, which can be set for each, and control for arbitrating according to the priority when two or more instruction streams simultaneously compete for resources shared by a plurality of instruction streams Means for competing for the shared resource, competing for an instruction issue request from two or more instruction decoding units for one functional unit, Conflict instruction fetch request from the instruction decode unit of the above, and is configured to be any of the access request conflicts of two or more functional units for one of the register sets.

According to this configuration, when processing requests from a plurality of instruction streams compete for resources shared by the instruction streams, arbitration is performed according to the priority, so that the processing performance for each instruction stream is flexibly improved. There is an effect that can be adjusted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a multi-thread processor according to an embodiment of the present invention.

FIG. 2 is a block diagram of a multi-thread processor according to another embodiment of the present invention.

FIG. 3 is an explanatory diagram of a priority designation register of the instruction stream control device according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of lower two bits of a priority specification register of the instruction flow control device according to the embodiment.

FIG. 5 is an explanatory diagram of upper one bit of a priority designation register of the instruction flow control device in the embodiment.

FIG. 6 is a configuration diagram of an internal interrupt register of the instruction flow control device according to the first embodiment.

FIG. 7 is a configuration diagram of an exclusive stop register of the instruction flow control device in the embodiment.

FIG. 8 is a block diagram showing a more detailed configuration example of an instruction issuance determination unit in the embodiment.

FIG. 9 is a block diagram showing a more detailed configuration example of an instruction issuance arbitration unit in the embodiment.

FIG. 10 is an explanatory diagram showing control logic of a priority order determination unit in the embodiment.

FIG. 11 is a block diagram showing a more detailed configuration example of an instruction issuance prohibition unit in the embodiment.

FIG. 12 is an explanatory diagram illustrating execution contents of a dedicated instruction and a control register read instruction by a functional unit.

FIG. 13 is a block diagram illustrating a detailed configuration of a priority control unit.

FIG. 14 is an explanatory diagram showing a relationship between a selection signal input to a selector in a continuous cycle priority section and an output value.

FIG. 15 is a block diagram illustrating a configuration of a conventional multithread processor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Instruction decoding part 2 Instruction decoding part 3 Instruction decoding part 20 Function unit A 21 Function unit B 22 Function unit C 23 Function unit D 30 Instruction issue determination part 40 Instruction issue arbitration part 50 Instruction issue prohibition part 60 Priority control part 70 Instruction Selection section

Claims (38)

[Claims] 1. A multi-thread processor for executing a plurality of instruction streams, comprising: a plurality of functional units each for executing an instruction; and a plurality of functional units provided corresponding to the instruction stream;
A plurality of instruction decoding means for designating a functional unit in which the instruction is to be executed and for generating an instruction issue request for requesting that the decoded instruction be issued to the functional unit; Holding means for holding the degree of execution, and when two or more instruction issuance requests specify one functional unit at the same time, decode instructions to be issued to the functional unit according to the priority held by the holding means. A multi-thread processor, comprising: a control unit for determining. 2. The holding unit further holds a flag group that can be set by an instruction and indicates whether the instruction flow should be stopped or executed for each instruction flow, and the control unit performs the determination. And when the flag indicating the stop is set, a stop means for stopping the instruction flow by making the determination excluding the instruction issue request of the instruction flow corresponding to the flag. The multi-thread processor according to claim 1, wherein: 3. The control means further determines that if an urgent process occurs for any of the instruction streams, the control means determines that the instruction belongs to the instruction stream and should be issued by the control means. 3. The multi-thread processor according to claim 2, further comprising a prohibition unit for temporarily prohibiting the issuance of the instruction to the functional unit. 4. The processing requiring urgency includes an interrupt request,
4. The multi-thread processor according to claim 3, wherein the event is any one of events notifying occurrence of a cache miss. 5. One of the functional units receives a dedicated instruction instructing a change of the priority, and changes the priority of the instruction stream to which the dedicated instruction belongs among the priorities held in the holding means. The multi-thread processor according to claim 1, wherein: 6. The dedicated instruction comprises only an operation code instructing to raise or lower the priority, and one of the functional units issues the dedicated instruction when a decoding result of the dedicated instruction is issued. 6. The multi-thread processor according to claim 5, wherein said instruction decoding means is determined, and the priority of an instruction stream corresponding to said determined instruction decoding means is raised or lowered. 7. The holding unit includes a control register having a first field for reading only, and one of the functional units issues the reading instruction when a decoding result of the reading instruction of the control register is issued. 7. The method according to claim 6, wherein the instruction decoding means determines the instruction decoding means, and outputs an instruction stream ID corresponding to the instruction decoding means to the internal bus as read data of the first field.
The multithreaded processor as described. 8. The control register further has a priority field for each instruction stream for holding the priority, and one of the functional units has issued a decoding result of a control register read instruction. 8. The multi-thread processor according to claim 7, wherein, in the case, each priority field is read. 9. The holding means has a control register, and the control register further has an individual field for each instruction stream for holding data unique to the instruction stream, and a read-only second field. When one of the functional units executes a read instruction of the control register, the functional unit further reads an individual field for each instruction stream, and reads a unique field of an instruction stream corresponding to an instruction decoding unit that has issued the read instruction. 7. The multi-thread processor according to claim 6, wherein the data is output on the internal bus as read data of the second field. 10. The multi-thread processor according to claim 9, wherein the data unique to the instruction stream is a priority. 11. The holding means has a priority field for holding a priority for each instruction stream, wherein the priority field comprises a small field indicating the priority of each execution mode of the instruction stream. One of the units, when a decoding result of the dedicated instruction is issued, determines the instruction decoding unit that has issued the dedicated instruction and determines the current one of the priority fields of the instruction stream corresponding to the determined instruction decoding unit. 7. The method according to claim 6, wherein the priority of the small field for the execution mode is increased or decreased.
The multithreaded processor as described. 12. A specific instruction detecting means for detecting that one of the functional units has started executing a specific instruction, detecting which instruction decoding means has issued a decoding result of the specific instruction, and starting execution of the specific instruction. Temporary detection means for temporarily changing the priority of an instruction stream corresponding to the instruction decoding means which has issued the specific instruction to a higher priority than other instruction streams for a predetermined period when detected. The multi-thread processor according to claim 1, wherein: 13. A multi-thread processor for executing a plurality of instruction streams, comprising: a plurality of functional units each for executing an instruction;
A functional unit to execute the instruction, a plurality of instruction decoding means for creating an instruction issue request for requesting the functional unit to issue the decoded instruction, and the priority of each instruction stream is maintained. Priority holding means, self-stop data holding means for holding self-stop data indicating whether the instruction stream should be executed or stopped for each instruction stream, and an instruction issuance request notified from a plurality of instruction decoding units In response, when two or more instruction issuance requests specify one functional unit at the same time, a decoded instruction to be issued to the functional unit is determined according to the priority held in the priority holding means. An arbitration unit; and an arbitration unit that receives, from the instruction issuance requests notified from the plurality of instruction decoding units to the arbitration unit, an instruction arbitration unit corresponding to an instruction stream stopped by the self-stop data. A stopping means for stopping notification of an instruction issue request to a stage. 14. The multi-thread processor further comprises exclusive stop data holding means for holding exclusive stop data indicating whether or not another instruction stream should be exclusively stopped for each instruction stream; 14. The multi-thread processor according to claim 13, further comprising: stopping notification of an instruction issuance request from the instruction decoding unit corresponding to the instruction stream stopped by the exclusive stop data to the arbitration unit. 15. One of the functional units, when a decoding result of a dedicated instruction for instructing a change of a priority is issued,
14. The multi-thread processor according to claim 13, wherein the priority is changed according to the instruction. 16. The dedicated instruction comprises only an operation code instructing to raise or lower the priority, and one of the functional units issues the dedicated instruction when a decoding result of the dedicated instruction is issued. 16. The multi-thread processor according to claim 15, wherein the determined instruction decoding means is determined, and the priority of the instruction stream corresponding to the determined instruction decoding means is increased or decreased. 17. The reading device according to claim 17, wherein the holding unit is a first read-only first unit.
A control register having a field, wherein one of the functional units, when a decoding result of a read instruction of the control register is issued, determines an instruction decoding unit that issued the read instruction, and responds to the instruction decoding unit. 2. An ID of an instruction stream to be output as read data of a first field on an internal bus.
7. The multi-thread processor according to 6. 18. The control register further has a priority field for each instruction stream for holding the priority, and one of the functional units has issued a decoding result of a control register read instruction. 18. The multi-thread processor according to claim 17, wherein in the case, each priority field is further read. 19. The holding means has a control register, and the control register further has an individual field for each instruction stream for holding data unique to the instruction stream, and a second field dedicated to reading. When one of the functional units executes a read instruction of the control register, the functional unit further reads an individual field for each instruction stream, and reads a unique field of an instruction stream corresponding to an instruction decoding unit that has issued the read instruction. 17. The multi-thread processor according to claim 16, wherein data is output as read data of a second field onto an internal bus. 20. The multi-thread processor according to claim 19, wherein the data unique to the instruction stream is a priority. 21. The holding means has a priority field for holding a priority for each instruction stream, wherein the priority field comprises a small field indicating a priority for each execution mode of the instruction stream. One of the units, when a decoding result of the dedicated instruction is issued, determines the instruction decoding unit that has issued the dedicated instruction and determines the current one of the priority fields of the instruction stream corresponding to the determined instruction decoding unit. 2. The method according to claim 1, wherein the priority of the small field for the execution mode is increased or decreased.
9. The multi-thread processor according to item 9. 22. A specific instruction detecting means for detecting that one of the functional units has started executing a specific instruction, detecting which instruction decoding means has issued a decoding result of the specific instruction, and starting the execution of the specific instruction. Temporary detection means for temporarily changing the priority of an instruction stream corresponding to the instruction decoding means which has issued the specific instruction to a higher priority than other instruction streams for a predetermined period when detected. 14. The multi-thread processor according to claim 13, wherein: 23. A multi-thread processor for simultaneously and independently executing a plurality of instruction streams in parallel, wherein the plurality of functional units execute instructions simultaneously and independently, and a plurality of functional units are provided corresponding to the plurality of instruction streams. A plurality of instruction decoding means for extracting and decoding instructions in the instruction stream and identifying a functional unit to be issued to among the functional units, and a priority designation for designating a priority for each of the plurality of instruction streams Means for determining whether or not a decoded instruction can be issued to the functional unit to which the instruction is to be issued, based on a state of each functional unit indicating whether or not the instruction can be accepted; When it is determined that two or more instructions can be issued to one functional unit, the two or more instructions are arbitrated according to the priority specified by the priority specifying means, and the one or more instructions are arbitrated. Multi-thread processor, characterized in that it comprises an instruction issue arbitration means for determining an instruction to be issued to the ability unit. 24. The multi-thread processor, when an urgent process occurs in any one of the instruction streams, should be issued by the instruction issuance arbitration means, the instruction belonging to the instruction stream. 3. An instruction issuance prohibiting unit for temporarily prohibiting instruction issuance to a functional unit with respect to an instruction determined as follows.
3. The multi-thread processor according to 3. 25. The multi-thread processor according to claim 24, wherein the urgent processing includes one of an interrupt request and an event for notifying occurrence of a cache miss. 26. The system according to claim 26, wherein said priority designation means includes a control register for holding a priority of the instruction stream for each instruction stream, and wherein said priority is set by an instruction in the instruction stream. 25. The multi-thread processor according to 24. 27. One of the functional units receives a dedicated instruction instructing a change of a priority, and changes a priority of an instruction stream to which the dedicated instruction belongs among the priorities held in the holding unit. The multi-thread processor according to claim 26, wherein: 28. The instruction issuance and arbitration unit further determines that two or more instructions can be issued to one functional unit, and the instruction streams to which the two or more instructions belong have the same priority. 28. The multi-thread processor according to claim 27, wherein in that case, an instruction to be issued to said one functional unit is determined by a predetermined procedure. 29. The instruction issuance arbitration means, as the predetermined procedure, a procedure of periodically deciding that a different instruction stream has priority, and an instruction of an instruction stream different from the previous one based on the execution history of the instruction stream. 29. An apparatus according to claim 28, further comprising an auxiliary determination unit configured to determine an instruction to be issued in accordance with one of a procedure for determining an instruction to be issued and a procedure for fixedly determining an instruction in any instruction stream. Multi-threaded processor. 30. The control register has a priority field for each execution mode for each instruction stream, and the instruction issue arbitration unit performs the arbitration by referring to a priority field corresponding to an execution mode of the instruction stream. 28. The multi-threaded processor according to claim 26, wherein the processing is performed. 31. The priority designation means includes a control register having a priority field which can be set for each execution mode by a dedicated instruction in the instruction stream for each execution mode. Detecting the instruction stream corresponding to the instruction decoding means of the issuer and the execution mode thereof, and setting the priority according to the dedicated instruction in the priority field corresponding to the detected instruction stream and execution mode. Item 25. The multi-thread processor according to item 24. 32. The multi-thread processor according to claim 31, wherein the dedicated instruction comprises only an operation code, and indicates one of an increase and a decrease in the priority. 33. A multi-thread processor for executing a plurality of instruction streams simultaneously and independently in parallel, comprising: a plurality of functional units for executing instructions simultaneously and independently; and a plurality of functional units provided corresponding to the plurality of instruction streams. A plurality of instruction decoding means for extracting and decoding the instructions in the instruction stream, and for decoding the functional unit to be issued among the functional units; a priority for each of the plurality of instruction streams; and an execution state for each instruction stream. Issue a decoded instruction to the functional unit to which the instruction is to be issued based on the priority specifying means for specifying whether the instruction is accepted or not, and the state of each functional unit indicating whether the instruction can be accepted or not. Instruction issuance determination means for determining whether or not two or more instructions can be issued to one functional unit; and if it is determined that two or more instructions can be issued to one functional unit, the instruction is determined in accordance with the priority specified by the priority specification means. Multi-thread processor, characterized in that arbitrates instruction with upper and a command issuing arbitration means for determining an instruction to be issued to the functional units of the one. 34. The priority specifying means, comprising: a first register for holding a priority for each instruction stream that can be set by a first instruction; a priority register that can be set by a second instruction; A second register for holding a state flag for each instruction stream indicating a state, and a third register for holding an exclusive stop flag for each instruction stream, which can be set by a third instruction and indicating that all other instruction streams are stopped.
34. The multi-thread processor according to claim 33, further comprising a register, wherein the instruction issuance determination unit determines that an instruction in a suspended instruction stream cannot be issued in accordance with the status flag and the exclusive suspension register. 35. The first instruction is an instruction consisting only of an operation code instructing to raise or lower the priority, and the second instruction is composed only of an operation code instructing to enter a stop state. The third instruction is an instruction consisting only of an operation code instructing to stop another instruction stream, and one of the functional units is a first, second, or third instruction. Is issued, an instruction flow corresponding to the instruction decoding means from which the instruction is issued is detected, and a priority, a state flag, or an exclusive stop flag corresponding to the detected instruction flow is changed. Item 34. The multi-thread processor according to Item 34. 36. A multi-thread processor for simultaneously and independently executing a plurality of instruction streams in parallel, comprising: an instruction cache for temporarily storing instructions of the plurality of instruction streams; and an instruction cache provided corresponding to the plurality of instruction streams. A plurality of instruction fetch means for fetching an instruction of an instruction stream from the instruction cache; a priority designation means for designating a priority for each of the plurality of instruction streams; and an instruction fetch request issued simultaneously from two or more instruction cache means. An instruction fetch control means for arbitrating an instruction fetch request in accordance with the priority of the priority control circuit. 37. A plurality of functional units for executing an instruction, a plurality of instruction decoding units for extracting and decoding an instruction from an instruction cache, designating a functional unit to execute the instruction, and outputting an instruction issue request, A multi-thread processor having the same number of register sets as the decoding unit and simultaneously and independently executing a plurality of instruction streams of the same number as the instruction decoding unit, the instructions being settable for each instruction stream by the instructions in the instruction stream. Holding means for holding the priority of a flow, and control means for arbitrating according to the priority when two or more instruction flows simultaneously compete for a resource shared by a plurality of instruction flows, wherein the shared Contention for resources is caused by contention of instruction issue requests from two or more instruction decoding units for one functional unit, and instruction fetching from two or more instruction decoding units for the instruction cache. A multi-thread processor, which is one of a contention of a request and a contention of an access request from two or more functional units to one register set. 38. One of the functional units receives an instruction for increasing or decreasing the priority, and changes the priority of the instruction stream to which the instruction belongs among the priorities held in the holding means. The multi-thread processor according to claim 36, wherein: