JP2003241977A - Central processing unit and information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a central processing unit capable of efficiently executing two or more command strings. <P>SOLUTION: This central processing unit for executing two or more command strings in parallel comprises a resistor for holding a context showing the halfway state of the execution of one command string; a memory access part for storing the content of the register according to an access command to memory in the command string; a context storage part for storing a context saved from the resister, which is provided separately from an area where the memory access part stores the content of the resistor; and a control part for saving the context from the resistor to the context storage part and returning the context from the context storage part to the resistor. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit and an information processing device. In particular, the present invention relates to a central processing unit and an information processing device that execute a plurality of instruction sequences in parallel.

[0002]

2. Description of the Related Art Japanese Patent No. 2788605 discloses a computer system that receives instructions in a specific order and executes them in a plurality of execution units. Further, there has been proposed a central processing unit having a plurality of registers that can be directly accessed by an arithmetic unit to execute a plurality of instruction sequences (Introduction to Hyper-Th).
reading technology, Intel
Corporation, 2001).

[0003]

However, the computer system described above cannot execute a plurality of instruction sequences in parallel. Also,
In the central processing unit, the number of semiconductors and the like required for each instruction sequence to be executed increases. Therefore, an object of the present invention is to provide a central processing unit and an information processing apparatus that can solve the above problems. This object is achieved by a combination of features described in independent claims of the invention. The dependent claims define further advantageous specific examples of the present invention.

[0004]

That is, according to the first aspect of the present invention, there is provided a central processing unit for executing a plurality of instruction sequences in parallel, which is in the middle of executing one instruction sequence. Is provided separately from the register that holds the context indicating the, the memory access unit that stores the contents of the register in the memory according to the memory access instruction in the instruction sequence, and the memory area that the memory access unit stores the contents of the register. , A central processing unit comprising: a context storage unit that stores the context saved from the register; and a control unit that saves the context from the register to the context storage unit and restores the context from the context storage unit to the register An information processing apparatus including the apparatus and the central processing unit is provided. Note that the above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the claimed invention, and the features described in the embodiments Not all combinations are essential to the solution of the invention.

FIG. 1 is a functional block diagram of the information processing device 5. The information processing device 5 includes a central processing unit 10 and
And a memory 20. The central processing unit 10 includes an execution unit 100, a register 110, and a context storage unit 1.
20, a cache memory 130, a determination unit 140,
Control unit 150 and executable context storage unit 160
And a priority changing unit 180. Execution unit 100
Has a memory access unit 102 and an arithmetic unit 104.

The central processing unit 10 sequentially reads out the instruction sequence from the memory 20 and executes it. Central processing unit 1
0 holds in the register 110 the context that is in the middle of executing the instruction sequence. The central processing unit 10 saves the context held in the register 110 to the context storage unit 120 when the cause of saving occurs in the execution of the instruction sequence. Then, the context saved in advance in the executable context storage unit 160 is restored to the register 110, and the execution of the instruction sequence corresponding to the context is restarted. In this way, the information processing device 5
Also, the central processing unit 10 can efficiently execute a plurality of instruction sequences by performing a context switch, which is a process of saving a context and restoring another context, at high speed.

The memory 20 stores an instruction group and data used by the central processing unit 10 to execute a program.

The execution section 100 executes the instruction sequence corresponding to the context stored in the register 110. That is, the execution unit 100 sequentially acquires the instructions in the instruction sequence from the memory 20 based on the context and executes the instructions. The execution unit 100 acquires data from the memory 20 or stores data in the memory 20 as needed when executing an instruction. The execution unit 100 may access the cache memory 130 instead of the memory 20. And
The execution unit 100 responds to the execution of the instruction by register 110.
Will be updated from time to time. Furthermore, when a save cause that causes a context to be saved occurs during execution of an instruction sequence, the execution unit 100 provides information indicating that the save cause has occurred to the control unit 1.
Send to 50. In addition, when the instruction being executed is completed, the execution unit 100 sends information to the determination unit 140 that the execution of the instruction is completed.

The memory access unit 102 is an execution unit 100.
Among the instructions to be executed by, the instructions for reading and writing to the cache memory 130 and the memory 20 are exclusively executed. On the other hand, the arithmetic unit 104 includes the execution unit 100.
Execute certain types of instructions that are executed by. The arithmetic unit 104 may execute a branch instruction for exclusive use, an addition / subtraction for exclusive use, or a multiplication / division for exclusive use, for example. Further, a plurality of arithmetic units 104 may be provided, and each of them may exclusively execute different types of instructions. Further, when the arithmetic unit 104 is newly enabled from the unusable state, the arithmetic unit 104 changes the priority order to give priority to the execution of the context that requires the arithmetic unit 104 to resume execution. It is transmitted to the section 180.

The register 110 holds a context indicating a state in the middle of executing an instruction sequence. Register 1
10 holds, as a context, a program counter indicating a position on the memory 20 in which an instruction for starting execution is stored. Further, the register 110 may hold a value of a general-purpose register, a value of a control register, a stack pointer, or a frame pointer as a context. The register 110 may hold the execution state of an instruction sequence that operates a process or thread by holding these registers and pointers. Therefore, register 11
The context stored by 0 is updated at any time according to the execution of the execution unit 100. When the register 110 receives an instruction to save the context from the control unit 150, the register 110 sends the context to the context storage unit 120,
The executable context is received from the executable context storage unit 160. Here, when the context is sent to the context storage unit 120, the register 110 does not send the information on the storage location of the context, but sends the actual content of the context, that is, the execution state of the instruction string necessary for resuming the execution. The register 110 also receives the content of the actual context when receiving the executable context from the executable context storage unit 160.

The context storage unit 120 has a register 1
The context saved from 10 is stored together with the save cause. The context storage unit 120 includes the memory 20 in which the memory access unit 102 stores the contents of the register 110.
Also, it is provided separately from the cache memory 130. The context storage unit 120 may also store a plurality of contexts that can be identified with each other. Further, the context storage unit 120 may store the context in the memory 20 when the total amount of the contexts already stored and the total of the contexts instructed to be stored exceed the storage capacity of the context storage unit 120. Good.

The cache memory 130 includes an execution unit 100.
When the data to be written to the memory 20 is received from the memory 20, the data is temporarily stored. In addition, the cache memory 13
0 temporarily stores the data read from the memory 20 by the execution unit 100. The cache memory 130 writes back the temporarily stored data to the memory 20 as needed.

The judgment unit 140 receives information indicating that the execution of the instruction is completed from the execution unit 100. Then, based on the information indicating that the execution of the instruction is completed, it is determined whether the cause of saving the context stored in the context storage unit 120 has been resolved. When the determination unit 140 determines that the evacuation cause has been eliminated, it sends information indicating that the evacuation cause has been eliminated to the context storage unit 120. When the context storage unit 120 receives, from the determination unit 140, information indicating that the save cause has been resolved, the context storage unit 120 sends the context saved in the context storage unit 120 due to the save cause to the executable context storage unit 160 and is executable. State.

When the control unit 150 receives the information indicating that the save cause has occurred from the execution unit 100, it sends an instruction to save the context to the register 110. Then, when the register 110 completes saving the context, the control unit 150 sends an instruction to restore the context to the executable context storage unit 160. Here, the control unit 15
0 is to realize a fast context switch,
The context may be saved from the register 110 to the context storage unit 120 at a transfer rate faster than the transfer rate when the memory access unit 102 stores the data in the memory 20 and reads the data from the register 110. Further, the register 110 can access the memory 20 and the context storage unit 120 using different access paths. Therefore, the control unit 150
Is executed by the memory access unit 102 in parallel with the operation of reading data from the register 110 in order to store the data in the memory 20.
The context may be saved to 20.

The executable context storage unit 160 stores the executable context and the priority order for returning the executable context to the register 110. The executable context storage unit 160 includes the context storage unit 12
Receive executable context from 0. When the executable context storage unit 160 receives an instruction to restore the context from the control unit 150, the executable context storage unit 160 sends the executable context having the highest priority to the register 110. When the executable context storage unit 160 receives an instruction from the priority changing unit 180 to change the priority of the executable context, the executable context storage unit 160 changes the priority according to the instruction. Executable context storage unit 160
May store a predetermined priority of execution in each of the executable contexts as the priority. For example, the executable context storage unit 160 may store scheduling priorities of processes and threads predetermined by the operating system.
Further, the executable context storage unit 160 may store the order of receiving the executable contexts from the context storage unit 120 as a priority order. In this case, the executable context storage unit 160 stores the first-in first-out (F
It may be an IFO) type queue structure.

The priority changing unit 180 is composed of the arithmetic unit 1
When the instruction to prioritize the execution of a context is received from 04, the executable context storage unit 16 issues an instruction to change the priority order corresponding to the context.
Send to 0. Further, the priority order changing unit 180 may change the priority order corresponding to a context when there is a time constraint on the execution of the context. For example, when the instruction sequence corresponding to the context is managed by the real-time operating system, or when a part of the compressed moving image is dynamically expanded and reproduced, the priority order changing unit 180 determines the context. Change the priority of.

FIG. 2 shows a combination of save causes and save cause canceling factors. The “interrupt wait instruction” corresponds to “interrupt occurrence”. That is, the control unit 150 determines that a save cause has occurred and performs a context switch when the execution unit 100 starts executing an interrupt waiting instruction that is an instruction that suspends operation until an interrupt occurs. Then, when an interruption occurs in the central processing unit 10, the judgment unit 140 judges that the save cause has been resolved, and judges that the context can be executed. Also,
The "timer wait instruction" corresponds to "timer wait completion".
That is, the control unit 150 determines that a save cause has occurred and performs a context switch when the execution unit 100 starts executing a timer wait instruction that is an instruction for suspending operation for a predetermined period. Then, when the predetermined period has elapsed and the waiting for the timer is completed, the determination unit 140 determines that the save cause has been resolved, and determines that the context can be executed.

"Waiting for acquisition of exclusive right" corresponds to "acquisition of exclusive right". The exclusive right is a right temporarily given to the context in order to access an instruction or data that is restricted from being accessed in parallel at the same time. That is, when the execution unit 100 executes an instruction to acquire the exclusive right, but the exclusive right has already been acquired by another context, the control unit 150.
Determines that the save cause has occurred and performs a context switch. Then, when the context can acquire the exclusion right, the determination unit 140 determines that the context can be executed.

"Cache miss at the time of reading" corresponds to "completion of reading". In the "cache miss at the time of reading", the execution unit 100 has executed the read instruction to the memory 20, but the data to be read is the cache memory
This is a case where the data is read from the memory 20 that is slower than the cache memory 130 because it does not exist in the memory 30. When a cache miss occurs due to the read instruction, the control unit 150 determines that the save cause has occurred and performs a context switch. Then, the determination unit 140 determines that the context can be executed when the read command completes reading the data from the memory 20.

The "slow instruction" corresponds to the "slow instruction completion". A slow instruction requires more execution time than a predetermined standard to complete execution. This slow instruction is, for example,
This is an instruction to execute a complicated numerical operation. The process executed by the slow instruction may be, for example, multiplication / division, a trigonometric function operation, an input instruction to an input device, or an output instruction to an output device. Good. For example, when the execution unit 100 starts executing a slow instruction, the control unit 150 determines that a save cause has occurred and performs a context switch. Then, the determination unit 140
Determines that the context can be executed when the execution of the slow instruction is completed.

"The arithmetic unit cannot be used" corresponds to "the arithmetic unit can be used". When the execution unit 100 starts executing an instruction but the arithmetic unit dedicated to the arithmetic processing required for the instruction is unavailable, the control unit 150 determines that the save cause has occurred, and Switch. The determination unit 140 determines that the context can be executed when the operation unit necessary for restarting execution of the context becomes available.

The control section 150 may further perform a context switch when starting execution of a predetermined instruction other than that shown in FIG. In this case, the judgment unit 1
When the execution of the other predetermined instructions is completed, 40 determines that the cause of saving the context has been resolved. In addition, the control unit 150 may save the context of the instruction sequence being executed in the context storage unit 120 when the instruction sequence is executed for a predetermined period.
In this case, the determination unit 140 unconditionally determines that the cause of saving the context has been resolved.

FIG. 3 shows an example of the data structure of the context storage unit 120. The context storage unit 120 stores a context field and a save cause field associated with the context field. The context field is an ID for identifying the context
A field, a general-purpose register field used when the executing unit 100 executes an instruction, a control register field indicating a state of a result of executing the instruction by the executing unit 100, and a position in the memory 20 of an instruction to be executed next by the executing unit 100. Contains a program counter field that represents

For example, the context whose ID is 1 is
The values of the registers named R0, R1, and R2 are stored as the values of the general-purpose registers. For example, the value of R0 is 0x0010 (hexadecimal 10). ID is 1
Is the SP as the value of the control register.
It stores the values of the registers named (Stack Pointer) and CCR (Condition Code Register). SP represents the position of the data temporarily stored in the memory 20. The CCR is a register that stores the presence or absence of overflow of the numerical operation instruction executed immediately before by the execution unit 100 and the result of the comparison instruction as the logical sum of these.

The save cause field stores the cause of saving each context from the register 110 to the context storage unit 120. The context with ID 1 is "cache miss at memory read" as the cause of saving.
To store. In the example of the figure, when the context having the ID of 1 is held in the register 110 and executed, as a result of the occurrence of the “cache miss at memory read”, the context is saved in the context storage unit 120. Show.

As described above, the context storage unit 120
Stores, as the context, information necessary for resuming execution of the instruction sequence, and also stores the reason for saving the context. Therefore, the determination unit 140 can determine whether the save cause has been resolved by looking at the save cause field. Also, the determination unit 150
Execution can be resumed by finally returning the contents stored in the context field to the register 110 via the executable context storage unit 160.

FIG. 4 shows the executable context storage unit 16
An example of the data structure of 0 is shown. The executable context storage unit 160 has an executable context field and a priority field associated with the executable context field. Executable context storage unit 1
The data structure of the executable context stored by 60 is
It is the same as the data structure of the context shown in FIG.

The priority field stores the priority order in which the executable contexts are returned to the register 110 by the control unit 150. The priority of the executable context whose ID is 7 is 1. ID is 5,
The priority of executable contexts that are 6 and 8 is
They are 3, 4, and 2, respectively. Therefore, the control unit 15
When 0 causes a saving cause in the context stored in the register 110, and when the context is saved, the context having the priority of 1 and the ID of 7 is set in the register 11
Return to 0. In this way, the control unit 150 can appropriately select the executable context to be restored by referring to the priority order.

FIG. 5 shows a time chart when a plurality of instruction sequences are executed in parallel by saving and restoring the context. FIG. 5A shows an instruction sequence A, an instruction sequence B,
And the execution timing of each instruction sequence C are shown. On the other hand, FIG. 5B shows the timing when the central processing unit 10 actually executes these instruction sequences. In this figure, the vertical direction indicates the passage of time. Horizontal arrows in FIG. 5A indicate saving and restoring of the context. That is, the arrow from the instruction sequence A to the instruction sequence B indicates that the context of the instruction sequence A is saved and the context of the instruction sequence B is restored.

When the execution unit 100 starts executing the input instruction while executing the instruction sequence A, the control unit 150 saves the context corresponding to the instruction sequence A and restores the context corresponding to the instruction sequence B (S100). ). Next, the execution unit 100
When the execution of the interrupt waiting instruction is started during execution of the instruction sequence B, the control unit 150 saves the context corresponding to the instruction sequence B and restores the context corresponding to the instruction sequence C (S110). Next, the execution unit 100 completes the execution of the input instruction that has started execution (S120), and the executable context storage unit 160 stores the context corresponding to the instruction sequence A from the context storage unit 120 to the executable context storage unit. Move to 160. When the execution unit 100 starts executing a slow instruction while executing the instruction sequence C, the control unit 150
Saves the context corresponding to the instruction sequence C. Then, since the input instruction is completed in S120, the control unit 150 restores the context corresponding to the instruction sequence A (S130).

Next, when the central processing unit 10 receives an interrupt from the outside (S140), the executable context storage unit 160 transfers the context corresponding to the instruction string B from the context storage unit 120 to the executable context storage unit 160. Transfer. Next, when the execution unit 100 starts executing the timer wait instruction while executing the instruction sequence A, the control unit 150
Saves the context corresponding to the instruction sequence A. Then, since the interrupt waiting is completed in S140,
The control unit 150 restores the context corresponding to the instruction sequence B (S150). When the execution unit 100 completes the execution of the slow instruction (S160), the executable context storage unit 160 retrieves the context corresponding to the instruction sequence C from the context storage unit 120 to the executable context storage unit 16.
Move to 0. When the execution unit 100 executes an exclusive right acquisition wait instruction while the instruction string B is being executed and enters the exclusive right waiting state, the control unit 150 saves the context corresponding to the instruction string B. Then, since the late instruction is completed in S160, the control unit 150 restores the context corresponding to the instruction sequence C (S170).

When the execution unit 100 completes waiting for the timer (S180), the executable context storage unit 160
The context corresponding to the instruction sequence A is moved from the context storage unit 120 to the executable context storage unit 160.
When the execution unit 100 starts executing the interrupt waiting instruction while executing the instruction sequence C, the control unit 150 saves the context corresponding to the instruction sequence C. Since the timer waiting is completed in S180, the control unit 150 restores the context corresponding to the instruction sequence A (S190).
In this way, the central processing unit 10 can execute the instructions of other instruction sequences in parallel with the execution of the slow instructions. Therefore, the central processing unit 10 can use the execution unit 100 effectively and efficiently by executing a plurality of instruction sequences in parallel with the execution of a slow instruction as a cause of saving the context.

FIG. 6 shows the transition of the state of the context. When the context is activated (S5), it enters the execution state (S10). In the execution state, the execution unit 100
Executes the instruction sequence of the context. When the save cause occurs, the context is saved from the register 110 to the context storage unit 120 (S20), and the context is suspended until the save cause is resolved (S3).
0). When the cause of saving is eliminated, the context is acquired as an executable context from the context storage unit 120 to the executable context storage unit 160 (S4
0), the state becomes ready to wait for execution resumption (S50).
When the cause of saving is generated in another context, the executable context is restored from the executable context storage unit 160 to the register 110 (S60), and becomes the execution state again (S10).

As is apparent from the embodiments described above, the information processing device 5 and the central processing unit 10 according to the embodiments of the present invention perform context switching at high speed. Further, the information processing device 5 and the central processing unit 10 do not have any adverse effect on the execution of the instructions performed by the central processing unit 10 when performing the context switch. Therefore, the information processing device 5 and the central processing unit 10 are stored in the storage area dedicated to the context, that is, the context storage unit 1.
By providing 20, the context switching can be performed at high speed without interfering with the execution of the memory access instruction as compared with the case where the context is stored in the cache memory 130. In addition, a modified example in which the central processing unit 10 is provided with a plurality of registers 100 is possible with respect to the present embodiment. Also in this case, the execution unit 100 can execute the instruction sequence by using the other register independently of the operation in which one register performs the context switch, and the information processing device 5 and the central processing unit 10 are It is possible to efficiently execute a plurality of instruction sequences in parallel.

According to the embodiment described above, the central processing unit shown in each of the following items is realized. (Item 1) A central processing unit for executing a plurality of instruction sequences in parallel, comprising: a register for holding a context indicating a state during execution of one instruction sequence; and a memory in the instruction sequence. Storing the context saved from the register, which is provided separately from a memory access unit that stores the contents of the register in the memory according to the access instruction of 1. and a memory area that stores the contents of the register by the memory access unit. A central processing unit, comprising: a context storage unit that stores the context; and a control unit that saves the context from the register to the context storage unit and restores the context from the context storage unit to the register. (Item 2) The control unit saves the context from the register to the context storage unit at a transfer rate faster than a transfer rate when the memory access unit stores data in the memory. 1. The central processing unit according to 1. (Item 3) The central part of item 1, wherein the control unit saves the context from the register to the context storage unit in parallel with the operation of the memory access unit storing data in the memory. Processing unit. (Item 4) The central processing unit according to item 1, wherein the context storage unit stores a plurality of the contexts that are saved from the register and are distinguishable from each other. (Item 5) The central processing unit according to item 1, wherein the control unit saves and restores the context between the register and the context storage unit by moving the context.

(Item 6) The context storage section
A determination unit that further stores a save cause associated with the saved context, and determines whether the save cause of the context has been resolved, and the determination unit has determined that the save cause has been resolved. Item 2. The item further comprising: an executable context storage unit that selects and stores an executable context that is a context from the context storage unit, and the control unit restores the executable context to the register. Central processing unit. (Item 7) The executable context storage unit further stores a priority order for returning the executable context to the register, and the control unit returns the executable context to the register based on the priority order. The central processing unit according to item 6, characterized in that (Item 8) The central processing unit according to item 6, wherein the executable context storage unit stores, as the priority, the order in which the contexts are executable. (Item 9) The central processing unit according to item 8, further comprising a priority order changing unit that changes the priority order stored in the executable context storage unit. (Item 10) An operation unit that executes a specific type of instruction is further provided, and the priority order changing unit increases the priority order of the context when the operation unit necessary for restarting execution becomes available. 10. The central processing unit according to item 9, wherein (Item 11) An arithmetic unit for executing a specific type of instruction is further provided, and the control unit stores the context from the register when the arithmetic unit required for continuing execution of the instruction sequence is unavailable. 2. The central processing unit according to item 1, wherein the context of the instruction sequence is saved in a section.

(Item 12) The control unit saves the context of the instruction sequence being executed in the context storage unit when the instruction sequence is executed for a predetermined period. 1. The central processing unit according to 1. (Item 13) The control unit saves the context of the instruction sequence being executed from the register to the context storage unit when starting execution of a predetermined instruction. Central processing unit. (Item 14) The control unit, when starting execution of an instruction that requires more time than a predetermined standard until completion of execution, sets the context of the instruction sequence being executed from the register to the context storage unit. Item 13. The central processing unit according to item 13, wherein the central processing unit is evacuated. (Item 15) The control unit saves the context of the instruction sequence being executed to the context storage unit when the execution of an interrupt waiting instruction that suspends an operation until an interrupt occurs is started. The central processing unit according to item 13. (Item 16) The control unit saves the context of the instruction sequence being executed in the context storage unit when starting execution of a timer waiting instruction that suspends execution until a predetermined time elapses. Characteristic item 13
Central processing unit described.

(Item 17) The control unit saves the context of the instruction sequence being executed in the context storage unit when executing the exclusive processing instruction and entering a waiting state for acquisition of the exclusive right. The central processing unit according to item 1 characterized. (Item 18) The central processing unit executes the plurality of instruction sequences by using a cache that temporarily stores access to the memory, and the control unit caches by executing one of the instruction sequences. The central processing unit according to item 1, wherein the context of the instruction sequence being executed is saved in the context storage unit when a miss occurs. (Item 19) When the control unit saves the context from the register to the context storage unit,
Item 1. The method further comprises an execution unit that executes in parallel both an instruction whose execution is started before the saving and an instruction in a context different from the context that is restored to the register after the saving. Central processing unit. (Item 20) An information processing device comprising a central processing unit for executing a plurality of instruction sequences in parallel and a memory, wherein the memory supplies the instruction sequence and data to the central processing unit and performs the central processing. The central processing unit stores data generated by the processing unit, and the central processing unit holds a context indicating a state during execution of one instruction sequence, and an access instruction to the memory in the instruction sequence. A memory access unit for storing the content of the register in the memory in accordance with the above, and a memory area for storing the context saved from the register, which is provided separately from the memory area in which the memory access unit stores the content of the register. Section, saves the context from the register to the context storage section, and The information processing apparatus characterized by the preparative storage unit and a control unit for returning the context in the register.

Although the present invention has been described with reference to the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. Various changes or improvements can be added to the above-described embodiment. It is also possible to include such modifications or improvements in the technical scope of the present invention.
It is clear from the description of the claims.

[0041]

As is apparent from the above description, according to the present invention, there is provided a central processing unit for efficiently executing a plurality of instruction sequences.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an information processing device 5.

FIG. 2 is a diagram showing a combination of save causes and save cause canceling factors.

FIG. 3 is a diagram showing an example of a data structure of a context storage unit 120.

FIG. 4 is a diagram showing an example of a data structure of an executable context storage unit 160.

FIG. 5 is a time chart when a plurality of instruction sequences are executed in parallel by saving and restoring a context.

FIG. 6 is a diagram showing how the state of context changes.

[Explanation of symbols] 5 Information processing equipment 10 Central processing unit 20 memory 100 execution unit 102 memory access unit 104 arithmetic unit 110 registers 120 Context storage 130 cache memory 140 Judgment section 150 control unit 160 Executable context storage 180 Priority change section

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Nobuyuki Harada             1623 1423 Shimotsuruma, Yamato-shi, Kanagawa Japan             BM Co., Ltd. Daiwa Office F term (reference) 5B098 BA14 DD01 DD02 GA02 GA04                       GA05 GA08 GC02

Claims (20)

[Claims] 1. A central processing unit for executing a plurality of instruction sequences in parallel, comprising: a register for holding a context indicating a state during execution of one instruction sequence; and a memory in the instruction sequence. A memory access unit that stores the contents of the register in the memory according to an access instruction to the memory, and a memory area that is provided by the memory access unit separately from the memory region that stores the contents of the register. A central processing unit, comprising: a context storage unit that stores the context; and a control unit that saves the context from the register to the context storage unit and restores the context from the context storage unit to the register. 2. The control unit saves the context from the register to the context storage unit at a transfer rate faster than a transfer rate when the memory access unit stores data in the memory. The central processing unit according to claim 1. 3. The control unit saves the context from the register to the context storage unit in parallel with the operation of the memory access unit storing data in the memory. Central processing unit. 4. The central processing unit according to claim 1, wherein the context storage unit stores a plurality of the contexts saved from the register and identifiable with each other. 5. The central processing unit according to claim 1, wherein the control unit saves and restores the context between the register and the context storage unit by moving the context. . 6. The determination unit, wherein the context storage unit further stores a save cause associated with the saved context, and determines whether the save cause of the context has been resolved, and the determine unit. Further comprises an executable context storage unit for selecting and storing an executable context that is a context determined to have solved the saving cause from the context storage unit, wherein the control unit stores the executable context in the register. The central processing unit according to claim 1, wherein the central processing unit returns. 7. The executable context storage unit further stores a priority order for returning the executable context to the register, and the control unit returns the executable context to the register based on the priority order. 7. The central processing unit according to claim 6, wherein 8. The central processing unit according to claim 6, wherein the executable context storage unit stores, as the priority, the order in which the contexts are executable. 9. The central processing unit according to claim 8, further comprising a priority order changing unit that changes the priority order stored in the executable context storage unit. 10. An operation unit for executing a specific type of instruction is further provided, wherein the priority order changing unit sets the priority order of the context when the operation unit required for resuming execution becomes available. The central processing unit according to claim 9, wherein the central processing unit has a higher height. 11. An operation unit for executing a specific type of instruction is further provided, wherein the control unit controls the context from the register when the operation unit required to continue execution of the instruction sequence is unavailable. The central processing unit according to claim 1, wherein the context of the instruction sequence is saved in a storage unit. 12. The control unit saves the context of the instruction sequence being executed in the context storage unit when the instruction sequence is executed for a predetermined period. Central processing unit described. 13. The control unit saves the context of the instruction sequence being executed from the register to the context storage unit when starting execution of a predetermined instruction. 1. The central processing unit according to 1. 14. The control unit, when starting execution of an instruction that requires more time than a predetermined standard until completion of execution, the context of the instruction string being executed from the register to the context storage unit. 14. The central processing unit according to claim 13, wherein the central processing unit is saved. 15. The control unit saves, in the context storage unit, the context of the instruction sequence being executed when the execution of an interrupt waiting instruction that suspends an operation until an interrupt occurs is started. Claim 1
3. The central processing unit according to 3. 16. The control unit saves, in the context storage unit, the context of the instruction sequence being executed, when the execution of a timer waiting instruction that suspends execution until a predetermined time has elapsed is started. 14. The central processing unit according to claim 13. 17. The control unit saves the context of the instruction sequence being executed in the context storage unit when executing an exclusive processing instruction and entering a waiting state for acquiring an exclusive right. The central processing unit according to claim 1. 18. The central processing unit executes the plurality of instruction sequences by using a cache that temporarily stores access to the memory, and the control unit executes one of the instruction sequences. The central processing unit according to claim 1, wherein when a cache miss occurs, the context of the instruction sequence being executed is saved in the context storage unit. 19. When the control unit saves the context from the register to the context storage unit, an instruction started to be executed before the saving and the context to be restored to the register after the saving. The central processing unit according to claim 1, further comprising an execution unit that executes both instructions in different contexts in parallel. 20. An information processing apparatus comprising a central processing unit for executing a plurality of instruction sequences in parallel and a memory, wherein the memory supplies the instruction sequence and data to the central processing unit and the central processing unit. The central processing unit stores data generated by an arithmetic processing unit, and the central processing unit holds a context indicating a state in the middle of executing one instruction sequence, and an access to the memory in the instruction sequence. A memory access unit that stores the contents of the register in the memory according to an instruction, and a context that is provided separately from the memory area that stores the contents of the register and that stores the context saved from the register A storage unit, saving the context from the register to the context storage unit, and The information processing apparatus characterized by the emission text storage unit and a control unit for returning the context in the register.