JP5145936B2 - Multi-thread central processing unit and simultaneous multi-threading control method - Google Patents

Description

  The present invention generally relates to a central processing unit (CPU or MPU) (hereinafter simply referred to as a “processor”), and in particular, controls a multi-thread processor capable of processing a plurality of threads in parallel within the processor and simultaneous multi-threading. Related to the method.

  The present invention relates to a multi-thread processor suitable for improving the throughput of a processor while keeping the time constraint imposed on each thread, particularly in applications that perform real-time processing such as various robots, automobiles, plants, and home automation. .

  In a real-time system that performs real-time processing, the scheduler of the operating system (OS) gives priority to each thread according to the execution period and time constraint of each thread in order to keep the time constraint of each thread. Then, based on the assigned priority, execution is performed by assigning computation resources in order from the thread with the highest priority. Here, the “thread” is a program execution unit, and usually one application program is composed of a number of threads.

  FIG. 1 shows an example in which real-time processing is performed using a conventional single thread processor that executes only one thread at a time. In this example, assume that thread # 0 has the highest priority and thread # 7 has the lowest priority. Also, the release time indicates the time at which the thread can be executed, and the time limit indicates the time constraint of the thread (the final time limit at which the execution is to be completed).

  In the example shown in FIG. 1, first, thread # 1, thread # 2, and thread # 3 become executable. Among these executable threads # 1, # 2, and # 3, the processor resource is given to the thread # 1 having the highest priority, and the thread # 1 is executed. When the execution of the thread # 1 is completed, a context switch occurs between the memory outside the processor and the processor in order to execute the thread # 2 having the next highest priority. The context switch saves the context of the currently executing thread # 1 (that is, various resources such as the program counter, register file, and status register in the processor necessary for executing the thread) to memory outside the processor. Then, the context of thread # 2 to be executed next is returned from the memory to the processor. Thereafter, the processor starts executing thread # 2. When execution of the thread # 2 is completed, a context switch occurs, the context of the thread # 2 is saved in the memory, and after the context of the thread # 3 returns from the memory to the processor, the execution of the thread # 3 is started. If thread # 0 with higher priority becomes executable during execution of thread # 3, execution of thread # 3 is interrupted, a context switch occurs, and the context of thread # 3 is saved in memory, and thread # 0 Is returned to the processor, and thread # 0 is executed first. When execution of thread # 0 is completed, the context of thread # 0 is saved in memory by the context switch, and the context of thread # 3 returns to the processor, so execution of suspended thread # 3 resumes .

  In this way, in the processing using the conventional single thread processor, when the execution of the thread with a higher priority is completed or when a thread with a higher priority than the currently executing thread becomes executable, A context switch occurs. The OS must save the context of the currently executing thread in the memory and return the context of the thread to be executed next to the processor. In a real-time system, this context switch is a large overhead. On the other hand, as a technique for reducing the overhead of context switching, there is a multi-thread processor that processes a plurality of threads in parallel in a processor. The multi-thread processor holds multiple thread contexts in the processor and executes each thread while switching them with the hardware in the processor, so it is possible to execute multiple threads without context switching (For example, see Patent Document 1).

  In addition, as another control technology for improving the throughput of a multi-thread processor suitable for real-time processing, a technology for changing the execution order of instructions of multiple threads at the reservation station according to the priority assigned to each thread. Is known (see, for example, Patent Document 2).

Japanese Patent Laid-Open No. 2004-220070 JP 2004-295195 A

  In a multi-thread processor, when a plurality of threads are executed in parallel, contention between threads may occur in computation resources such as cache access and computing units. When the competition of computing resources occurs, the execution time of a single thread increases. If the combination of a plurality of threads executed in parallel within the processor is different, the execution time of each thread is different because the manner and frequency of computation resource competition differ. As a result, the prediction accuracy of the execution time of each thread decreases. In particular, in a real-time system, each thread has a time constraint. Therefore, the scheduler schedules thread execution so that execution of each thread can be completed within the time constraint. However, in a system using a multi-thread processor, the time prediction accuracy is low for the above reason, so that it is difficult to perform scheduling that keeps the thread time constraint.

  Accordingly, an object of the present invention is to suppress fluctuations in thread execution time that cause a decrease in time prediction accuracy in a multithread processor.

  Another object of the present invention is to improve the throughput of a multi-thread processor.

  According to the present invention, the multi-thread central processing unit that processes a plurality of threads in parallel stores the priority of each thread, and uses the priority of each thread to process the processing order of the plurality of threads or Control the frequency. In addition, the multi-thread central processing unit stores the instruction execution target of each thread, monitors the number of execution instructions per time of each thread, and performs feedback control operation using the number of execution instructions and the target value. Control the order or frequency of processing of instructions in multiple threads.

  According to this multi-thread central processing unit, by controlling the instruction processing order / frequency using the priority given to each thread, the competition between threads of various resources necessary for instruction processing is reduced. Will be arbitrated accordingly. In addition, feedback control based on monitoring the instruction execution status of each thread (for example, the number of instructions executed per predetermined period, IPC or CPI) reduces the influence of other threads being processed at the same time. Variations in execution time are suppressed. This leads to an improvement in the prediction accuracy of the execution time of each thread, and it is possible to improve the throughput of the entire processor while keeping the time constraint of real-time processing.

  In a preferred embodiment, the allocated amount of a predetermined resource (for example, an instruction buffer, a reservation station, or a reorder buffer) in the multi-thread central processing unit to a plurality of threads is monitored, and the resources for these monitored threads are monitored. The order or frequency of instruction fetch, issue, or execution of the threads is controlled so that the allocated amount follows the priority of the threads. For example, when the resource allocation amount of one or more threads having a lower priority exceeds the resource allocation amount of one or more threads having a higher priority, at least one of the threads having the higher priority Instruction fetch, issue or execution of one thread is facilitated, or instruction fetch, issue or execution of a thread having its lower priority is suppressed or prohibited.

  More specifically, the instruction buffer occupancy of each thread is monitored, and the instruction buffer occupancy by one or more threads having higher priority is that of one or more threads having lower priority. Controls to facilitate fetching instructions for at least one thread in a thread with its higher priority, or to suppress fetching instructions for a thread with its lower priority when . Also, when the instruction buffer occupancy by one of the threads is small and the predetermined lower limit condition is not satisfied, control is made so as to facilitate fetching of the instruction of the thread or cancel suppression of fetching of the instruction of the thread. May be. Furthermore, when the reservation station occupancy of each thread is monitored, the reservation station occupancy by one or more threads having a higher priority is less than that of one or more threads having a lower priority. It is also possible to perform control so as to promote the issuance of instructions of at least one thread in the thread having the higher priority, or to suppress fetching of instructions of the thread having the lower priority. In addition, among multiple threads with the same priority, the instruction fetch right is given to the thread with the smaller instruction buffer occupancy, or the instruction is given priority to the thread with the smaller reservation station occupancy. Control can be performed to give issuance rights.

  In this way, in the preferred embodiment, control is performed so that instructions of higher priority threads are processed before instructions of lower priority threads. However, under certain circumstances in which higher priority threads waste processing resources or use them inefficiently (eg, cache misses, branch prediction misses or high likelihood, or reservations) In the case of station occupation, etc., control may be performed so that instructions of lower priority threads are processed before instructions of higher priority threads.

  In the preferred embodiment, the instruction execution state (for example, IPC) of each thread is brought close to the instruction execution target (for example, IPC target value) set for each thread, particularly in the instruction fetch or issue stage. Adjustments are made to the control conditions of the control action according to the priority. For example, when the instruction execution status of a thread does not satisfy the above target, the frequency of fetching or issuing the instruction of the thread is increased, or the instruction of an instruction of another thread having a lower priority than the thread is fetched. Or the frequency of issuing is suppressed. In order to adjust the control operation by priority, an operation value for each thread called “inflation value” incorporated in the control condition of control by priority (in the preferred embodiment, called “inflation value”) is increased or decreased. , Thereby facilitating or suppressing the fetching or issuing of instructions for each thread. However, even if the operation value is changed, if the instruction execution state does not improve according to the change, the operation value is restored.

  According to the present invention, in a multi-thread processor, it is possible to reduce the variation in the execution time or IPC of each thread. This facilitates better scheduling for real-time processing, which in turn can contribute to improving the throughput of the entire processor.

The time chart figure which shows the example of the real-time process by the conventional single thread processor. The block diagram which shows the structure of the principal part of one Embodiment of the multithread processor according to this invention. The block diagram which shows the structure for controlling IPC of a thread | sled. The block diagram which shows the operation | movement of the state transition of a control function for controlling IPC of a thread | sled, and inflation value increase / decrease. The time chart which shows the example at the time of performing real-time processing using the multithread processor which performs arbitration by priority. The time chart which shows the example of the real-time process by the multithread processor which performs IPC control with arbitration by priority. The time chart which shows the example of the real-time processing by the SMT processor which has four pipelines and performs IPC control with arbitration by priority.

Explanation of symbols

10 multi-thread processor 12 issue unit 14 cache unit 16 execution unit 20 thread control unit 24 fetch thread selector 32 instruction issue selector 36 register file 38 context cache 40 reorder buffer 44 instruction cache 48 instruction wait buffer 52 data read / write buffer 58 data wait Buffer 60 Reservation station 100 Pipeline processing mechanism 102 Number of executed instructions monitoring unit 104 Comparison unit 106 Control function unit

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

  FIG. 2 shows a block configuration of a main part of the multithread processor according to the embodiment of the present invention.

  A multi-thread processor (hereinafter simply referred to as “processor”) 10 shown in FIG. 2 employs an SMT (Simultaneous Multi Threading) architecture, and can process a plurality of (for example, a maximum of eight) threads simultaneously. At the same time, the context of more threads (for example, up to 40) can be held internally, and a large number of threads can be processed without context switching with external memory. As shown, the processor 10 includes an issue unit 12, a cache unit 14, and an execution unit 16. The basic functions of these units 12, 14 and 16 are as follows. The cache unit 14 accesses an external memory (not shown), fetches and caches instructions from the external memory, loads and caches data (operands) from the external memory, and stores data to be stored. Cache and store to external memory. The execution unit 16 has operation resources such as a memory access unit and various arithmetic units, executes the instruction issued from the issuing unit 12 in an out-of-order manner, and writes back the execution result of the instruction to the issuing unit 12. The issue unit 12 internally holds the contexts of the plurality of threads so that the plurality of threads can be processed in parallel, fetches the instructions of the plurality of threads from the cache unit 14, decodes the instructions, The operation instruction of the decoding result of the instruction is issued to the execution unit 16, the instruction execution result written back from the execution unit 16 is received, and the instruction is committed.

  In addition to the basic functions described above, the processor 10 has two notable functions according to the principles of the present invention as follows. One is an arbitration function based on priority. That is, it is a function that mediates resource competition among a plurality of threads based on priorities assigned in advance to the plurality of threads. Another one is an IPC control function for keeping a desired value constant as much as possible while suppressing variations in IPC (Instructions per Clock Cycle) of each thread. That is, it monitors the number of execution instructions per fixed time for each thread, and the instructions of the plurality of threads so that the number of execution instructions of each thread matches the target value of the number of execution instructions assigned to each thread as much as possible. It is a function to adjust the execution frequency. These two functions are related to each other and work simultaneously. Here, the priority of each thread and the target number of instruction executions are set for the processor 10 by, for example, an OS scheduler or programmer.

  In order to realize the arbitration function by priority, the issuing unit 12 stores in advance the priority assigned in advance to each thread. The priority is also notified to the cache unit 14 and the execution unit 16. The issue unit 12, the cache unit 14, and the execution unit 16 individually determine the amount of resources for instruction fetch, issue, execution, and commit provided to each of the plurality of threads based on the priority of the plurality of threads. Control. For this purpose, not only does the execution of the higher priority thread not be hindered by the lower priority thread, but also the lower priority thread A control method to be executed is implemented.

  Furthermore, in order to implement the IPC control function, the issuing unit 12 stores in advance a target value of the number of execution instructions allocated in advance to each thread. The issuing unit 12 counts the actual number of executed instructions (number of committed instructions) for each thread at a fixed repetition period, and compares it with a target value stored in advance. If the actual number of instructions executed by a thread does not reach the target value, the resource contention arbitration control based on the priority is corrected by feedback control so that the frequency of fetching or issuing the instruction of the thread is increased. For example, in order to increase the frequency of fetching or issuing an instruction of a thread, fetching or issuing a thread having a lower priority than that thread is suppressed. Conversely, for example, in order to reduce the frequency of fetching or issuing instructions of a thread, fetching or issuing of a thread having a lower priority than that thread is facilitated.

  Hereinafter, a more specific configuration and function of the processor 10, particularly a part related to the arbitration function by priority and the IPC control function will be described with reference to FIG. 2.

  The issue unit 12 includes a thread control unit 20, a PC (program counter) control unit 22 corresponding to the maximum number of threads that can be processed simultaneously (for example, eight), a fetch thread selector 24, an instruction decoder 26, an instruction analyzer 28, and an instruction buffer 30. , An instruction issue selector 32, a rename register 34, a register file 36 corresponding to the maximum number of threads that can be processed simultaneously (for example, eight), and a reorder buffer 40. The cache unit 14 includes an instruction MMU (memory management unit) 42, an instruction cache 44, an instruction victim cache 46, an instruction wait buffer 48, a data MMU 50, a data read / write buffer 52, a data cache 54, a data victim buffer 56, and a data wait buffer. 58. The execution unit 16 has a predetermined plurality (for example, five) of reservation stations 60 and various computing resources 62-80. The computing resource 62-80 includes a memory access unit 62, a plurality of branch units 64, an integer divider 66, a plurality of integer computing units 68, an FP (floating point) divider 70, a plurality of FP computing units 72, and a 64-bit integer. There are an arithmetic unit 74, a vector integer arithmetic unit 78, a vector FP arithmetic unit 80, and the like. Since it is unlikely that threads that are processed simultaneously will use the same computing resource at the same time, the number of reservation stations and the number of each computing resource are less than the maximum number of threads that can be processed simultaneously (for example, eight). Avoid unnecessary redundancy.

  In the following, the function and operation of each part will be described along the flow of processing instructions.

  The thread control unit 22 is a unit that functions as a core for controlling parallel processing of a plurality of threads. The thread control unit 22 stores and holds the priority of the plurality of threads therein, and the priority is assigned to the entire processor 10. To distribute. Here, the number of priority threads that can be stored in the thread control unit 22 is preferably equal to or greater than the maximum number (for example, 40) of context threads that the processor 10 can internally hold. The plurality of PC control units 22 are respectively assigned to a plurality of threads that can be simultaneously processed in the processor 10, and give the value of the program counter from each thread to the fetch thread selector 24. Contention between multiple threads first occurs in instruction cache access. Therefore, the fetch thread selector 24 selects one thread from the threads requesting the instruction cache access using the priority of each thread, and sets the program counter of the selected thread to the instruction MMU (memory management). Unit) 42. Here, the fetch thread selector 24 selects, in principle, a thread having the highest priority among threads requesting instruction cache access. However, the thread with the highest priority is not always selected, and the thread with the lower priority is selected instead of the thread with the highest priority under certain circumstances where the execution of the thread with the highest priority is not under pressure. Sometimes it is done.

  The instruction MMU 42 accesses the instruction cache 44 and passes the instruction of the selected thread from the instruction cache 44 to the instruction decoder 26. Here, when an instruction cache miss occurs, it is necessary to read the cache line by accessing an external memory (not shown). Since memory access has higher latency than cache access, if a cache miss continues, a plurality of memory access requests are waited in the instruction wait buffer 48. In this case, based on the priority of each thread, the instruction wait buffer 48 basically processes the memory access request of the highest priority thread first. Thereby, priority is given to the execution of a thread having a higher priority. However, memory access requests of higher priority threads are not always given priority, and under certain circumstances where the execution of higher priority threads is not under pressure, the memory of lower priority threads is higher than higher priority threads. In some cases, the access request is processed first.

  A plurality of (for example, eight, which is one line of the cache) instructions are simultaneously sent from the instruction cache 44 to the instruction decoder 26. The instruction decoder 26 simultaneously decodes a plurality of instructions fetched from the instruction cache 44 at the same time, and the decoding results of these instructions (also referred to as “instructions” for convenience in the following description) are simultaneously stored in the instruction buffer 40. At that time, it is necessary for the instruction analyzer 28 to determine the instruction type of multiple instructions decoded simultaneously (which thread's instruction, which computing resource is used, and whether there is a dependency between instructions, etc.) Information regarding threads, opcodes, operands, etc.) and giving the instruction type to the instruction issue selector 32. The instruction issue selector 32 checks the availability of the reorder buffer 40, the rename register 34, and the reservation station 60, and the dependency relationship between instructions in the instruction buffer 30, and based on the result, from the instruction buffer 30 to the reservation station 60. Select an instruction that can be issued. A predetermined number of instructions (for example, four less than the maximum number of threads that can be processed simultaneously) can be issued from the instruction buffer 30 at the same time. At that time, when there are a plurality of instructions that can be issued in the instruction buffer 30 (especially, more than the predetermined number (four)), the instruction issue selector 32 is in principle higher order according to the priority of each thread. It is issued first from the instruction of the thread with the priority. However, as will be described later, under a predetermined situation in which execution of a higher priority thread is not squeezed, an instruction of a lower priority thread than a higher priority thread may be issued first.

  The various arithmetic units such as the integer arithmetic unit 68 and the FP arithmetic unit 72 connected to each reservation station 60 also compete with each other. Thus, each reservation station 60 also performs contention arbitration using the priority of each thread. Each reservation station 60 sends the instructions waiting there to the arithmetic unit out-of-order in order from the instruction having the operands necessary for the operation. At that time, when a plurality of instructions can be operated simultaneously, each reservation station 60, in principle, sends the instruction of the thread with the higher priority first to the operation unit based on the priority of each thread. Priority is given to thread execution. However, the instruction of the thread with the higher priority is not always given priority, and the instruction of the thread with the lower priority is substituted for the thread with the higher priority in a predetermined situation where the execution of the thread with the higher priority is not under pressure. May be sent to the arithmetic unit first.

  Contention also occurs in data cache access. Therefore, the data read / write buffer 52 gives priority to the execution of the higher priority thread by executing first the data cache access of the higher priority thread based on the priority of each thread. However, cache access with a higher priority is not always given priority. Under certain circumstances where the execution of higher priority threads is not under pressure, cache access with lower priority threads is substituted for higher priority threads. May be processed first. When a data cache miss occurs, it is necessary to access an external memory (not shown) and read the cache line. However, as in the case of the instruction cache, the data wait buffer 58 is based on the priority of each thread. Thus, in principle, the execution of the thread with the higher priority is given priority by processing the memory access request of the thread with the higher priority first. However, even in this case, memory access of a higher priority thread is not always given priority, and in a predetermined situation where execution of a higher priority thread is not under pressure, a lower priority is used instead of a higher priority thread. In some cases, the memory access of the thread is processed first.

  The reorder buffer 40 temporarily holds the execution result of the instruction executed out of order, and commits the instruction in order. A predetermined number of instructions (for example, four less than the maximum number of threads that can be processed simultaneously) can be committed simultaneously. At that time, if a plurality of (especially, more than the predetermined number (four)) instructions can be committed, the reorder buffer 40 generally commits the instructions of the higher priority thread first. However, in this case as well, a thread with a higher priority is not always given priority, and a thread with a lower priority is replaced with a thread with a lower priority in a predetermined situation where execution of a thread with a higher priority is not under pressure. Sometimes committed first.

  There are as many register files 36 as the maximum number of threads that can be processed simultaneously (for example, eight), and each register file 36 is assigned to a plurality of threads that are processed simultaneously. Each register file 36 stores the context of each thread. The context cache 38 can store contexts for a larger number of threads (for example, 32 threads). The context of any thread in the context cache 38 and the context in any register file 36 can be quickly exchanged. Therefore, in this processor 10, the number of register files 36 (for example, eight) threads can be processed without performing context switching, and the number of threads (for example, 32) supported by the context cache 38 can be processed at high speed. A switch can be performed.

  As described above, in units related to the fetch, issue, execution, and commit stages of instructions in the processor 10, instructions for arbitrating resource contention among threads using the priority of a plurality of threads. The processing order or the processing frequency is controlled. As a result, the higher priority thread is preferentially executed, and the lower priority thread is also executed without degrading the performance of the upper priority thread.

  In addition to the above control, in order to facilitate the prediction of the execution time of each thread, the processor 10 performs IPC control for suppressing fluctuation of the IPC of each thread and maintaining it as close to a desired value as possible. Done. The control of the processing order or processing frequency of instructions using the thread priority described above is adjusted or corrected by this IPC control. In this embodiment, the thread control unit 20, the fetch thread selector 24, and the instruction issue selector 32 are directly involved in this IPC control. The thread control unit 20 stores and holds a target value of the number of execution instructions allocated in advance to each of a plurality of threads. Here, the number of threads of the target value that can be stored in the thread control unit 22 is preferably equal to or greater than the maximum number (for example, 40) of context threads that the processor 10 can internally hold. The thread control unit 20 counts the actual number of execution instructions (IPC x number of clock cycles in one monitoring period) per thread for every fixed monitoring period (for example, every several hundred clock cycles), and the counted execution instructions The number is compared with the stored target value, and the frequency of instruction fetch and instruction issue of each thread by the fetch thread selector 24 and the instruction issue selector 32 is controlled by a feedback control method based on the comparison result. .

  FIG. 3 shows a configuration of a mechanism for performing this IPC control.

  In FIG. 3, block 100 shows a mechanism for pipeline processing of the above-described multi-thread instructions in processor 10, where, as described above, using the priority of each thread, Resource contention arbitration control is performed. The IPC control mechanism includes an execution instruction number monitoring unit 102, a comparison unit 104, and a control function unit 106, and is incorporated in the thread control unit 20 shown in FIG.

  The execution instruction number monitoring unit 102 counts the number of execution instructions of each of a plurality of threads being processed in parallel for each fixed monitoring period. The comparison unit 104 compares the counted actual instruction execution count with a target value stored in advance for each thread. As will be described later, in this embodiment, the comparison unit 104 performs not only the comparison between the actual instruction execution number and the target value, but also the following comparison because of the control for performing state transition as described later. . That is, for each thread, the number of instructions (the number of carry-over instructions) in which the actual number of effective instructions should have been executed in the previous monitoring cycle is calculated, and the number of carry-over instructions and the target value are calculated. It is added to calculate the carry-over residual value (that is, the number of instructions to be executed in the current monitoring period), and the carry-over residual value is compared with the actual instruction execution number this time.

  The control function unit 106 performs a predetermined feedback control operation based on the comparison result by the comparison unit 104, determines an operation value for adjusting the frequency of instruction fetch and instruction issuance of each thread, and the operation value Is applied to the pipeline processing mechanism 100. Here, although PD control, PID control, or the like can be used for the feedback control operation, in this embodiment, the operation value is controlled according to the state transition as described later with reference to FIG. Control action is adopted. As the operation value, a parameter called an inflation value prepared for each thread as described later with reference to FIG. 4 is adopted.

  The inflation value for each thread output from the control function unit 106 is a unit for controlling the frequency of instruction fetch and instruction issuance in the pipeline processing mechanism 100, that is, in this embodiment, the fetch thread selector 24 shown in FIG. And the instruction issue selector 32. The inflation value of each thread is gradually increased or decreased within a predetermined variable range by the control function unit 106 according to the comparison result between the number of instructions executed by each thread, the target value, and the carry-over residual value. As the inflation value increases, the frequency of instruction fetch and instruction issuance increases, and when the inflation value is low, the fetch thread selector 24 and the instruction issuance selector 32 reduce the frequency of instruction fetch and instruction issuance according to the inflation value. Adjust control actions using priorities. For example, when the inflation value of a thread increases, the fetch thread selector 24 and the instruction issue selector 32 suppress the frequency of instruction fetch and instruction issue of a thread having a lower priority than that thread, respectively. The frequency of instruction fetch and instruction issue of the thread is increased. Conversely, for example, when the inflation value of a thread decreases, the fetch thread selector 24 and the instruction issue selector 32 promote the frequency of instruction fetch and instruction issue of a thread having a lower priority than that thread, respectively. As a result, the frequency of instruction fetch and instruction issuance of the thread is reduced.

  The IPC control mechanism having the above-described configuration monitors the IPC of each thread with a certain monitoring period PERIOD. The programmer writes the value of “PERIOD × ipc” in the IPC setting register of each thread as the setting value of the number of execution instructions of each thread, with the IPC target value of each thread as ipc. When a setting value “PERIOD × ipc” is not satisfied for any thread, the IPC control mechanism increases the inflation value of the thread.

  The IPC control mechanism holds the following values for each thread and controls the inflation value.

ipc_target: Setting value for the number of instructions executed, that is, PERIOD x ipc;
com_cnt: Number of instructions executed this term, that is, the number of instructions actually executed in the current monitoring period PERIOD;
prev_com_cnt: Number of instructions executed in the previous period, that is, the number of instructions actually executed in the previous monitoring period PERIOD;
carry_over: Number of carry-over instructions, that is, the number of instructions to be executed in the current monitoring period PERIOD, and if this value is not zero at the end of the current monitoring period PERIOD, this value is carried over to the next monitoring period PERIOD ;
stat_cnt: The number of monitoring periods PERIOD remaining in the current state (each state shown in FIG. 4 described later).

Here, the value of the carry-over instruction carry_over is updated every monitoring period PERIOD.
carry_over = carry_over + ipc_target-com_cnt
It is decided as follows. That is, if only a smaller number of instructions can be executed than the number specified in the carry-over instruction carry_over in a certain monitoring period PERIOD, the insufficient instruction number is carried over to the next monitoring period PERIOD as the carry-over instruction number carry_over. Carry_over in the monitoring period PERIOD increases. Conversely, when more instructions are executed in a certain monitoring period PERIOD than the number specified in the carry-over instruction carry_over, the carry-over instruction number carry_over decreases in the next monitoring period PERIOD. If the number of instructions executed com_cnt in the current period exceeds the number of carry-over instructions carry_over in a certain monitoring period PERIOD, instruction fetch of the corresponding thread is not performed in the monitoring period PERIOD.

  The control function unit 106 of the IPC control mechanism performs the state transition shown in FIG. 4 for each monitoring period PERIOD using the above-described values, and controls the inflation value. The details are as follows.

  FIG. 4 shows the state transition of the control function unit 106 and the inflation value increase / decrease operation.

  The control function unit 106 performs the operation shown in FIG. 4 in parallel for each of the plurality of threads.

  In FIG. 4, “normal” 110 is a state in which the current number of executed instructions com_cnt satisfies the set value ipc_target and the number of carry-over instructions carry_over, in other words, the performance of the thread is guaranteed. It is. If the status was “Normal” 110 until now, if the number of instructions executed in the current monitoring period PERIOD could not satisfy both of the set value ipc_target, the status transited to “IPC Failing” 112, while it was carried forward If only the instruction number carry_over cannot be satisfied, the state transitions to “request failing” 114. Further, when “normal” 110 continues over a certain number of monitoring cycles, the inflation value is decreased, and as a result, the frequency of instruction fetch and instruction issuance of the thread is suppressed.

  “Request failing” 114 is a state in which the current number of executed instructions com_cnt satisfies the set value ipc_target but does not satisfy the number of carry-over instructions carry_over. In other words, the IPC target value is satisfied in the short term, but the IPC target value is not satisfied in the previous monitoring period PERIOD, so that the insufficient instruction must be executed extra. If this state lasts for a certain number of times REQ_FAIL_THRESH or more, the inflation value is increased and the state transitions to “resource up check” 116. On the other hand, in “request failing” 114, when the current number of executed instructions satisfies the carry-over residual value, the state transitions to “normal” 110.

  “IPC failing” 112 is a state in which the current number of executed instructions com_cnt does not satisfy both the carry-over instruction number carry_over and the set value ipc_target. In other words, the IPC target value is not met in the short and long term. If this state continues for a certain number of times IPC_FAIL_THRESH or longer, the inflation value is increased and the state transitions to “resource up check” 116. On the other hand, in “IPC failing” 112, when both the carry-over instruction number carry_over and the set value ipc_target are satisfied, the state transitions to “normal” 110.

  The “resource up check” 116 is a state for checking whether or not there has been an improvement in IPC commensurate with the increase in the inflation value after the inflation value has been increased. In this state, if the increment of the current execution instruction number com_cnt compared to the previous execution instruction number prev_com_cnt is greater than or equal to the preset threshold EFFICIENT_THRESH, but the carry-over instruction number carry_over is not yet satisfied, the inflation value further increases. Is done. On the other hand, when the number of carry-over instructions carry_over is satisfied, the state transitions to “normal” 110. Further, in the “resource up check” 116, when the increment is less than the threshold value EFFICIENT_THRESH, the inflation value is decreased and the state transitions to “resource down” 118.

  “Resource down” 118 is a state corresponding to a case where an improvement in IPC commensurate with an increase in inflation value is not recognized. When entering this state, the inflation value is decreased and the state transitions to “resource down check” 120.

  The “resource down check” 120 is a state for checking whether or not the IPC has significantly decreased after the inflation value is decreased. In this state, when the number of execution instructions com_cnt in the current period falls below a preset threshold value compared to the number of execution instructions prev_com_cnt in the previous period, the inflation value is returned to the value one cycle before. Otherwise, the inflation value is maintained at the current value. The state transitions to “normal” 110, “IPC failing” 112, or “request failing” 114. Whether the state transitions to “normal” 110, “IPC failing” 112, or “request failing” 114 is determined by a comparison result between the current execution instruction number com_cnt, the set value ipc_target, and the carry-over instruction number carry_over.

  As described above, if the state where the IPC does not satisfy the desired value continues for each thread, the inflation value is increased. However, even if the inflation value is increased, if the IPC improvement corresponding to the increase cannot be obtained, the inflation value is restored. The reason is to cope with the fact that the maximum performance of the program changes with time. In other words, since the IPC of the program changes with time, the IPC target value may not be satisfied in a certain monitoring period PERIOD. In such a case, increasing the inflation value is meaningless and only the execution of other threads is hindered. Therefore, if an increase in the inflation value does not improve the IPC corresponding to the increase, it can be expected to recover in the future monitoring period PERIOD, so the increase in the inflation value is cancelled. The number of insufficient instructions is added to the carry-over instruction number carry_over. By increasing the inflation value when the IPC of the program becomes easier to improve in the future, the number of insufficient instructions will be eliminated.

  With the above IPC control, the performance of a specific thread can be controlled without significantly impeding the execution of other threads, even in a program whose performance varies greatly. Since the IPC of each thread is controlled to be close to a desired value, the accuracy of predicting the execution time of each thread is improved. As a result, in real-time processing, it is easy to schedule such that time constraints can be observed even when a plurality of threads are executed in parallel.

  FIG. 5 shows an example in which real-time processing is performed using a multi-thread processor that performs arbitration based on the above-described priority. In the example of FIG. 5, for convenience of explanation, a single pipeline multi-thread processor having only one thread that can be simultaneously processed is used instead of the SMT processor that can simultaneously process a plurality of threads such as the processor 10 described above. In this case, an ideal execution (no cache miss or branch prediction miss occurs) is assumed.

  In the example shown in FIG. 5, it is assumed that thread # 0 has the highest priority and thread # 7 has the lowest priority. In this example, first, thread # 1, thread # 2, and thread # 3 become executable. Here, in a conventional multi-thread processor that does not perform resource arbitration according to priority, thread # 1, thread # 2, and thread # 3 are executed in parallel. On the other hand, in a multi-thread processor that arbitrates resources according to priority, in principle, execution of thread # 1 with the highest priority is given priority due to arbitration of computing resources according to priority. Therefore, thread # 1 is executed first. When the execution of the thread # 1 is completed, the thread # 2 having the next highest priority is preferentially executed by arbitration based on the priority. At this time, since the context of the thread # 2 is held in the processor, the thread # 2 is immediately executed without performing a context switch. Even when thread # 0 having a higher priority becomes executable during execution of thread # 4, execution of thread # 0 is given priority due to arbitration of computing resources by priority. Also at this time, thread # 0 is immediately executed without performing a context switch. When the execution of the thread # 0 is completed, a computing resource is allocated to the thread # 4, and the thread # 4 immediately resumes execution.

  In general, even when one thread is stalled due to a cache miss or the like, a multi-thread processor can maintain a high throughput of the entire processor by executing another thread. With respect to this aspect, in the multi-thread processor according to the present invention, when a high-priority thread stalls, arbitration by priority can be performed so that the next highest-priority thread is executed, thereby reducing throughput. It is possible to improve.

  FIG. 6 shows an example of a case where a plurality of threads are simultaneously executed by a multithread processor that performs IPC control together with arbitration by priority. The example of FIG. 6 shows a case where a single pipeline multi-thread processor with only one thread that can be simultaneously processed is actually executed (a cache miss or a branch prediction miss occurs).

  Also in the example shown in FIG. 6, as in the example shown in FIG. 5, thread # 0 has the highest priority and thread # 7 has the lowest priority. First, thread # 1, thread # 2, and thread # 3 becomes executable. Due to the arbitration of computing resources by priority, execution of the thread # 1 having the highest priority among the executable thread # 1, thread # 2, and thread # 3 is given priority. In the case of the ideal execution illustrated in FIG. 5 described above, since no cache miss or branch prediction miss occurs, threads are executed in order according to priority. In this ideal case, there is no IPC change because there is no interference between threads. On the other hand, in the actual execution illustrated in FIG. 6, a cache miss or a branch prediction miss may occur. For example, when thread # 1 stalls due to this type of mistake, thread # 2 with the next highest priority is executed. Since the context of the thread # 2 is held in the processor, the thread # 2 can be immediately executed without performing a context switch. For this reason, it appears that “thread # 1 and thread # 2 (or more threads) are executed simultaneously in parallel”. Since thread # 2 uses computational resources, it affects the execution time of thread # 1, which has a higher priority. For this reason, interference between threads occurs, and IPC changes occur. When IPC control is not adopted, the time prediction accuracy of thread # 1 is lowered. On the other hand, by adopting IPC control, the number of instructions executed (IPC) of each thread # 1 and # 2 being executed simultaneously is brought closer to the target value of each thread # 1 and # 2. The frequency of execution is controlled. Therefore, even when a plurality of threads are executed simultaneously, the decrease in time prediction accuracy is small. Therefore, it is possible to improve the throughput of the entire processor while keeping time constraints.

  5 and 6 exemplify the case of a single pipeline processor for easy understanding. However, the same description applies to an SMT processor that can simultaneously process a plurality of threads as shown in FIG. FIG. 7 shows an example in which a plurality of threads are simultaneously executed (actual execution) by an SMT processor having the four pipelines shown in FIG.

  As shown in FIG. 7, in a multi-pipeline SMT processor, a larger number of threads seem to be executed concurrently in parallel. The greater the number of threads that are executed in parallel, the more frequently the resource contention between threads occurs, and the time prediction accuracy for each thread is further reduced. Therefore, there is a great advantage that the decrease in time prediction accuracy due to the adoption of IPC control can be suppressed.

  Now, a more specific and detailed control method of resource arbitration by priority and IPC control in the processor 10 employing the SMT architecture shown in FIG. 2 will be described below.

  First, a resource arbitration control method based on priority will be described.

  This control mediates and resolves competition among threads in each operation resource such as an instruction fetch slot, instruction issue slot, and operation unit when a plurality of threads are executed simultaneously. In this case, the priority assigned by the scheduler is used to resolve the conflict between threads. By using the priority for the conflict resolution between threads generated in the processor 10, it is possible to prevent the low priority thread from obstructing the execution of the high priority thread and to guarantee the execution of the high priority thread. However, if the priority is simply introduced to all the competing processes, the performance of the entire system is lowered, and the latency concealment effect by multithread cannot be obtained. Therefore, a mechanism for executing a low priority thread without degrading the performance of a high priority thread is adopted. Since the SMT architecture adopts a superscalar architecture, the performance of a single thread is higher than that of a normal single pipeline. However, in order to increase the performance of a single thread as much as possible, it is necessary to share execution resources among threads so that all execution resources can be used by one thread. Sharing execution resources can be expected to improve the performance of a single thread, but it tends to affect performance between threads, so low-priority threads adversely affect the performance of high-priority threads. End up. As countermeasures, in addition to slot priority control such as fetch slots and issue slots, control of shared resource occupancy can also be implemented. Also, a control method is adopted in which a bottleneck in fetch thread selection is avoided as much as possible and the entire instruction supply mechanism is controlled. At that time, paying attention to the difference between the properties of the soft real-time task and the hard real-time task, a control method that places a large weight on the performance of a single thread, and a weight on the overall performance while suppressing a decrease in the performance of a single thread A control method can be implemented.

  In fetch thread selection, it is possible to adopt a control method that can fetch other threads while suppressing the performance degradation of the highest priority thread as much as possible. When focusing on minimizing the performance degradation of the highest priority thread as much as possible, other lower priority threads use slots that are wasted (not used) by the highest priority thread under certain circumstances. Therefore, it can be expected that the performance of the entire system will be improved to some extent. The following can be mentioned as such a control method.

(1) Cache miss in instruction fetch The same thread fetching an instruction after a cache miss only unnecessarily complicates the hardware. Another thread fetches until an instruction returns from the cache.

(2) Recovery from a branch misprediction The instruction in the pipeline is discarded due to a branch misprediction when the branch instruction is committed. When the branch instruction is written back, the success or failure of the prediction is known, so if there is a misprediction, subsequent fetches are wasted. Therefore, when the branch instruction written back has a misprediction, fetch is performed from another thread until the instruction is committed.

(3) Number of instructions in the instruction buffer In order not to degrade the performance of the highest priority thread, it is necessary to keep issuing to the execution mechanism as much as possible. For this purpose, it is necessary to always store an instruction in the instruction buffer. In the case of the processor 10 shown in FIG. 2, since there are five stages until the instruction issuance, if there are 6 clock instructions in the instruction buffer 30 in the instruction buffer 30 at the time of thread selection, fetch from other threads at that clock Even if the operation is performed, there is no shortage of instructions in the instruction buffer. Since 24 instructions are present in the instruction buffer 30 because 4 instructions are issued simultaneously, fetching is performed from a thread having a low priority. However, the number of valid instructions among the instructions fetched by the next highest priority thread is unknown at this point, and the next instruction fetch may cause a cache miss. If you take this into account, you can prevent performance degradation by increasing the number of instructions.

  The above three control methods are methods in which the instructions of the lower priority thread are stored using the slots that the highest priority thread wastes. On the other hand, it is also possible to employ a control method in which a thread with a low priority is predicted to use an execution resource inefficiently and a thread with a low priority is fetched. Examples are given below.

(1) Number of conditional branch instructions in the pipeline The more conditional branch instructions are executed, the higher the possibility of branch misprediction and the higher the possibility of wasting execution resources. Therefore, when the number of conditional branch instructions in the pipeline exceeds the threshold value, fetching is performed from a thread having a low priority.

(2) Number of instructions in the pipeline As the number of instructions in the pipeline increases, more instructions wait for the data on which they depend, making it difficult to fill the execution slot. This phenomenon is particularly noticeable when the number of instructions in a single thread increases. For this reason, when the number of instructions in the pipeline exceeds a threshold, fetching is performed from a thread with a low priority.

(3) Number of instructions in the instruction buffer In the control method described above, it is assumed that the maximum number of instructions is always issued. However, the maximum number of instructions may not be issued due to a problem such as the reservation station 60. Therefore, the threshold value is set lower than the above-described 24 instructions. It is considered that the lower the threshold value, the lower the performance of the high priority thread.

(4) Number of stages occupied in the fetch control unit Compared with the branch predictor used for decoding, BTB (Branch Target Buffer, not shown) has no information on whether there is a branch instruction. The prediction accuracy is greatly inferior. Therefore, the speculative fetch number by BTB is limited. By controlling the number of stages in the fetch control pipeline, the number of consecutive fetches is suppressed.

(5) Number of waiting instructions in the reservation station If there is a bias in the execution units used or if there is a strong dependency relationship between the instructions, there is a possibility that the reservation station 60 will be filled with control by the number of instructions in the pipeline. There is. Therefore, the number of instructions in the reservation station 60 is counted, and when the threshold is exceeded, fetching is performed from a thread having a low priority.

  The above five control methods place emphasis on improving the performance of the entire system.

  In the issue instruction selection, it is considered that if the instruction fetch mechanism has enough instructions to directly supply an instruction to the instruction execution unit 16, the performance of the thread is greatly affected. Therefore, in order to suppress a decrease in the performance of a high-priority thread, the instruction issue mechanism issues an instruction of a thread with a high priority as much as possible. In the issue instruction selection by priority, similarly to the fetch thread selection, an instruction of a thread with a low priority is issued by the following method.

(1) When the target reservation station is full If the instruction of a thread with a low priority includes an instruction that uses another reservation station, that instruction is issued.

(2) When the reorder buffer and rename register are full: When these execution resources are owned by each thread, issue instructions from other threads.

(3) In the case of an instruction for which speculative execution is prohibited In the case of an instruction for which speculative execution is prohibited, such as an instruction for writing to the control register, the instruction issuance is stopped unless all instructions before that instruction are committed.

(4) When recovering from a branch misprediction As with fetch thread selection, if a branch instruction that has been written back has made a misprediction, it stops issuing instructions until the instruction commits.

When the target reservation station 60 is full, many instructions cannot be issued from a low-priority thread unless the units used by the high-priority thread and the low-priority thread are biased and different. In addition, when the reorder buffer 40 and the rename register 34 are configured to be shared among threads, it is impossible to issue an instruction from a thread having a low priority, and an instruction whose speculative execution is prohibited is a normal program. Is less frequent. That is, there is a low possibility that an instruction of a thread with a low priority is issued as compared with fetch thread selection in which a cache miss may occur. A further control method is adopted for hiding latency by parallel execution of multiple threads. Furthermore, emphasis is placed on the overall system performance, the following parameters:
-Number of conditional branch instructions in the pipeline-Number of instructions in the pipeline-Refer to the number of waiting instructions in the reservation station and stop issuing instructions from threads with high priority.

The control method for resolving contention related to slots in the pipeline such as instruction fetch and issue has been described above. In addition, in the SMT architecture, execution resources are shared by multiple threads, so it is necessary to consider the contention control. The execution resource here is typically
Instruction buffer 30
・ Rename register 34
・ Reorder buffer 40
And so on. These execution resources are provided in two ways: prepared for each thread or shared.

  When execution resources are prepared for each thread, it is possible to keep the influence between threads low. Even if one thread is stalled, other threads can be easily executed. However, since the amount of one thread that can be used is kept small, the performance of a single thread is lowered. On the other hand, when an execution resource is shared among threads, when a single thread is preferentially executed, the execution resource can be used sufficiently, and the performance is improved. However, since the influence between threads becomes large, a low-priority thread inhibits a high-priority thread. Also, when a thread stalls, other threads may not execute.

  Considering the influence between threads in this way, the method of preparing execution resources for each thread is preferable, but the amount of resources per thread can be kept small because of the chip size limitation. For this reason, the performance of threads with high priority is lowered, and there is a problem in terms of high performance that can withstand soft real-time processing. Therefore, the processor 10 shown in FIG. 2 aims to improve the performance of a single thread by sharing execution resources.

  By partitioning each buffer (dividing it into several units), hardware complexity can be prevented. By designing one partition to be used only by a single thread, it is only necessary to store the order of use of the partition and the current position in the partition for each thread, thereby simplifying the hardware.

  By sharing each buffer, a thread having a low priority occupies the buffer, thereby hindering execution of a thread having a high priority. Therefore, in order to suppress the influence on the performance between threads in the shared buffer, the number of buffer entries that can be used by each thread is set by software in units of partitions. In this regard, the following two control methods can be employed.

(1) Resource reservation Set partition usage rights for each thread using the control register. The same partition can be used by multiple threads.

(2) Maximum number setting Set the maximum number of partitions that can be used for each thread using the control register.

  In the resource reservation method, the resources that can be used for each thread can be specified individually, so stable performance can be expected, but it corresponds to the case where the thread cannot be executed, such as when the periodic task finishes executing and waits for the next period It is difficult to use execution resources effectively. In the maximum number setting method, other slots are controlled by priority control, so execution resources can be used from the highest priority thread up to the maximum amount specified, depending on the situation. It is easy to use execution resources as much as possible. However, if the total of the maximum number of each thread exceeds the total number of partitions, a thread with a low priority will impede execution of a thread with a high priority. The resource reservation method can statically predict the performance, and the maximum number setting method can dynamically increase the efficiency of execution resource usage. However, it is difficult to maintain the performance of the highest priority thread only with these control methods. For example, when a thread with a high priority is ready for scheduling and the highest priority thread is switched, a thread with a low priority that has been executed so far occupies execution resources, and a thread with a high priority. Execution will be hindered. Therefore, if the number of partitions storing high-priority thread instructions is less than the threshold and there is no free partition, the thread instruction with the lowest priority among the threads currently using that resource is selected. Discard. In the case of the instruction buffer 30, the instruction is refetched from the head instruction of the thread, and in the reorder buffer 40, an instruction in the pipeline is discarded using the same mechanism as in the case of a branch prediction miss.

  In the SMT architecture, even if control is performed based on priority, execution of the highest priority may be affected depending on the threads that are executed simultaneously. Therefore, in order to improve predictability of the processor performance and improve the overall throughput, each thread can be controlled to allocate an amount of processor resources according to its priority. For example, with respect to instruction fetch, the allocation amount of each instruction buffer to each thread can be controlled to follow the priority of each thread. This makes it easier for the lower priority thread to acquire the fetch right, so that the performance of the highest priority thread may be somewhat reduced, but the fluctuation in performance is reduced and the predictability is considered to be increased. In addition, improvement in overall performance can be expected by improving the use efficiency of the instruction buffer.

  This control regarding instruction fetch will be specifically described below. This control is executed mainly by the fetch thread selector 24 in the processor 10 shown in FIG. This control monitors the instruction buffer occupancy of each thread, and if the occupancy of a lower priority thread exceeds the occupancy of a higher priority thread, the thread from the lower priority thread Instruction fetch is suppressed or prohibited. The following symbols are used in the following description.

Ti: Thread;
Gj: A group of threads given the same priority. The priority between groups is assumed to be Gj>Gj-1;
ThOfMinIQ (Gj): Thread with the smallest instruction buffer occupancy in group Gj;
THNUM (Gj): Number of threads Ti belonging to group Gj;
IQSUM (Gj): Number of instruction buffers occupied by group Gj (total number of instruction buffers occupied by threads belonging to group Gj);
MINIQ (Gj): Minimum number of instruction buffers occupied by group Gj;
MIN_IQ_THRESH: a predetermined lower limit for the number of instruction buffers occupied per thread;
FREQj: Group Gj fetch request;
FETCHj: Thread that fetches when fetch request FREQj is accepted (fetch thread).

The fetch request FREQj and the fetch thread FETCHj are determined according to the following control conditions (1) and (2).
FREQj =
MINIQ (Gj) ≦ IQSUM (Gj-1)
or
IQSUM (Gj) ≤ MIN_IQ_THRESH × THNUM (Gj)… Control condition (1)
FETCHj = ThOfMinIQ (Gj)… Control condition (2)
Here, the value MIN_IQ_THRESH is a lower limit value for the purpose of reducing the frequency with which the instruction buffer of each thread becomes empty. When the instruction buffer occupation number of each thread falls below this lower limit value MIN_IQ_THRESH, each thread can issue a fetch request unconditionally. This value MIN_IQ_THRESH is the following condition value,
・ The number of instructions fetched by one fetch ・ The shortest number of cycles required from the start of fetch to the issue of instructions ・ It can be determined by the maximum number of instructions issued in one cycle. For example, in the processor 10 shown in FIG. 2, eight instructions are fetched in one cycle, six cycles are required from the start of fetching to issuing an instruction, and four instructions are issued in one cycle. Therefore, it is considered that the frequency at which the supply of instructions is interrupted can be reduced by starting fetching when the number of instructions in the instruction buffer reaches 24. Therefore, “24” can be adopted as the value MIN_IQ_THRESH.

  According to the control condition (1), the minimum value MINIQ (Gj) of the instruction buffer occupation number of a certain group Gj is lower than the instruction buffer occupation number IQSUM (Gj-1) of the group Gj-1 having a lower rank priority. When the instruction buffer occupation number IQSUM (Gj) of a certain group Gj is equal to or less than the lower limit value MIN_IQ_THRESH × THNUM (Gj) of the instruction buffer number to be occupied by the group Gj The fetch request FREQj of the group Gj is permitted, but the fetch request FREQ j-1 of the group Gj-1 having a lower priority is not permitted. According to the control condition (2), when the fetch request FREQj of the group Gj is recognized, the fetch right is given to the thread ThOfMinIQ (Gj) having the smallest instruction buffer occupation number in the group Gj.

  As described above, FETCHj and FREQj are determined. In the processor 10, only one thread performs fetch in one cycle, so one thread must be selected from a plurality of fetch requests. Therefore, in order to prioritize the execution of the highest priority thread, a control method can be adopted in which a fetch request of the highest priority group is selected and the fetch thread is determined. Further, even when a thread selected as a fetch thread causes a cache miss or the like and cannot be fetched, the fetch right may not be transferred to a lower priority thread. This is to prevent reversal of the resource occupancy and prevent the lower priority thread from squeezing the performance of the upper priority thread.

  On the other hand, in this control method, it is considered that the lower priority thread easily obtains the fetch right, and the overall performance of the processor is improved. On the other hand, the higher priority thread is controlled so that more instruction buffers can be acquired regardless of the program characteristics. The problem is that many instruction buffers are allocated to low priority threads, Occupied problems are unlikely to occur. This advantage is further strengthened by a combination with a command issue control method described later. Further, in this control method, when there are a plurality of threads having the same priority, the fetch is performed from the thread having the smallest instruction buffer occupation number among them.

  Next, an instruction issue control method will be described.

  Similar to the instruction fetch control, the instruction issue of each thread is controlled so that the occupation amount of the resource follows the priority. This instruction issue control is executed by, for example, the instruction issue selector 32 in the processor 10 shown in FIG. In this command issue control, a reservation station or a reorder buffer can be adopted as a resource to be monitored. In the control described below, the occupancy of each reservation station thread is monitored, and if the occupancy of a lower priority thread exceeds the occupancy of a higher priority thread, the lower priority Instruction issue from the thread is suppressed or prohibited. In the following description, the following symbols are used.

Tj, k: threads belonging to group Gj;
RSNUM (Tj, k): Number of reservation stations occupied by thread Tj, k;
RSSUM (Gj.): Number of reservation stations occupied by group Gj (total number of reservation stations occupied by threads belonging to group Gj);
IREQj, k: Instruction issue request for thread Tj, k.

The instruction issue request IREQj, k is determined according to the following control condition (3).
IREQj, k = RSNUM (Tj, k) ≤ RSSUM (Gj-1) ... Control condition (3)

  According to the control condition (3), the reservation station occupation number RSNUM (Tj, k) of a thread Tj, k is equal to or less than the reservation station occupation number of the group Gj-1 having a lower rank priority than that. When the number is low, the instruction issue request IREQj, k of the thread Tj, k is accepted, but the instruction issue request IREQj-1, k of the group with the lower priority is not accepted. Here, in the processor 10 shown in FIG. 2, a maximum of four threads can issue instructions in one cycle. Unlike instruction fetch, there may be an instruction issue request from multiple threads in the same group. Therefore, in the instruction issuance control, the threads issuing the instruction issuance requests are ranked as follows, and the top four threads in the rank are set as the issuing threads.

-Order in descending order of priority given to threads-Order in which the reservation station 60 occupies the smallest number among threads of the same priority (group)

  The instruction issue control method is very similar to that of the aforementioned instruction fetch. The difference is that the number of occupations of the reservation station 60 is used instead of the number of occupations of the instruction buffer 30, and there is no condition corresponding to the lower limit value MIN_IQ_THRESH of the occupation number. The reason for using the reservation station 60 as a criterion for selecting an issue thread is as follows. That is, there is a case where the thread selected as the issuing thread cannot actually be issued. This is mainly the case as follows.

There is no space in the reorder buffer 40. There is no space in the rename buffer 34. There is no space in the reservation station 60 of the issuing execution unit. In the processor 10, the reorder buffer 40 and the rename buffer 34 are linked and are actually limited. It is the reorder buffer 40 or the reservation station 60 that becomes. Of these, in practice, there are many cases where the reservation station 60 is not empty and cannot issue an instruction. Therefore, in the above control condition (3), the number of occupations of the reservation station 60 is used as a thread selection criterion in order to allocate more precious resources to high priority threads. Actually, it was found from the evaluation test conducted by the inventor that the reservation station 60 is more influential than the reorder buffer 40.

  Next, a specific method of IPC control will be described.

  In real-time processing, predictability of task execution time is important. Therefore, a mechanism for controlling the IPC can be added to the above-described instruction fetch and instruction issue mechanism. In IPC control, the number of instructions executed by each thread is monitored at regular intervals, and if it does not reach the specified target value, the frequency of instruction fetch and issue is increased. Moreover, the performance of the program may change greatly with time, and this point is also taken into consideration in the IPC control described below.

In this IPC control, an inflation value INFLj that changes according to the current IPC of the group Gj is introduced, and the above-described instruction fetch and issue control conditions (1) and (3) are controlled by the following control conditions (4) and (5 ) Is changed.
FREQj =
MINIQ (Gj) ≤ IQSUM (Gj-1) + INFLj × THNUM (Gj)
or
IQSUM (Gj) ≤ MIN_IQ_THRESH × THNUM (Gj)… Control condition (4)
IREQj, k = RSNUM (Tj, k) ≤ RSSUM (Gj-1) + INFLj… Control condition (5)
Here, as already described with reference to FIG. 4, the inflation value INFLj is increased or decreased according to the current performance of the group Gj within a predetermined value range, for example, a range of 0 ≦ INFLj ≦ 32. That is, when the IPC specified by the group Gj is not obtained, the inflation value INFLj increases, thereby suppressing the fetching and issuing of threads having a lower priority than the group Gj, and the thread of the group Gj Increase performance. The reason why the variable range of the inflation value INFLj is 0 to 32 is that the instruction buffer 30 and the reservation station 60 have 32 entries in the processor 10 shown in FIG.

  As mentioned above, although embodiment of this invention was described, this embodiment is only the illustration for description of this invention, and is not the meaning which limits the scope of the present invention only to this embodiment. The present invention can be implemented in various other modes without departing from the gist thereof.

Claims (14)

In a multi-thread central processing unit that processes a plurality of threads in parallel,
Priority storage means for storing the priority of each thread;
First control means for controlling the order or frequency of instruction processing of the plurality of threads using the priority of each thread;
Target storage means for storing a target value of the number of executed instructions per fixed repetition period of each thread;
The instruction execution state of each thread is monitored, and the instructions of the plurality of threads controlled by the first control unit are controlled by a feedback control operation using the actual number of executed instructions per repetition period and the target value. Second control means for adjusting the order or frequency of processing,
The first control means monitors the allocation amount of the predetermined resource in the device to the plurality of threads, and the allocation amount to the plurality of threads follows the priority of the plurality of threads. A multi-threaded central processing unit that controls the order or frequency of fetch, issue, or execution of instructions for threads. The apparatus of claim 1.
The first control means has an allocation amount of the resource to one or more first threads having a first priority of one or more having a second priority lower than the first priority. Facilitate fetching, issuing, or executing instructions of at least one thread in the first thread when less than to a second thread, or fetching, issuing, or executing instructions of the second thread Multi-thread central processing unit that suppresses The apparatus of claim 1.
The first control means facilitates fetching, issuing, or executing an instruction of each thread when the resource allocation amount to each thread is small and does not satisfy a predetermined lower limit condition; or A multi-threaded central processing unit that removes restrictions on fetching, issuing, or executing instructions. The device according to claim 2 or 3,
The multi-thread central processing unit, wherein the at least one thread in the first thread includes a thread having a minimum occupation amount of the resource in the first thread. The device according to any one of claims 1 to 4,
The multi-thread central processing unit, wherein the predetermined resource includes an instruction buffer for holding fetched instructions of the plurality of threads until they are issued. The apparatus of claim 5, wherein,
The multi-thread central processing unit, wherein the predetermined resource includes one or more reservation stations that hold the instructions of the plurality of threads issued from the instruction buffer until the instructions are executed. The device according to any one of claims 1 to 6,
When the actual number of execution instructions of a thread does not satisfy the target value so that the second control means approaches the target value of each thread so that the actual number of execution instructions of each thread A multi-thread central processing unit that facilitates fetching or issuing instructions of the certain thread or suppressing fetching or issuing instructions of other threads having a lower priority than the certain thread. The device according to any one of claims 1 to 7,
In order for the second control means to make the actual execution instruction number of each thread approach the target value of each thread, the actual execution instruction number of a certain thread satisfies the target value. If not, an adjustment for increasing the frequency of processing of the instruction of the certain thread is added to the control of the first control means, and the actual execution instruction of the certain thread even if the adjustment is added A multi-thread central processing unit that cancels the added adjustment if no improvement appears in the number that satisfies a predetermined condition. The device according to any one of claims 1 to 8,
The second control means comprises:
A monitoring unit that counts the number of instructions executed for each thread for each monitoring period;
For each thread, a first comparison is performed to check whether the actual number of instructions executed in the current monitoring cycle satisfies a preset target value, and the number of instructions executed in the previous monitoring cycle for each thread. A comparison unit that performs a second comparison that obtains a carry-over residual value that is an addition of the deficiency of the target value and the target value, and checks whether the actual number of executed instructions in the current monitoring cycle satisfies the carry-over residual value;
A multi-thread central processing unit having a control unit that varies the frequency of instruction fetch or instruction issue based on the result of the first and second comparisons for each thread. The apparatus of claim 9.
The control unit is
For each thread, the instruction execution state is a first state in which both the first and second comparison results are positive, and the first comparison result is positive but the second comparison result is negative. Means for determining whether the second state is a target and the third state in which both the first and second comparison results are negative;
Means for decreasing the frequency of instruction fetch or instruction issue if the first state continues for a predetermined first time length for each thread;
Means for increasing the frequency of instruction fetch or instruction issue if the second state continues for a predetermined second time length for each thread;
Means for increasing the frequency of instruction fetch or instruction issue if the third state continues for a predetermined third time length for each thread;
Means for performing a resource up check for checking whether an increase of a predetermined degree or more has occurred in the number of execution instructions when the frequency of the instruction fetch or the instruction issue is increased for each thread;
A multi-thread central processing unit having means for reducing the frequency of the instruction fetch or the instruction issuance when the result of the resource up check is negative for each thread. The apparatus of claim 1.
In a normal situation, the first control means processes an instruction of a higher priority thread before an instruction of a lower priority thread, and the upper priority thread wastes a predetermined resource in the device. Or a multi-thread central processing unit that performs control so that instructions of the lower priority thread are processed before instructions of the higher priority thread under predetermined circumstances such that they are used inefficiently or inefficiently. The apparatus of claim 1.
Multi-thread in which the second control means controls the order or frequency of fetching or issuing instructions of the plurality of threads so that the actual number of instructions executed by each thread approaches the target value of each thread Central processing unit. The apparatus of claim 1 .
Said second control means, wherein the adjustment for the actual number of executed instructions for each thread to approach the target value of said each thread, multi-threaded central processing applied to control of said first control means apparatus. A simultaneous multithreading control method in a multithread central processing unit that processes a plurality of threads in parallel,
A step of storing a priority of each thread by a priority storage means;
A step of controlling a sequence or frequency of processing of instructions of the plurality of threads by using a priority of each thread;
A step of storing a target value of the number of execution instructions per fixed repetition period of each thread;
The second control means monitors the instruction execution state of each thread, and is controlled by the first control means by a feedback control operation using the actual number of executed instructions per repetition period and the target value. Adjusting the order or frequency of processing of the instructions of the plurality of threads;
The first control means monitors the allocation amount of the predetermined resource in the device to the plurality of threads, and the allocation amount to the plurality of threads follows the priority of the plurality of threads. A simultaneous multithreading control method that controls the order or frequency of fetching, issuing, or executing instructions of a thread.

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