JP2012113487A - Multithread processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multithread processor capable of improving processing efficiency.SOLUTION: A multithread processor is characterized by the presence of a plurality of threads for performing a hardware multi-threading processing. When the plurality of threads perform access processing to a specific shared access object, they request a dedicated thread, which performs access processing to the specific shared access object, to perform the access processing.

Description

  The present invention relates to a multi-thread processing apparatus in which a plurality of threads perform processing on each of them, and particularly to a multi-thread processing apparatus that performs hardware multi-threading processing by a plurality of threads.

  In recent years, techniques for realizing a plurality of functions by a single processor have been researched and put into practical use as the performance of the processor has been improved. For example, in the field of in-vehicle control devices mounted on vehicles, a control device that controls a certain in-vehicle device and a control device that controls other in-vehicle devices (for example, a transmission control device and an engine control device) are integrated. There is a trend to reduce computer hardware and reduce costs and weight.

  One method of hardware integration is known as hardware multithreading processing. In hardware multithreading processing, multiple threads with different instruction buffers and operation result storage locations (registers) share part of the hardware such as instruction decoders and arithmetic circuits. .

  A multi-thread processing device that performs hardware multi-threading processing includes a storage device such as a RAM and an access target such as an I / O, as in a normal computer. Such an access target is controlled so that only one thread can access it. For this reason, when a plurality of threads try to access the same access target while performing parallel processing in a time-sharing manner, the thread that issued an access request later enters a processing wait state. For this reason, there is a case where the clock supplied to the thread waiting for processing is wasted.

  On the other hand, Patent Document 1 describes a disk controller that executes a write command task for a disk drive device, which is a lower-level device, in response to a write command from a higher-level device. In this disk controller, when an error is detected during execution of a write instruction, an alternative processing task having a high priority is generated and error processing is performed.

Japanese Patent Laid-Open No. 2-173983

  However, since the disk controller described in Patent Document 1 generates an alternative process only when an error occurs, the processing efficiency cannot be improved in a normal processing state where no error occurs.

  In addition, the time division multitask system in the disk controller described in Patent Document 1 does not assume hardware multithreading in the first place, and the alternative processing task performs error processing to the last, and hardware multithreading processing. In the multi-thread processing apparatus that performs the above, access to the shared access target is not subjected to alternative processing.

  The present invention is for solving such problems, and a main object of the present invention is to provide a multithread processing apparatus capable of improving the processing efficiency.

In order to achieve the above object, one embodiment of the present invention provides:
A multi-thread processing device in which hardware multi-threading processing is performed by a plurality of threads,
When the plurality of threads perform an access process to a specific shared access target, a proxy thread that performs the access process to the specific shared access target is delegated to the specific shared access target. It is characterized by requesting,
A multi-thread processing device.

  According to this aspect of the present invention, when performing access processing to a specific shared access target, a dedicated thread that performs access processing to the specific shared access target is requested to perform access processing proxy. The thread that has requested access processing proxy can perform other general processing until the access processing ends. As a result, the processing efficiency can be improved.

In one embodiment of the present invention,
The plurality of threads, when requesting the dedicated thread to perform access processing for the specific shared access target, if the dedicated thread is not activated, instructs the dedicated thread to start and the access It is also possible to add a task related to a proxy for processing and add a task related to the proxy for the access processing when the dedicated thread is activated.

In one embodiment of the present invention,
It is preferable that the allocation ratio of execution time to the plurality of threads and the dedicated thread can be changed.

  By doing this, it is possible to appropriately determine the allocation ratio of execution time to a plurality of threads and dedicated threads according to how much execution time is required for the access process requested for the substitution.

in this case,
It is more preferable that the change of the execution time allocation ratio is performed by a thread that requests substitution of access processing to the specific shared access target among the plurality of threads. It is the thread that makes the proxy request that best understands how long the access process requested by the proxy requires.

  According to the present invention, it is possible to provide a multithread processing apparatus capable of improving processing efficiency.

1 is a system configuration example of a multithread processing apparatus 1 according to an embodiment of the present invention. FIG. 6 is a diagram schematically showing a state in which threads # 1, # 2 and an access dedicated thread #k are each executing a plurality of tasks. It is a flowchart which shows the flow of a process when each thread requests the access-dedicated thread #k to perform access process substitution. It is a flowchart which shows the flow of the process performed by the thread only for access #k. It is a figure which shows the operation example by the conventional multithread processing apparatus. It is a figure which shows the operation example by the multithread processing apparatus 1 of a present Example. It is a figure which shows the other operation example by the multithread processing apparatus 1 of a present Example. It is a figure which shows the operation example by the conventional multithread processing apparatus. It is a figure which shows the operation example by the multithread processing apparatus 1 of a present Example. It is a figure which shows the other operation example by the multithread processing apparatus 1 of a present Example.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings.

  A multi-thread processing apparatus 1 according to an embodiment of the present invention will be described below with reference to the drawings.

[Constitution]
FIG. 1 is a system configuration example of a multithread processing apparatus 1 according to an embodiment of the present invention. The multi-thread processing apparatus 1 includes, as main components, a program memory 10, an instruction fetch bus 15, an instruction fetch unit 20, instruction buffers 22 # 1 to 22 # n, an instruction decoder 24, and an instruction issuing unit 26. , Registers 28 # 1 to 28 # n, an arithmetic unit 30, an LSU 32, a control device 40, a specific shared access target 50, and a data bus 55.

  In this embodiment, it is assumed that the number of threads (including an access dedicated thread described later) that is an arbitrary number of 2 or more is n, and the number after “#” indicates the thread number. The configuration shown in FIG. 1 exemplifies a general configuration for performing hardware multithreading processing, and any configuration element can be used as long as it can perform hardware multithreading processing. Replace, delete, add, etc.

  The hardware multithreading process is a process in which a plurality of threads share a part of hardware such as an instruction decoder and an arithmetic circuit. A thread is a virtual processing entity that performs processing while partially sharing hardware. In this embodiment, an instruction buffer and a register are prepared for each thread, but other components are shared between threads.

  The program memory 10 is, for example, a flash ROM (Read Only Memory), and stores a program (instruction sequence) executed by each thread. When an address indicating the instruction storage location is input from the instruction fetch unit 20, the program memory 10 outputs the instruction stored at the address.

  The instruction fetch unit 20 incorporates a program counter for each thread, fetches an instruction from the program memory 10 via the instruction fetch bus 15, and stores the instruction buffer corresponding to the thread among the instruction buffers 22 # 1 to 22 # n. Store.

  That is, when an instruction executed by thread # 1 is fetched, the instruction is stored in instruction buffer 22 # 1, and when an instruction executed by thread # 2 is fetched, the instruction is stored in instruction buffer 22 # 2.

  The instruction buffers 22 # 1 to 22 # n are controlled to input / output instructions according to, for example, FIFO (First In, First Out).

  The instruction decoder 24 decodes (decodes) an instruction supplied from any instruction buffer and outputs the instruction to the instruction issuing unit 26. The result of decoding by the instruction decoder 24 is, for example, the type of operation, the source operand, the storage location of the result, and the like.

  The instruction issuing unit 26 acquires the operation target value and the like from the registers 28 # 1 to 28 # n according to the instruction input from the instruction decoder 24, and outputs it to the arithmetic unit 30 and the LSU 32.

  The arithmetic unit 30 performs four arithmetic operations and other arithmetic processes in response to a thread request. On the other hand, the LSU 32 executes a store instruction or a load instruction in response to a thread request.

  The control device 40 controls these operations as a whole. Specifically, the instruction fetch unit 20, the instruction decoder 24, the instruction issuing unit 26, the arithmetic unit 30, the LSU 32, and the like are operated according to the rising edge of the internal clock.

  The control device 40 controls thread switching. For example, when the processing of the thread # 1 is performed for one clock, the switching control is performed such that the processing of the thread # 2 is performed for one clock and the processing of the thread # 1 is performed for one clock next. These thread processing time allocations can be arbitrarily set, and the control device 40 may incorporate a setting holding register 42 for holding the setting state.

  The specific shared access target 50 is a specific device group accessed by the LSU 32 or the like via the data bus 55. For example, a data memory such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) or a RAM (Random Access Memory), an I / O, CAN (Controller Area Network) controller, and the like may be applicable. The I / O includes, for example, an I / O port and its control device.

[Access proxy request]
The thread in this embodiment is capable of executing a plurality of tasks (indicating a group of instructions having a certain functional unit) in parallel or in a desired order.

  By the way, the tasks executed by the thread include operations that are relatively short in processing time and do not include access to the data bus 55, such as performing calculations by the calculator 30 and storing them in the registers 28 # 1 to 28 # n. Access to the specific shared access target 50 via the data bus 55 and a relatively long processing time are mixed.

  When performing the access process to the specific shared access target 50, the thread in this embodiment requests the dedicated thread that performs the access process to the specific shared access target 50 to perform the access process proxy. Hereinafter, such a dedicated thread is referred to as an “access dedicated thread”.

  Although not shown in FIG. 1, in addition to the specific shared access target 50, there may be an access target (hereinafter referred to as “non-specific access target”) accessed via the data bus 55 or other bus. For each non-specific access target, each thread may not request an access-dedicated thread for access processing.

  When there are non-specific access targets, it may be arbitrarily determined depending on the system specifications whether to handle various access targets as the specific shared access target 50 or the non-specific access target.

  FIG. 2 is a diagram schematically showing a state in which the threads # 1, # 2 and the access dedicated thread #k are each executing a plurality of tasks. In this figure, the task 10 executed by the thread # 1 and the task 21 executed by the thread # 2 are access processes to the specific shared access target 50, and the task 11 executed by the thread # 1 and the thread # 2 is a process other than the specific access process. Hereinafter, the access processing to the specific shared access target 50 is referred to as “specific access processing”, and the other processing is referred to as “general processing”. The general process may include an access process to the non-specific access target or may not include the general process.

  In FIG. 2, broken line arrows indicate data access in the conventional multithread processing apparatus. In conventional multithread processing, each thread independently performs access processing to the specific shared access target 50. For this reason, as will be described later, useless clocks are assigned to threads, and processing efficiency may be reduced.

  On the other hand, in the multi-thread processing apparatus of this embodiment, each thread that is not an access dedicated thread (hereinafter referred to as “each thread” excludes an access dedicated thread) is transferred to the specific shared access target 50. When the access process is performed, the access dedicated thread #k is requested to perform the access process, and only the access dedicated thread #k is controlled to perform the access process to the specific shared access target 50. A solid line in FIG. 2 indicates data access in the multithread processing apparatus 1 of the present embodiment.

  As a result, the thread that requested access processing proxy can perform other general processing until the access processing ends. Therefore, processing efficiency can be improved.

[Processing flow]
Hereinafter, the flow of processing when each thread requests the access dedicated thread #k to perform access processing proxy and the flow of processing in the access dedicated thread #k will be described.

  FIG. 3 is a flowchart showing the flow of processing when each thread requests the access dedicated thread #k to perform access processing proxy. This flow is started when each thread tries to access the specific shared access target 50.

  First, each thread determines whether or not the access dedicated thread #k has been activated (S100).

  If the access dedicated thread has not been activated, the controller 40 is instructed to activate the access dedicated thread #k (S102).

  Then, the access dedicated thread #k is notified to add an access processing task for the own thread (S104).

  In this way, each thread instructs activation of the access dedicated thread #k and addition of a task when the access dedicated thread #k has not been activated, and adds a task when the access dedicated thread #k has already been activated. Only instruct.

  FIG. 4 is a flowchart showing a flow of processing executed by the access dedicated thread #k. This flow is repeatedly executed every time an operation clock is assigned to the access dedicated thread #k.

  First, it is determined whether or not the access processing task being executed is completed in the operation clock (S200). If the access processing task being executed has not ended in the operation clock, one routine of this flow is ended.

  When the access processing task being executed is completed, it is determined whether another access processing task is in a waiting state (S202). If another access processing task is in a waiting state, the access processing task is terminated, and the access processing task in a waiting state is executed in the next routine (S204).

  Here, the access processing task may be stored in a waiting queue or the like possessed by the access-dedicated thread and executed in order according to the FIFO. However, the access processing task may be set to be executed immediately in response to an interrupt instruction from each task. .

  On the other hand, if another access processing task is not in a waiting state, the access processing task is terminated and the access dedicated thread #k itself is terminated (S206).

  At this time, instead of ending the access dedicated thread #k, it may be continued as an idle task (clock allocation is kept very low). In this way, it is possible to reduce the time and load required for starting and ending the access dedicated thread #k.

[Change operation ratio]
Further, in the multi-thread processing device 1 of the present embodiment, the thread operation ratio can be arbitrarily changed in response to the access processing proxy request or the activation and termination of the access dedicated thread. For example, when the thread # 1 and the thread # 2 operate at 1: 1 before the access processing proxy occurs, and an access processing proxy request that does not require much clock allocation occurs, the thread # 1 When the operation ratio between the thread 1, thread # 2, and the access thread #k is set to 1: 1: 1, and an access processing proxy request requiring a large number of clock allocations occurs, the thread # 1 and the thread # 2 And the operation ratio of the access dedicated thread #k may be set to 1: 1: 3. In this way, it is possible to maintain the processing efficiency of the entire apparatus and ensure the order of processing.

  The operation ratio can be set by rewriting the contents of the setting holding register 42, for example. The set operation ratio is notified to the control device 40 from the thread that performs the access processing proxy request. If the access processing is immediately performed in the control device 40, the setting holding register 42 according to the notified operation ratio. The contents of the setting holding register 42 are rewritten in accordance with the operation ratio notified at the timing when the access processing is performed.

[Operation comparison]
The difference in operation from the conventional multithread processing apparatus will be described below. Here, the same preconditions as in FIG. 2 are used. That is, the task 10 executed by the thread # 1 and the task 21 executed by the thread # 2 are access processing to the specific shared access target 50, and the task 11 executed by the thread # 1 and the thread # 2 The task 20 executed by is a general process other than the specific access process. In the conventional multi-thread processing apparatus, there is no concept such as “specific shared access target”, but it is described here in the same column. In FIGS. 5 to 10, portions indicated as “finger 1” and “finger 2” indicate that an instruction such as a write instruction is performed. A portion indicated by a number with an overline indicates consumption of clock time (unit: half clock). Further, the portion described as “play” indicates that CPU processing is wasted. That is, it is a play clock.

(For access with low clock allocation requirement)
5 to 7 show an operation example in the case where a time not requiring the CPU processing occurs in the execution time of the external peripheral as in the case where the specific shared access target 50 is an EEPROM or I / O, that is, the access processing The example of operation | movement in case it is not necessary to increase clock allocation with respect to execution of a task too much is shown.

  More specifically, in FIGS. 5 to 7, tasks 10 and 21 write to an EEPROM (abbreviated as “E2P” in FIGS. 5 to 7), and tasks 11 and 20 perform general processing. Writing to the EEPROM requires two clocks for the Write instruction and consumes 13 clocks. However, the processing by the access processing task is unnecessary within the time corresponding to 13 clocks.

  FIG. 5 shows an operation example of a conventional multithread processing apparatus.

  First, at time T0, the task 10 starts to access the EEPROM. As described above, the write process ends at time T2 with the write instruction and the passage of time of 13 clocks. During this period, access to the RAM by other tasks is prohibited (exclusive section). During this writing process, since a clock is continuously assigned to the task 10, 13 idle clocks are generated.

  Assume that a write request to the EEPROM by the task 21 is made at time T1 in the middle of the writing process by the task 10 (denoted as “exclusive request” in the figure). In this case, the task 21 is in a waiting state until the writing process by the task 10 is completed, and therefore the entire thread # 2 is in a waiting state. During this waiting state, since a clock is continuously assigned to the task 21, 10 idle clocks are generated.

  When the time T2 is reached, the task 21 starts to access the EEPROM. The write process ends at time T3 after the Write instruction and the time of 13 clocks have elapsed. During this writing process, the clock continues to be assigned to the task 21, so that 13 idle clocks are generated.

  Here, since the task 11 is a general process, it can be executed in parallel with the task 21. For this reason, the task 11 is executed during the time T2 to T3. With respect to the task 20, execution is started after the task 21 is completed.

  As a result, in the operation example shown in FIG. 5, a total of 36 clocks are generated.

  FIG. 6 shows an operation example by the multithread processing apparatus 1 of the present embodiment.

  In this figure, it is assumed that the clock allocation ratio of the thread # 1, the thread # 2, and the access dedicated thread #k after the access dedicated thread #k is activated is set to 1: 1: 1.

  First, at time T10, an instruction to start an access dedicated thread and an access processing task 10 * for itself are issued by the thread # 1, and the task 10 * by the access dedicated thread #k executes a write instruction. To do. The writing process ends at time T12 when 13 clocks have elapsed. During this writing process, a clock continues to be assigned to the task 10 *. However, since the clock assignment ratio is lower than that in FIG. 5, only eight idle clocks are generated.

  Thread # 1 can execute task 11 between time T10 and time T12. Here, it is assumed that the execution of the task 11 is completed after processing for 9 clocks.

  At time T11 in the middle of the write process by the task 10 * for the access dedicated thread, the task 21 instructs the access dedicated thread #k to add the access processing task 21 * for itself. In this case, the task 21 * is in a waiting state until the writing process by the task 10 * is completed, but the thread # 2 can start the general task 20 from the next clock. Here, it is assumed that the execution of the task 20 is completed after processing for 15 clocks.

  When the time T12 is reached, access to the EEPROM by the task 21 * is started. The write process ends at time T13 after the Write instruction and the passage of 13 clocks. During this write process, since a clock is continuously assigned to the task 21, eight idle clocks are generated.

  As a result, in the operation example shown in FIG. 6, a total of 16 idle clocks are generated, and the generation of idle clocks is suppressed as compared with the conventional multi-thread processing apparatus. Also, from the viewpoint of processing results, the conventional multithread processing apparatus is in a state where the task 20 has started gradually at time T3, whereas at time T13, which is substantially the same time as time T3, The processing device 1 has finished the processing of the task 20.

  From these, it can be seen that the processing efficiency is improved in the multithread processing apparatus 1 of this embodiment as compared with the conventional multithread processing apparatus shown in FIG.

  FIG. 7 shows another operation example by the multithread processing apparatus 1 of the present embodiment.

  In this figure, it is assumed that the clock allocation ratio of the thread # 1, the thread # 2, and the access dedicated thread #k after the access dedicated thread #k is activated is set to 2: 2: 1. That is, the clock ratio assigned to the access dedicated thread #k is reduced as compared with the operation example of FIG.

  In this case, the processing execution order is almost the same as the operation example of FIG. The time at which the processing of tasks 10 * and 21 * at which the clock allocation ratio decreases is slightly delayed compared to the operation example of FIG. 6, but more clocks can be allocated to the processing by tasks 11 and 20. (The figure shows that processing for 10 clocks and 19 clocks is possible, respectively). Further, the generation of idle clocks is less than that in the operation example of FIG.

(For access with high clock allocation requirement)
8 to 10 are examples of operations when CPU processing is required for writing and reading as in the case where the specific shared access target 50 is RAM, that is, a large number of clock allocations are required to execute the access processing task. An example of the operation is shown.

  More specifically, in FIGS. 8 to 10, tasks 10 and 21 write to the RAM, and tasks 11 and 20 perform general processing. It is assumed that writing to the RAM consumes time for 15 clocks. In the time corresponding to the 15 clocks, processing by the access processing task becomes unnecessary.

  FIG. 8 shows an operation example of a conventional multithread processing apparatus.

  First, at time T20, access to the RAM by the task 10 is started. As described above, the writing process ends at time T22 after the elapse of 15 clocks. During this period, access to the RAM by other tasks is prohibited (exclusive section).

  It is assumed that a write request to the RAM by the task 21 is made at time T21 during the writing process by the task 10 (denoted as “exclusive request” in the figure). In this case, the task 21 is in a waiting state until the writing process by the task 10 is completed, and therefore the entire thread # 2 is in a waiting state. During this waiting state, since a clock is continuously assigned to the task 21, 10 idle clocks are generated.

  When the time T22 is reached, access to the RAM by the task 21 is started. The writing process ends at time T23 with the passage of 15 clocks.

  Here, since the task 11 is a general process, it can be executed in parallel with the task 21. For this reason, the task 11 is being executed between times T22 and T23. With respect to the task 20, execution is started after the task 21 is completed.

  As a result, in the operation example shown in FIG. 8, a total of 10 idle clocks are generated.

  FIG. 9 shows an operation example by the multithread processing apparatus 1 of the present embodiment.

  In this figure, it is assumed that the clock allocation ratio of the thread # 1, the thread # 2, and the access dedicated thread #k after the access dedicated thread #k is activated is set to 1: 1: 2.

  First, at time T30, an instruction to start an access dedicated thread and an access processing task 10 * for itself are issued by the thread # 1, and the task 10 * by the access dedicated thread #k writes to the RAM. To start. The writing process ends at time T32 after the elapse of 15 clocks.

  Thread # 1 can execute task 11 between time T30 and time T32. In this figure, the number of clocks related to the execution of tasks 11 and 20 is omitted.

  At time T31 in the middle of the writing process by the task 10 * for the access dedicated thread, the task 21 instructs the access dedicated thread #k to add the access processing task 21 * for itself. In this case, the task 21 * is in a waiting state until the writing process by the task 10 * is completed, but the thread # 2 can start the general task 20 from the next clock.

  When the time T32 is reached, access to the RAM by the task 21 * is started. The writing process ends at time T33 with the passage of 15 clocks.

  As a result, since no idle clock is generated in the operation example shown in FIG. 9, the generation of the idle clock is suppressed as compared with the conventional multi-thread processing apparatus. Also, from the viewpoint of processing results, the conventional multithread processing apparatus is in a state where the task 20 has started gradually at time T23, whereas at time T33, which is substantially the same time as time T23, the multithread of this embodiment. The processing device 1 finishes the processing of the task 20 for 11 clocks.

  From these, it can be seen that the processing efficiency is improved in the multithread processing apparatus 1 of the present embodiment as compared with the conventional multithread processing apparatus shown in FIG.

  FIG. 10 shows another operation example by the multithread processing apparatus 1 of the present embodiment.

  In this figure, it is assumed that the clock allocation ratio of the thread # 1, the thread # 2, and the access dedicated thread #k after the access dedicated thread #k is activated is set to 1: 1: 4. That is, the clock ratio assigned to the access dedicated thread #k is lowered as compared with the operation example of FIG.

  In this case, the execution order of processing is almost the same as the operation example of FIG. The time at which the processing of tasks 11 and 20 ends is slightly later than the operation example of FIG. 9, but more clocks can be assigned to the processing by tasks 10 * and 21 *. Further, the idle clock is not generated as in the operation example of FIG.

  Further, comparing the operation examples of FIGS. 6 and 7 with the operation examples of FIGS. 9 and 10, the ratio of clocks allocated to the access dedicated thread is higher in the operation examples of FIGS. This shows a state in which the clock allocation ratio is appropriately set for an access that requires clock allocation for writing or the like and an access that does not. Usually, the task related to the access process knows whether or not a large number of clock allocations are required in the access process to be executed. Therefore, as described above, the control device 40 starts from the thread that performs the access process proxy request. It is preferable that the clock allocation ratio is notified.

[Summary]
According to the multithread processing device 1 of the present embodiment described above, when performing access processing to the specific shared access target 50, the access dedicated thread #k that performs access processing to the specific shared access target 50 is accessed. In order to request processing proxy, the thread that has requested access processing proxy can perform other general processing until the access processing ends. As a result, the processing efficiency can be improved.

  In addition, since the execution time allocation ratio for the plurality of threads # 1... And the access dedicated thread #k can be changed, a plurality of access processes requested for the substitution are performed depending on how much execution time is required. The allocation ratio of the execution time to the thread # 1... And the access dedicated thread #k can be appropriately determined.

  Furthermore, since the determination of the allocation ratio is made by the thread that performs the proxy process that best knows how much execution time the access process requested for the proxy requires, the allocation ratio of the execution time is It can be determined more appropriately.

  The best mode for carrying out the present invention has been described above with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. And substitutions can be added.

DESCRIPTION OF SYMBOLS 1 Multithread processing apparatus 10 Program memory 15 Instruction fetch bus 20 Instruction fetch unit 22 # 1-22 # n Instruction buffer 24 Instruction decoder 26 Instruction issuing part 28 # 1-28 # n Register 30 Calculator 32 LSU
40 Control device 50 Specific shared access target 55 Data bus # 1, # 2, #k thread

Claims (4)

A multi-thread processing device in which hardware multi-threading processing is performed by a plurality of threads,
When the plurality of threads perform an access process to a specific shared access target, a proxy thread that performs the access process to the specific shared access target is delegated to the specific shared access target. It is characterized by requesting,
Multi-thread processing unit. The multi-thread processing apparatus according to claim 1,
The plurality of threads, when requesting the dedicated thread to perform access processing for the specific shared access target, if the dedicated thread is not activated, instructs the dedicated thread to start and the access Adding a task related to the proxy of the process, and adding the task related to the proxy of the access process when the dedicated thread is activated,
Multi-thread processing unit. The multi-thread processing apparatus according to claim 1 or 2,
The allocation ratio of the execution time to the plurality of threads and the dedicated thread can be changed,
Multi-thread processing unit. The multi-thread processing apparatus according to claim 3,
The change in the execution time allocation ratio is performed by a thread that requests substitution of access processing to the specific shared access target among the plurality of threads.
Multi-thread processing unit.

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