JPH10111491A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve deterioration in display due to a leak current of switching transistors by reversing a frame period alteratingly at a specific value or above, and also setting the frame frequency to a specific value or higher. SOLUTION: Active elements for switching pixels are constituted of multi-gate transistors for which plural pieces of single gate transistors 3, 4 of more than one size are serially connected. Then, the frame period N is reversed for AC electrification at N>2, with the frame frequency fd set as fd<60Hz. With the frame period N made larger than 2, the deviation ΔV of an effective voltage in a holding voltage can be reduced. In addition, with the frame frequency fd made larger than 60Hz, a leak time, namely a period in which polarity is reversed between the holding voltage and the voltage Vd applied to the data bus line 1, is shortened, thereby reducing the deviation ΔV of the effective voltage in the holding voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an active matrix type liquid crystal display device (Active Matrix type) provided with means for preventing deterioration of a displayed image due to reversal of the polarity of a frame.
e Liquid Crystal Display)
It is about.

[0002]

2. Description of the Related Art Conventionally, liquid crystal display devices have been used for OA terminals, projectors, etc. because of their small size, light weight, and low power consumption. In particular, for a high quality liquid crystal display device, an active matrix type liquid crystal display device provided with a switching TFT for each pixel is used.

Such a conventional active matrix type liquid crystal display device will be described with reference to FIGS. 9 and 10. FIG. FIG. 9A shows a schematic configuration of a conventional active matrix type liquid crystal display device. Gate bus lines (scanning bus lines) 41 provided in a mesh shape so as to be orthogonal to each other. And a data bus line (drain bus line) 42, a pixel 43 composed of a TFT and a pixel capacitor is arranged, one end of the pixel capacitor of each pixel is connected to the source electrode of the TFT, and the other end is connected to the common electrode. Connection and apply a common voltage V _com .

[0004] In each gate bus line 41, from the scan driver sequentially scanning signal V _g1, V _g2, applying a · · · V _gn, whereas, the respective data bus line 42, from the data driver sequentially Image display signals V _d1 , V _d2 ,... V _dm
, _Vc11 , _Vc12 ,... _Vcnm are applied to one end of the pixel electrode of each pixel 43, respectively.
Depending on the values of V _c11 , V _{c12 ,.}
A display of black lightness is obtained.

FIG. 9B shows a potential relationship between a black level and a white level in a normally white mode liquid crystal display device.
When the gate bus line is not selected, the TFT that constitutes the pixel
Is sufficiently turned off, the black level V _b− is set higher than the potential V _{go ff} of the scanning signal at the time of off.

FIG. 10 is an explanatory diagram of driving waveforms in a conventional active matrix type liquid crystal display device. A very common frame frequency _fd is 60 Hz (one frame period フ レ ー ム 16.7 m).
s) shows an example in which frame inversion is performed, that is, AC conversion is performed in a two-frame cycle, and DF (AC conversion inversion control signal) in the figure repeats +/- for each frame.

The scanning signal applied to each gate bus line is such that a pulse signal having a voltage of V _gon and a pulse width of one horizontal period (1H) is applied in a phase sequentially from V _{g1 to} V _gn. Is controlled.

[0008] For the sake of simplicity, each pixel potential will be described for the pixel in the m-th column. The voltage V _m applied to the m-th data bus line is V V in one frame cycle. _This shows a case of black display in which _{b +} and _Vb- are repeated.

In this case, the pixel potential V _c1m of the first row rises to V _{b +} with the application of the scanning signal V _g1 , and falls to V _b- with the application of the scanning signal of the second frame. the pixel potential V _cnm rise to V _{b +} with application of the scan signal V _gn, will be fall in V _b-with the application of the second frame of the scanning signal is repeated such a vibration.

[0010]

However, in such an active matrix type liquid crystal display device, the magnitude of the off-leak current of the pixel transistor in the non-scanning selection period depends on the potential difference between the source and the drain, and the potential difference is large. The larger the value is, the larger the off-leak current is.

Accordingly, during the period from writing to write again in the next frame, the pixel polarity of the voltage V _dm applied to the holding voltage and the data bus line is almost the same, i.e., the voltage of V _C1M is applied In the pixel, almost no leak occurs, the written voltage _Vc1m is maintained, and display deterioration does not occur.

On the other hand, between the writing and the rewriting in the next frame, the polarity of the holding voltage and the voltage _Vdm applied to the data bus line are almost opposite, and the potential difference between the source and the drain becomes large. That is, in a pixel to which a voltage of V _cnm is applied, a large leak occurs, and the written voltage V _c1m is greatly shifted by ΔV, so that the display is significantly deteriorated.

Further, in this conventional active matrix type liquid crystal display device, since all frames are of a polarity-changed frame in which the polarity is inverted with respect to the previous frame, a frame inversion method in which two frames are exchanged is used. There is also a problem that the effective voltage of the pixel holding voltage is greatly shifted toward the last pixel.

Accordingly, an object of the present invention is to improve display degradation caused by leakage current of a switching transistor in an active matrix type liquid crystal display device.

[0015]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. 1 (a) to 1 (c) (1) According to the present invention, in the liquid crystal display device, the frame period N is inverted with AC>N> 2, and the frame frequency f _d is f _d > 60 Hz. It is characterized by.

As described above, the frame period N is defined as N =
By making it larger than 2, V _cnmIn a big leak
Can reduce the frequency of polarity change frames
As a result, the deviation ΔV of the effective voltage of the holding voltage is reduced.
Can be eliminated.

Further, the frame frequency f _d is changed from the conventional f _d
= By greater than 60 Hz, the time to leakage, i.e., can be the polarity of the voltage V _d applied to the holding voltage and the data bus line 1 is shorter periods are reversed,
Since the refresh operation can be performed frequently, the deviation ΔV of the effective voltage of the holding voltage can be reduced.

(2) According to the present invention, in the above (1), the active element for switching the pixel is constituted by a multi-gate transistor in which a plurality of single-gate transistors 3 and 4 of one or more sizes are connected in series. Features.

As described above, by configuring the active element with a multi-transistor, particularly, a multi-gate transistor in which a plurality of single-gate transistors 3 and 4 having different sizes are connected in series, an off-leak current can be suppressed.

(3) In the present invention according to (1) or (2), the buffer for storing at least a part of the input image data and outputting the display data at the same speed as the input image data or at a different speed. A memory is provided.

As described above, by providing the buffer memory, the speed of the display data can be set arbitrarily with respect to the speed of the input image data. When image data at a normal speed is used as the input image data, By increasing the speed of the display data, the deviation Δ of the effective voltage of the holding voltage can be obtained.
V can be reduced.

(4) The present invention is characterized in that in any one of the above (1) to (3), N = 4.

When the frame period N is set to N> 4, the periodic fluctuation of the display luminance is likely to be remarkable.
= 4, the maximum effect is obtained.

(5) In the present invention, in any one of the above (1) to (4), I _off is the off current of the active element, ΔV _p is the specification value of the pixel voltage deviation, and C is the total pixel. When the capacity is used, the frame frequency f _d is set to f _d ≧ I _off / (ΔV _p × C).

In general, the specification value ΔV _p of the pixel voltage deviation is
Depending on the application of the display device, ΔV _p becomes small in order to obtain a display with a high gradation, so that the frame frequency f _d
Is determined based on the relationship of f _d ≧ I _off / (ΔV _p × C), whereby a high-quality liquid crystal display device without display deterioration can be obtained. It should be noted that the total pixel capacitance C is, when no multi-gate transistor is used,
Pixel capacitor 6, i.e., in the case of using the multi-gate transistor provided C _cell. Therefore, the element holding capacitor 5, the sum of the element holding capacitor 5 and the pixel capacitor 6, i.e., the C _h + C _cell.

(6) Further, according to the present invention, in any one of the above (1) to (4), the frame frequency f _d is set to 1
It is characterized in that 00 Hz ≦ f _d ≦ 150 Hz.

As a specific value of the frame frequency f _d , 100 Hz ≦ f _d ≦ 150 Hz is appropriate.

(7) The present invention is characterized in that in any one of the above (1) to (4), the frame frequency f _d is set to twice the frame frequency of the input image data.

[0029] A specific value for such a frame frequency f _d, is suitably twice the frame frequency of the input image data, when the frame frequency as a normal input image data is 60Hz includes a 120Hz Become.

(8) The present invention is characterized in that in the liquid crystal display device, the active element is constituted by a multi-gate transistor in which a plurality of single-gate transistors 3 and 4 having different sizes are connected in series.

As described above, by configuring the active element with a multi-gate transistor in which a plurality of single-gate transistors 3 and 4 having different sizes are connected in series, the potential difference applied between the source and the drain can be reduced. it can.

(9) The present invention is characterized in that in any one of the above (2) to (8), the size of the single gate transistors 3 and 4 is increased on the side closer to the data bus line 1. .

Since the off-leak current of the single-gate transistors 3 and 4 depends on the size, the size of the single-gate transistor 4 connected to the pixel electrode, that is, the channel width needs to be reduced. Needs to have a larger current capacity, so that the size of the single gate transistor 3 must be increased.

(10) Further, according to the present invention, in any one of the above (2) to (9), the channel regions of the plurality of single-gate transistors 3 and 4 constituting the multi-gate transistor are divided into a plurality of gate bus lines 2. The semiconductor device is characterized by being constituted by a single semiconductor layer meandering crosswise.

By forming a plurality of single-gate transistors 3 and 4 with such a single semiconductor layer, the area occupied by the multi-gate transistors can be reduced and the overall configuration can be miniaturized.

(11) According to the present invention, in any one of the above (2) to (10), the element holding capacitor 5 is connected to at least one of the nodes connecting the single gate transistors 3 and 4 to each other. In addition, the other end of the element holding capacitor 5 is connected to a predetermined potential.

As described above, by providing the element holding capacitor 5, the potential difference applied between the source and the drain can be further reduced, so that the leak current is reduced and the display deterioration is further improved.

(12) In the present invention, in the above (11), one electrode constituting the element holding capacitor 5 is formed of the same conductive layer as the data bus line 1 and the other electrode is an auxiliary capacitor electrode. It is characterized by comprising.

[0039] Thus, by constituting the other electrode constituting the element holding capacitor 5 with an auxiliary capacitor electrode (C _s bus line), since the element storage capacitor 5 does not constitute a unique light-shielding portion, the aperture ratio And a bright liquid crystal display device with high brightness can be realized.

(13) The present invention is characterized in that, in the above (11), the element holding capacitor 5 is constituted by a gate capacitance of a transistor to which a predetermined bias is applied.

Such an element holding capacitor 5 may be constituted by a gate capacitance of a transistor to which a predetermined bias is applied.

(14) The present invention is characterized in that, in the above (13), the gate electrode of the transistor constituting the element holding capacitor 5 is constituted by an auxiliary capacitance electrode.

[0043] Thus, by forming the gate electrode of the transistor included in the element storage capacitor 5 by the auxiliary capacitance electrode (C _s bus line), since the element storage capacitor 5 does not constitute a unique light-shielding portion, the aperture A highly efficient and bright liquid crystal display device can be realized, and a unique manufacturing process for forming the element holding capacitor 5 is not required.

(15) Further, according to the present invention, in any one of the above (1) to (14), at least a part of the drive circuit for driving the pixel is integrated on the substrate integrally with the active element. Features.

In an active matrix type liquid crystal display device in which a driving circuit for driving a pixel is integrated, it is necessary to increase the driving capability in order to compensate for the low carrier mobility of polycrystalline silicon. Although it is necessary to increase the on-current, the off-current, that is,
The configuration of the present invention is particularly effective in an active matrix type liquid crystal display device integrated with a drive circuit, because the off-leak current also increases.

[0046]

FIG. 2 shows a first embodiment of the present invention.
This will be described with reference to FIG. FIG. 2A is a diagram showing a schematic planar structure of a pixel, and FIG.
FIG. 3A is a diagram showing a cross-sectional structure in the vicinity of the element holding capacitor along the alternate long and short dash line in FIG. 3A, and FIG.
3B is an enlarged view of the TFT section shown in FIG. 3, and FIG. 3B is a diagram showing an equivalent circuit of the pixel shown in FIG.

Referring to FIGS. 2A and 2B, a meandering polycrystalline silicon film 12 is formed on a glass substrate 11 serving as a TFT substrate by depositing and patterning a polycrystalline silicon film over the entire surface. Next, an SiO ₂ film or the like is provided on the entire surface to form the gate insulating film 13.

Next, a conductive layer made of Al or the like is deposited,
By patterning, a gate bus line 14 crossing the meandering portion of the polycrystalline silicon film 12 is formed,
Next, after depositing a first interlayer insulating film 15 made of a SiO ₂ film or the like, contact holes 16 and 19 are formed, and then a conductive layer made of Al or the like is deposited and patterned to be connected to the contact hole 16. The data bus line 17 and the element holding capacitance electrode 18 connected to the contact hole 19 are formed.

[0049] Next, after depositing a second interlayer insulating film 20 made of SiO ₂ film or the like, is deposited a conductive film made of Al or the like, the C _s bus line 21 for forming an auxiliary capacitor by patterning After the third interlayer insulating film 22 made of a SiO ₂ film or the like is deposited again, a transparent conductive film made of ITO or the like is deposited and patterned to form the pixel electrode 23,
The basic pixel configuration is completed.

In this case, peripheral circuits such as a data driver and a scanning driver are also formed by TFTs using a polycrystalline silicon film around a display section composed of a pixel matrix. Display device.

Referring to FIG. 3A, FIG. 3A shows the polycrystalline silicon film 1 shown in FIG.
2 at a position where the polycrystalline silicon film 12 indicated by a dashed circle crosses the gate bus line 14, two series-connected first TFTs 24 and second TFTs.
25 are formed.

In this case, the line width of the gate bus line is made constant, that is, the channel length L is made constant, and the line width of the polysilicon film 12 is changed, that is, the channel widths W ₁ and W _{2 are changed.} By changing the first TFT 2
The driving capability of the fourth TFT 25 is different from that of the second TFT 25.

In this case, the off-leakage current of the TFT depends on the on-state current, that is, the driving capability.
_By connecting the second TFT 25 having a small size of 2 to the pixel electrode, the leak current from the pixel electrode is reduced, and the deviation of the effective voltage of the holding voltage is also reduced.

Also, the first TFT 24 in the former stage is naturally required to have a higher driving capability than the second TFT 25 in the latter stage. Therefore, when the channel length L is fixed, the channel of the first TFT 24 is width W ₁ and the ratio of the channel width W ₂ of the second TFT 25, W ₁ / W ₂ is (C _h + C _cell) /
Although it depends on the value of C _cell , in the embodiment, 2 /
It is set to 1.

FIG. 3 (b) is a diagram showing an equivalent circuit of the pixel shown in FIG. 2 (a). A first TFT 24 and a second TFT 25 are connected in series to form a multi-gate transistor. The multi-gate transistor switches the pixel capacitance 27 as an active element, and the element holding capacitance electrode 18 and C _s are connected to the nodes of the first TFT 24 and the second TFT 25.
Element holding capacitor 26 formed from the bus line 21. is connected to the C _s bus line 21 a predetermined potential V _bias, such as V _com is applied.

In this case, when the electric charge is accumulated in the pixel capacitance 27, the electric charge is also accumulated in the element holding capacitance 26.
When the scanning signal is off, almost no reverse voltage is applied between the source and the drain of the second TFT 25, and almost no off-leak current flows, thereby preventing display degradation.

The charge / discharge current i from the pixel capacitor 27
_Since the charge / discharge current i _h from the _cell and the element holding capacitor 26 flows through the first TFT 24 having a large driving ability, the second charge / discharge current i _h
Even if the size of the TFT 25 is reduced, no problem occurs in the driving capability of the pixel.

The capacitance C of the element holding capacitor 26 in this case is
_h may be any size of about suppressing off leak of the second TFT 25, 0 of the capacitance C _cell of the pixel capacitor 27.
The capacity may be 1 to 1.0 times, and in the embodiment, it is 0.3 times.

[0059] The auxiliary capacitance C _s in this case, C _s bus line 21 and the pixel electrode 2 through the third interlayer insulating film 22
3 and the element holding capacitor 26 is also C
_{Since the s} bus line 21 is formed so as to overlap with the _s bus line 21, the space for forming the element holding capacitor 26 does not form a unique light-shielding portion. it can.

As described above, in the first embodiment of the present invention, a multi-gate transistor in which single-gate TFTs having different sizes are connected in series is used as an active element, and an element holding capacitor is connected. Therefore, the off-leak current can be reduced.

Further, since the multi-gate transistor is formed of a single polycrystalline silicon film 12 meandering across the gate bus line 14 a plurality of times, the space for providing an active element can be reduced. Even if a multi-gate transistor is used, the degree of integration is not reduced.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 4A is a diagram showing a schematic planar structure of a pixel, and FIG.
FIG. 5A is a diagram showing a cross-sectional structure near the element holding capacitor along the alternate long and short dash line in FIG. 5A, and FIG.
5B is an enlarged view of the TFT section in FIG. 5, and FIG. 5B is a diagram showing an equivalent circuit of the pixel shown in FIG.

Referring to FIGS. 4A and 4B, a polycrystalline silicon film is deposited on the entire surface of a glass substrate 11 serving as a TFT substrate and patterned in the same manner as in the first embodiment. To form a meandering polycrystalline silicon film 12, and then provide an SiO ₂ film or the like on the entire surface to form a gate insulating film 13.

Next, a conductive layer made of Al or the like is deposited,
A gate bus line 14 that crosses the meandering portion of the polycrystalline silicon film 12 by patterning;
The C _s bus line 28 so as to partially cover is formed of, then, after the deposition of the first interlayer insulating film 15 made of SiO ₂ film or the like, to form a contact hole 16, and then, Al
A data bus line 17 connected to the contact hole 16 is formed by depositing and patterning a conductive layer made of the same.

Next, after depositing a second interlayer insulating film 20 made of an SiO ₂ film or the like, a transparent conductive film made of ITO or the like is deposited and patterned to form a pixel electrode 23, thereby forming a basic pixel electrode. The configuration is completed.

Also in this case, peripheral circuits such as a data driver and a scanning driver are also formed by TFTs using a polycrystalline silicon film around a display section composed of a pixel matrix, so that a driving circuit integrated type active matrix type It is a liquid crystal display device.

Referring to FIG. 5A, FIG. 5A shows the polycrystalline silicon film 1 shown in FIG.
2 at a position where the polycrystalline silicon film 12 indicated by a dashed circle crosses the gate bus line 14, two series-connected first TFTs 24 and second TFTs.
25, and the polycrystalline silicon film 12 and C
_In the overlapping portion with the _s bus line 28, the third TFT 2
9 is formed.

Also in this case, the line width of the gate bus line is made constant and the line width of the polycrystalline silicon film 12 is changed, so that the driving capability of the first TFT 24 and that of the second TFT 25 are made different. , the channel width W ₁ of the first TFT24 second TFT25 ratio of the channel width W ₂ of, W
₁ / W ₂ depends on the value of (C _ht + C _cell ) / C _cell , where C _ht is the gate capacitance of the third FET 29.
For example, a 2/1, by connecting the small second TFT25 size of the channel width W ₂ to the pixel electrode, the leakage current is reduced from the pixel electrodes, displacement of the effective voltage of the holding voltage is reduced.

FIG. 5 (b) is a diagram showing an equivalent circuit of the pixel shown in FIG. 4 (a). A first TFT 24 and a second TFT 25 are connected in series to form a multi-gate transistor. configure, together with the multi-gate transistor for switching the pixel capacitor 27 as an active element, a first TFT24 between the second TFT25 the third TFT29 to the gate electrode of the C _s bus lines 28 formed the predetermined potential V _bias, such as V _com is applied to the C _s bus line 28.

In this case, by using the gate capacitance of the third TFT 29 as an element holding capacitance, as in the first embodiment, when the scanning signal is off, the second TFT 2
5, a reverse voltage is hardly applied between the source and the drain, and almost no off-leak current flows, so that deterioration of display can be prevented.

In this case, the gate capacitance of the third TFT 29 may be large enough to suppress the off-leakage of the second TFT 25, and is 0.1% of the capacitance C _cell of the pixel capacitance 27.
The capacity may be up to 1.0 times, and in the embodiment, it is 0.3 times.

In this case, the storage capacitor C _s is constituted by the overlap of the C _s bus line 28 and the pixel electrode 23 via the first interlayer insulating film 15 and the second interlayer insulating film 20 and the third capacitor C _s . since TFT29 also utilizes C _s bus line 28, since the space for forming the third TFT29 do not form their own light-shielding portion, in a conventional manner with high aperture ratio, to realize a bright liquid crystal display device be able to.

In the second embodiment,
As with conventional, since the form C _s bus line 28 by utilizing the process of forming the gate bus line 14, becomes unnecessary a unique process for forming an element holding capacity than the first embodiment Also, the manufacturing process is simplified.

As described above, also in the second embodiment of the present invention, the active element uses a multi-gate transistor in which single-gate TFTs having different sizes are connected in series, and the gate capacitance of the third TFT is reduced. Since the used element holding capacitor is connected, the off-leak current can be reduced.

Next, with reference to FIGS suppress leak current by increasing the frame frequency f _d, illustrating a third embodiment of the present invention. FIG. 6 is a diagram showing a schematic configuration of an active matrix type liquid crystal display device according to a third embodiment of the present invention, in which an image generating means 31 comprising a personal computer or the like, and a synchronization signal from the image generating means 31 are shown. Sync ₀ and input image data DA ₀ are written at a predetermined timing, and read at a predetermined timing. Buffer memory means 32 composed of a high-speed memory element or the like, and input image data written in buffer memory means 32 synchronizing signal generating means 33 for generating a synchronization signal indicating the read timing, etc., the latch means 34 to adjust the timing of the read-out image data from the buffer memory means 32, and the display image data DA _d and synchronization signals Syn
accordance c _d performs display and a drive circuit-integrated liquid crystal display device 35.

FIG. 7 is a diagram showing a driving method of the active matrix type liquid crystal display device shown in FIG.
The dot clock signal _DCLK is generated by the horizontal synchronizing signal _Hsync among the synchronizing signals from 1 and the first half of the dot clock signal _DCLK is a writing period R, and the latter half is a reading period W, and the timing of R / W Set.

A write control signal W _CNTL is generated based on the write period W of the dot clock signal D _CLK , and the frame frequency f ₀ = 60H is generated by the write control signal W _CNTL .
write to the buffer memory unit 32 the input image data DA ₀ sent by z as write image data W _DATA. Note that the write image data W _DATA in this case accumulates all of the input image data DA ₀ or a part of one frame or the like.

[0078] Then, based on the synchronizing signal from the synchronizing signal generating means 33, the dot clock signal D to the reading period R of _CLK to generate a read control signal R _CNTL for performing read twice out operation, the read control signal R the written image data W _dATA transiently accumulated by _CNTL read at twice the frequency, to form a read image data R _dATA.

[0079] Then, in the latch means 34, the synchronization signal in synchronization with the first synchronizing signal L _CK1 from the generation means 33, the read-out image data R _DATA latched image data L _DATA1
After conversion into, based on the second synchronization signal L _CK2, to form a display data DA _d in which the dot data at regular intervals,
The data is input to the driving circuit integrated type liquid crystal display device 35.

[0080] Figure 8 reference 8 is a diagram showing driving waveforms when driving the liquid crystal display device by the display data DA _d obtained as a result of FIG. 7, in this case, it is shown in DF, 1 frame period f _d is the 120 Hz (8.3 ms), conventional 60Hz
Is doubled, the frame is inverted in units of two frames, that is, alternating is performed in a cycle of four frames.

[0081] Voltage applied to the gate bus line and the drain bus line in this case is basically the same as the conventional, the scanning signal V _g1 ··· V _gn to sequentially timing deviates to each gate bus line is applied, in synchronization with the scanning signal V _g1 ··· V _gn, from the image data signal V _dm applied to each drain bus lines, the pixel voltage _V c1m ··· V _cnm applied to each pixel formation Is done. Note that this case shows a case of black display in the normally white mode.

In the third embodiment, since the frame is inverted every two frames, the frequency of the polarity change frame is reduced. That is, since the reverse bias is not applied for one frame, the holding due to the off-leak current is maintained. The deviation ΔV of the effective voltage is much smaller than in the prior art.

[0083] Also, since the frame frequency f _d to the conventional two-fold, the time itself reverse bias is applied, ie, the time itself which leaks is reduced, the off-leakage current is reduced, the holding voltage with it Of the effective voltage becomes significantly smaller than in the prior art.

Note that the AC inversion cycle N in the above embodiment is 4, that is, 4 frames cycle AC.
= 4 is optimal because it does not feel the periodic fluctuation of the display luminance, but is not limited to N = 4.
It is sufficient if N> 2, which is larger.

As the frame frequency f _d , 120 Hz which is twice the conventional frame frequency f ₀ of the input image data DA ₀ is employed, but the frame frequency is not limited to 120 Hz and may be 60 Hz or more. , Especially 100
A range of up to 150 Hz is preferred.

When the frame frequency f _d is I _off is the off current of the active element, ΔV _p is the specification value of the pixel voltage deviation, and C is the total pixel capacitance, f _d ≧ I _off / (ΔV _p × C) It is determined based on the relationship.

This generally corresponds to the specification value Δ of the pixel voltage deviation.
V _p , that is, the allowable value differs depending on the use of the display device. This is because ΔV _p becomes small in order to obtain a high-gradation display, and the frame frequency f _d is changed to f _d ≧ I _off /
By determining based on the relationship of (ΔV _p × C), a high-quality liquid crystal display device with no display deterioration according to the application can be obtained.

When the multi-gate transistor is not used, the total pixel capacitance C is the pixel capacitance, that is, C _cell
When a multi-gate transistor provided with an element holding capacitor as in the first or second embodiment is used, the sum of the element holding capacity and the pixel capacity, that is, _Ch +
C _cell .

Although the third embodiment is established irrespective of the structure of the active element, the off-leak current can be further reduced by applying the third embodiment in combination with the first or second embodiment. Can be reduced.

In the description of the first and second embodiments, two multi-gate transistors are configured by connecting two single-gate transistors in series. However, two or more single-gate transistors are connected in series. The configuration may be made as follows.

Each single gate transistor has
The polycrystalline silicon film is formed in a meandering manner, and the portion overlapping the gate bus line in the meandering portion is used as a channel region. However, the present invention is not necessarily limited to such a form. May be formed.

[0092] Further, the element storage capacitor does not necessarily need to use the C _s bus lines, independently, the gate bus line, or those may be configured by a conductive film of C _s bus lines in the same layer .

In each of the embodiments described above, the liquid crystal display device integrated with a driving circuit is described. However, in the case of the integrated driving circuit type, the polycrystalline silicon TFT forming the driving circuit is used. In order to compensate for the low mobility of the above, the on-current is configured to be large, but this also inevitably increases the off-leak current, and the deterioration of the display due to the off-leak current becomes remarkable. The present invention is not limited to a liquid crystal display device integrated with a drive circuit, but also applies to a liquid crystal display device of a separate drive circuit type using an amorphous silicon TFT as an active element.

[0094]

According to the present invention, the active element is constituted by a multi-gate transistor in which single-gate transistors having different sizes are connected in series, so that the leak current can be reduced. By making the inversion period N greater than 2 and the frame frequency f _d greater than 60 Hz,
A leak current can be reduced, and a liquid crystal display device of high display quality with little display degradation can be realized.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of an equivalent circuit according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of an equivalent circuit according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a schematic configuration of a third embodiment of the present invention.

FIG. 7 is an explanatory diagram of a driving method according to a third embodiment of the present invention.

FIG. 8 is an explanatory diagram of driving waveforms according to a third embodiment of the present invention.

FIG. 9 is an explanatory diagram of a conventional active matrix type liquid crystal display device.

FIG. 10 is an explanatory diagram of driving waveforms in a conventional active matrix type liquid crystal display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Data bus line 2 Gate bus line 3 Single gate transistor 4 Single gate transistor 5 Element holding capacity 6 Pixel capacity 11 Glass substrate 12 Polycrystalline silicon film 13 Gate insulating film 14 Gate bus line 15 First interlayer insulating film 16 Contact hole 17 Data bus line 18 element storage capacitor electrodes 19 contact hole 20 second interlayer insulating film 21 C _s bus line 22 third interlayer insulating film 23 pixel electrode 24 first TFT 25 second TFT 26 element holding capacitor 27 pixel capacitor 28 C _s Bus line 29 Third TFT 31 Pixel generating means 32 Buffer memory means 33 Synchronous signal generating means 34 Latch means 35 Drive circuit integrated liquid crystal display device 41 Gate bus line 42 Data bus line 43 Pixel

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akira Yamamoto 4-1-1 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Mitsuharu Nakazawa 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Inside Fujitsu Limited

Claims (15)

[Claims] 1. A liquid crystal display device in which a frame period N is AC-inverted when N> 2, and a frame frequency f _d is f _d > 60 Hz. 2. The liquid crystal device according to claim 1, wherein the active element for switching pixels of the liquid crystal display device is constituted by a multi-gate transistor in which a plurality of single-gate transistors of one or more types are connected in series. Display device. 3. The liquid crystal display device according to claim 1, further comprising a buffer memory for storing at least a part of the input image data and outputting the display data at the same speed as or a different speed from the input image data. 3. The liquid crystal display device according to 1 or 2. 4. The liquid crystal display device according to claim 1, wherein the frame period N is set to N = 4. 5. When the frame frequency f _d is I _off is the off current of the active element, ΔV _p is a specification value of a pixel voltage deviation, and C is a total pixel capacitance, f _d ≧ I _off / (ΔV The liquid crystal display device according to claim 1, wherein _p × C). 6. The frame frequency f _d is set to 100 Hz.
5. The liquid crystal display device according to claim 1, wherein ≦ f _d ≦ 150 Hz. 6. 7. The liquid crystal display device according to claim 1, wherein the frame frequency f _d is set to twice the frame frequency of the input image data. 8. A liquid crystal display device wherein an active element for switching a pixel is constituted by a multi-gate transistor in which a plurality of single-gate transistors having different sizes are connected in series. 9. The liquid crystal display device according to claim 2, wherein the size of the single gate transistor is larger on the side closer to the data bus line. 10. The multi-gate transistor according to claim 2, wherein the channel region of each of the plurality of single-gate transistors comprises a single semiconductor layer meandering across the gate bus line a plurality of times. The liquid crystal display device according to any one of the above. 11. An element holding capacitor is connected to at least one of the nodes connecting the single-gate transistors, and the other end of the element holding capacitor is connected to a predetermined potential. Item 11. The liquid crystal display device according to any one of items 2 to 10. 12. The liquid crystal according to claim 11, wherein one of the electrodes forming the element holding capacitor is formed of the same conductive layer as the data bus line, and the other electrode is formed of an auxiliary capacitor electrode. Display device. 13. The liquid crystal display device according to claim 11, wherein said element holding capacitance is constituted by a gate capacitance of a transistor to which a predetermined bias is applied. 14. The liquid crystal display device according to claim 13, wherein a gate electrode of the transistor forming the element holding capacitor is formed by an auxiliary capacitor electrode. 15. The liquid crystal display device according to claim 1, wherein at least a part of a driving circuit for driving a pixel of the liquid crystal display device is integrated on a substrate together with an active element for switching the pixel. 2. The liquid crystal display device according to claim 1.