JPH1011117A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a programmable controller capable of quickly executing respective instructions related to a contact (b) even in a programmable controller utilizing a general microprocessor. SOLUTION: The programmable controller is provided with a data output circuit 500 for outputting the value of data indicating the state of a contact (a) as it is when the data are read out from a memory and inverting the value of data indicating the state of the contact (b) and outputting the inverted value when the data are read out from the memory. At the time of executing an instruction for the contact (a) selected as an object to be processed in a sequence program, the data read out from the memory are used as they are, and in the case of executing an instruction for the contact (b) selected an object to be processed, the data read out from the memory are inverted by the circuit 500 and the inverted data are used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a programmable controller, and more particularly to a programmable controller which uses a general-purpose microprocessor and can execute a command concerning a contact b (normally closed contact) among contacts to be controlled at a high speed.

[0002]

2. Description of the Related Art When a sequence is controlled by a programmable controller, a ladder for arranging symbols such as switches and coils, graphics representing functions, related data, labels, and the like in an order along the sequence in left and right buses. A method of designing with a ladder diagram language using diagrams is widely adopted, and application programs for design support are also commercially available.

FIG. 1 is a schematic diagram showing typical instruction words used in such a ladder program, and shows the names of instructions, symbols, mnemonics, and functions in the ladder program.

[0004] Of these instruction words, for example, an instruction indicated by a mnemonic "LD" is a load instruction, and a
Contact, ie normally open contact (NO: Normal Open contact in Fig. 1)
Is the instruction to connect The instruction indicated by the mnemonic "LDB" is a load bar instruction, and is an instruction for connecting the b contact, that is, a normally closed contact (NC: Normal Close contact in FIG. 1) to the bus.

[0005] The instruction indicated by the mnemonic "AND" is an AND instruction, which is an instruction for connecting the a contact in series. The command indicated by the mnemonic "ANB" is an AND bar command, which is a command for connecting the b contacts in series.

The instruction indicated by the mnemonic "OR" is an OR instruction, and is an instruction to connect the NO contacts in parallel. The instruction indicated by the mnemonic "ORB" is an OR instruction, and b
It is a command to connect the contacts, that is, the normally closed contacts in parallel.

By using a personal computer on which the above-described design support application program is installed, a ladder program can be designed by combining mnemonics of various instructions as described above. Are arranged in the left and right buses in the order according to the sequence of the ladder program to create a ladder diagram.

A ladder program designed as described above is executed by a programmable controller (Programma
ble Logic Controller (PLC) is used, and there are a case using a dedicated microprocessor and a case using a general-purpose microprocessor. The former is designed as a dedicated microprocessor for processing various instructions of a ladder program, while the latter processes various instructions of a ladder program by a combination of instructions included in a general-purpose microprocessor. Therefore, when the former dedicated hardware is used, the ladder program can be processed at high speed. However, the latter differs depending on the instruction processing speed of the general-purpose microprocessor used and the combination of instructions used to process each instruction of the ladder program. In any case, the processing speed is lower than the former. can not deny.

Each of the load, AND, and OR instructions of the various instruction words shown in FIG. 1 is executed by the following instructions in a general-purpose microprocessor.

Load (LD): mem → reg AND (AND): reg ∧ mem → reg OR (OR): reg ∨ mem → reg

Specifically, the load instruction of the ladder program is a general-purpose microprocessor which stores data indicating the state of the contact a stored in the memory (mem) in a register (reg).
And stored as an instruction. In a general purpose microprocessor, the AND instruction of the ladder program performs an AND operation on data indicating the state of a certain contact already held in a register (reg) and data indicating the state of a certain contact stored in a memory (mem). (Logical AND operation: ∧) and the result is stored in the original register (reg). In the OR instruction of the ladder program, a general-purpose microprocessor performs an OR operation on data indicating the state of a certain contact already held in a register (reg) and data indicating the state of a certain contact stored in a memory (mem). (OR operation: ∨) and the result is stored in the original register (reg).

Therefore, a load instruction, an AND instruction, and an OR instruction, which are instructions relating to the contact a of the ladder program, are all processed by one instruction in the general-purpose microprocessor. However, for example, among the instructions of the ladder program shown in FIG. 1 above, each instruction relating to the contact b, that is, the load bar instruction indicated by the mnemonic "LDB" and the mnemonic "AN"
A general-purpose microprocessor processes an AND bar instruction indicated by "B" and an OR bar instruction indicated by mnemonic "ORB". In the following description, "#" indicates an inverted (bar) symbol. ing.

Load bar (LDB): mem → reg, # reg → r
eg And bar (ANB): # reg → reg, reg ∨ mem → reg, #r
eg → reg ORB (ORB): # reg → reg, reg∧ mem → reg, #reg
→ reg

More specifically, the load bar instruction of the ladder program includes, in a general-purpose microprocessor, an instruction for transferring data indicating the state of a certain b-contact stored in a memory (mem) to a register (reg); This is realized by two instructions: an instruction to invert (#reg) the data transferred to (reg) and store it in the original register (reg).

The ladder program and bar instruction is an instruction for inverting (#reg) data indicating the state of a certain contact already held in a register in a general-purpose microprocessor and storing the result in the original register (reg). , The inverted data and memory (mem) stored in the register (reg)
An instruction to perform an OR operation (logical addition operation: を) on the data indicating the state of the contact b stored in the register as it is and store the result in the original register (reg), and the instruction stored in the register Invert the data (#reg) to the original register (re
g) is realized by three instructions including the instruction stored in.

In a general purpose microprocessor, an OR-bar instruction of a ladder program is an instruction for inverting (#reg) data indicating the state of a certain contact held in a register and storing the result in the original register (reg); That register (re
g) flipped data and memory stored in (mem)
An instruction to perform an AND operation (logical AND operation: ∧) on the data indicating the state of the contact b stored in the register and store the result in the original register (reg), and the data stored in the register Is inverted (#reg) and the original register (re
g) is realized by three instructions including the instruction stored in.

[0017]

As described above, the load bar instruction relating to the contact b of the ladder program is processed by two instructions in the general-purpose microprocessor, and the AND-bar instruction and the OR-bar instruction of the ladder program are processed by three instructions in the general-purpose microprocessor. You. In other words, in a programmable controller using a dedicated microprocessor for processing a ladder program, the load (LD), AND (AND), and OR (OR) instructions relating to the a-contact also require the load bar (LDB) relating to the b-contact. ), And bar (ANB), or bar (ORB)
Can be executed in basically the same processing time, but in a programmable controller using a general-purpose microprocessor, the processing time of each instruction related to the contact b is a
There is a problem that the processing time is required to be about two to three times as long as that for the contact.

However, a microprocessor configured as a dedicated programmable controller is expensive,
On the other hand, on the other hand, there is an economical problem that a general-purpose microprocessor is inexpensive, so that there is a great demand for a programmable controller using a general-purpose microprocessor. Therefore, even in a programmable controller using a general-purpose microprocessor, b
It is desired to shorten the processing time of each instruction related to a contact.

The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a programmable controller using a general-purpose microprocessor, which can execute each instruction related to the contact b at a higher speed. .

[0020]

According to the present invention, a programmable controller according to the present invention sets a non-conducting state of an a contact and a non-conducting state of a b contact to predetermined values for a non-conducting state of an a contact and a conducting state of a b contact in sequence control. A general-purpose microprocessor that includes a memory that stores data indicating a state that is complementary to a predetermined value, and that configures a sequence program that processes data indicating the state of each contact stored in the memory; Is a programmable controller that performs sequence control by combining and executing the instructions for use, and when data indicating the state of the contact a is read from the memory, the value is output as it is, and data indicating the state of the contact b is output. It has a data output circuit that inverts the value when it is read from the memory and outputs the inverted value. When executing the instructions of the sequence program, the data read from the memory is used as it is, and when executing the instructions of the sequence program targeting the b contact, the data read from the memory is used by the data output circuit. It is characterized in that inverted data is used.

Further, in the programmable controller according to the present invention, in addition to the above configuration, when compiling each instruction of the sequence program, the memory address included in the instruction relating to each a contact is included in the instruction relating to each b contact as it is. A memory address included in each instruction, and a data output circuit configured to decode the memory address included in each instruction. Means for outputting the value read from the memory as it is or for inverting and outputting the value.

Further, the programmable controller according to the present invention is characterized in that the non-conducting state of the contact a and the conducting state of the contact b relating to the sequence control have a predetermined value, and the conducting state of the contact a and the non-conducting state of the contact b have a predetermined value. Is a memory that stores data indicated by values complementary to each other, and when data indicating the state of the a contact is read from the memory, the value is output as it is, and data indicating the state of the b contact is read from the memory. A data output circuit for inverting and reading out the value when read out, and a general-purpose microprocessor instruction for forming a sequence program for processing data indicating the state of each contact stored in the memory as a processing target. Is a programmable controller that performs sequence control by executing the combination of the b-contact data and the b-contact data stored in the memory. By programming a general purpose microprocessor instruction to store inverted to register the data output circuit, b stored in the memory
Performs an AND operation on a load bar instruction of a sequence program that stores data indicating the state of a contact in a register, data that is obtained by inverting data of a contact b stored in a memory by a data output circuit, and data that is stored in a register. By using a general-purpose microprocessor instruction to store the data in a register, the data indicating the state of the contact b stored in the memory and the data indicating the state of a certain contact stored in the register are AND-operated. A general-purpose microprocessor instruction that performs an OR operation on an AND bar instruction of a sequence program, data obtained by inverting data of the b-contact stored in the memory by the data output circuit, and data stored in the register, and storing the result in the register By programming the b connection stored in the memory. And having a data indicating the state of a contact that is stored in the state data and register indicating the Oaba instruction sequence program that OR operation a.

According to the present invention, even in a programmable controller constituted by a general-purpose microprocessor, each instruction relating to the contact b can be executed by one corresponding instruction for the general-purpose microprocessor.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to the drawings showing the embodiments. FIG. 2 is a block diagram showing a configuration example of a system for executing a ladder program including the programmable controller according to the present invention. FIG. 2 is a block diagram showing an example of the internal configuration of a PLC (programmable controller) 20 of the present invention,
A schematic external view of the personal computer 10 for designing and loading a ladder program executed by the PLC 20 is also shown.

The personal computer 10 includes a design support application program for realizing a function of editing a ladder program as a sequence program, a function of simulating a ladder program, and a function of monitoring a simulation state, such as a magnetic disk on which the program is recorded. And the like from the recording medium D.

The personal computer 10 is connected to the PLC 20 of the present invention via a cable. A ladder program designed on the personal computer 10 conforms to an interface standard such as RS232C.
Transferred to LC20. The above-described design support application program installed in the personal computer 10 outputs to the devices 30 such as switches, valves, and sensors of the actual machine output of control signals for opening and closing switches and valves, or opening and closing of manual switches. PLC 20 by inputting a state signal, a detection signal of a sensor, or the like.
The present embodiment also provides a monitor function for periodically polling the status of the sequence control of the device 30 and displaying a change over time in the status of the device 30 such as a switch, a valve, or a sensor on a screen with a numerical value, a time chart, or the like.

The PLC 20 of the present invention basically uses a general-purpose microprocessor (MPU 202).
A serial communication interface (I / F) circuit 201 for serially transferring data to and from the personal computer 10 is provided. The ladder program transferred from the personal computer 10 via the serial communication I / F circuit 201 is stored in the RAM 204. . In addition, PLC20
Stores, in the RAM 204, data input / output to / from switches, valves, sensors, and the like via the input / output circuit 205 when the ladder program is executed, and responds to requests periodically transmitted from the personal computer 10. In response, these data stored in RAM 204 are transferred to personal computer 10 via serial communication I / F circuit 201.

The ROM 203 of the PLC 20 stores a program for converting a ladder program loaded from the personal computer 10 into an instruction system of a general-purpose microprocessor and a system program such as a compiler for converting the program into object code. RAM2
04 includes a user program such as a ladder program,
Data used for executing the system program and the user program are stored at the predetermined addresses.

The MPU 202 of the PLC 20 executes a ladder program stored in the RAM 204 according to the OS to sequence-control devices 30, such as switches, valves, and sensors, arranged in the actual machine to be controlled. The data stored in the RAM 204 is rewritten. Further, the PLC 20 outputs to the devices 30 such as switches, valves, and sensors a control signal for opening and closing the switches and valves, and inputs and outputs a state signal for opening and closing the manual switches, a detection signal of the sensor, and the like. A circuit 205 is provided.

A signal from a simple portable terminal (not shown) for programming or editing a user program such as a ladder program at the site of sequence control is wired to the serial communication I / F circuit 201 of the PLC 20. Or wirelessly. Further, it goes without saying that the connection between the personal computer 10 and the PLC 20 can be made by wire or wireless.

FIG. 3 shows the MPU 202 of the PLC 20 of the present invention.
FIG. 2 is a logic circuit diagram showing an example of the configuration of a circuit for accessing the RAM 204, that is, a data output circuit.

In FIG. 3, reference numeral 202 denotes an MPU.
, 204 indicates the RAM as described above, respectively.
The MPU 202 includes a CPU 50 as control means, a decoder 51, and inverters, gates, and AND gates indicated by reference numerals 52 to 57. The data output circuit 500 is composed of the inverter, the gate, the AND gate and the decoder 51 indicated by reference numerals 52 to 57.

An address signal ADD is supplied from the CPU 50 to the decoder 51. Also, the read / write signal R / # W from the CPU 50 receives a 2-input AND gate 5
The gate 57 is provided with a negative logic control terminal as a control signal in addition to one of the input terminals 3 and 54.

A read data inversion signal #RD from the decoder 51 is input to the other input terminal of the AND gate 53 after being inverted by the inverter 52.
The read data inversion signal #RD from the decoder 51 is input to the other input terminal of the gate 54 as it is.
The output signal of the AND gate 53 is supplied as a control signal to a control terminal of a gate 55, and the output signal of the AND gate 54 is supplied as a control signal to a control terminal of a negative logic gate (hereinafter referred to as an inversion gate) 56. I have.

When the address signal ADD is given from the CPU 50 and the value of the specific bit is "0", the decoder 51 uses the memory address specified by the address signal ADD to store the contact reference space 2 in the RAM 204.
04a and the read data inversion signal #
A low level (“0”) signal is output as RD. On the other hand, the decoder 51 outputs the address signal ADD from the CPU 50.
Is given, when the value of the specific bit is “1”, the address signal ADD is set to “0”.
The contact reference space 204a is accessed with the memory address specified by, and a high-level (“1”) signal is output as the read data inversion signal #RD. The read data inversion signal #R output from the decoder 51
D is the input terminal of the inverter 52 and AND
The other input terminal of the gate 54 is provided.

The gate 55 and the inverting gate 56 are both R
It is used when reading data from the AM 204 to the CPU 50 (read). Specifically, the gate 55 is
The read / write signal R / # W output from U50 is "
1 ", that is, the reading is instructed, and A
When the output signal of the ND gate 53 is "1", the RAM
The data signal output from the CPU 204
0, the inverting gate 56 indicates that the read / write signal R / # W output from the CPU 50 is “1”, that is, instructs reading, and the output signal of the AND gate 54 is “1”. In some cases, the data signal output from the RAM 204 is inverted and input to the CPU 50.

On the other hand, the gate 57 is connected to the RAM from the CPU 50.
It is used at the time of writing data (writing) to the data 204. Specifically, the gate 57 inputs the data signal output from the CPU 50 to the RAM 204 when the read / write signal R / # W output from the CPU 50 is “0”, that is, when the write is instructed. I do.

Therefore, when an address signal ADD having a specific bit value of "0" is input from the CPU 50 to the decoder 51, the address value is directly supplied to the contact reference space 204a of the RAM 204 to perform memory access. At this time, a read / write signal R / # W of “1” is output from the CPU 50 and input to the AND gate 53, and a read data inversion signal #RD of “0” is output from the decoder 51. ing. Since the read data inversion signal #RD from the decoder 51 is inverted by the inverter 52 and is input to one of the input terminals of the AND gates 53 and 54 and the negative logic control terminal of the gate 57, the output of the AND gate 53 is output. The signal becomes "1" and the gate 55 becomes conductive. The AND gate 54 has "
Since the read data inverted signal #RD of “0” is input,
The output signal becomes "0", and the gate 56 is maintained in a non-conductive state. Further, since the read / write signal R / # W of "1" is input to the negative logic control terminal of the gate 57, the non-conductive state is maintained. Therefore, in this case, only the gate 55 is turned on, and the data signal output from the contact reference space 204a in response to the address signal ADD is directly input to the CPU 50.

On the other hand, an address signal ADD whose specific bit value is “1” is supplied from the CPU 50 to the decoder 5.
When the address value is input to 1, the value of the specific bit is converted to "0" in the address value, and the converted value is applied to the contact reference space 204a to perform a memory access. At this time, the CPU 5
From 0, a read / write signal R / # W of "1" is output and input to one of the input terminals of the AND gates 53 and 54 and the control terminal of the gate 57, and the decoder 51 outputs "1" in this case. The read data inversion signal #RD of “1” is output. The read data inversion signal #RD from the decoder 51 is inverted by the inverter 52 and input to the AND gate 53 as a signal of “0”.
The output signal of the gate 53 becomes "0", and the gate 55 maintains the non-conductive state. Since the read data inversion signal #RD of "1" is input to the AND gate 54, the output signal thereof becomes "1" and the gate 56 becomes conductive. The gate 57 is kept in a non-conductive state because the read / write signal R / # W of "1" is inputted to its negative logic control terminal. Therefore, in this case, only the gate 56 becomes conductive, the data signal output from the contact reference space 204a corresponding to the address signal ADD is inverted, and the CPU
50 is input.

When the read / write signal R / # W indicates a data write (write), the value is "0", and the output signal of both AND gates 53 and 54 is "0". 0 ", and the gates 55 and 56 are both turned off. However, the gate 57 is rendered conductive because the read / write signal R / # W of "0" is supplied to its negative logic control terminal. Therefore, in this case, since only the gate 57 is turned on, the data signal output from the CPU 50 is input to the contact reference space 204a, and is simultaneously written to the address corresponding to the address signal ADD output from the CPU 50.

The MPU 202 executes the ladder program stored in the other space 204c of the RAM 204 according to the OS as described above, and outputs control signals and the like via the input / output circuit 205 to output switches, valves, sensors, and the like. Of the device 30 in sequence, and data input / output to / from the device 30 is stored in the contact reference space 204a.
Then, if necessary, the data stored in the contact reference space 204a is rewritten. Further, the MPU 202
These data stored in the contact reference space 204a are transferred to the personal computer 10 via the serial communication I / F circuit 201 in response to a request periodically transmitted from the personal computer 10.

By the way, the contact reference space 2 of the RAM 204
04a, as shown in FIG. 4, each contact C1, C
2, C3, C4... Are stored. Specifically, the address of the contact reference space 204a "
0000 ”indicates the state“ 1 ”of the contact C1 and the address“ 0 ”.
001 ”indicates the state“ 0 ”of the contact C2 and the address“ 00 ”.
10 ”, the state“ 1 ”of the contact C3 is stored in the address“ 001 ”.
Data indicating the open / closed state of each contact is stored in "1" such as the state "1" of the contact C4, and "0" in the data indicates that the contact is in a normal state, that is, A contact indicates a non-conducting state, a b contact indicates a conducting state, and data "1" indicates that the contact is not in a normal state, that is, a contact indicates a conducting state. The state indicates that the contact is non-conductive if the contact is b.

On the other hand, the contact reference space 204a as described above
Considering the virtual inversion contact reference space 204b in which the contents of the contact point appear to be inverted when viewed from the MPU 202 side, data indicating the state of each of the contacts C1, C2, C3, C4,. This means that the inverted data is stored. Specifically, the virtual inversion contact reference space 204b
Address "0000" of the contact C1 has the inverted state "0"
However, the address "0001" has an inverted state of the contact C2.
Data indicating the inverted state of the open / close state of each contact, such as 1 ", the inverted state" 0 "of the contact C3 at the address" 0010 ", the inverted state" 0 "of the contact C4 at the address" 0011 ", and so on. Is stored.

Therefore, the data "0" considered to be stored in the virtual inversion contact reference space 204b indicates that the contact is not in a normal state, that is, the contact is a conductive state if the contact is a. A contact b indicates a non-conducting state, and data "1" indicates that the contact is in a normal state, that is, a contact indicates a non-conducting state.
If it is a contact b, it indicates that it is in a conductive state.

Such a virtual inversion contact reference space 204b
The circuit for enabling virtual access to the above is the circuit shown in FIG. However, access to such a virtual inversion contact reference space 204b when a general-purpose microprocessor executes an instruction is performed by compiling a ladder program described using a mnemonic into an object code via an instruction system of the general-purpose microprocessor. In doing so, the command for the b-contact, ie, the load bar,
A portion related to a memory address for contact reference of an instruction such as an AND bar or an OR bar is stored in a virtual inverted contact reference space 204.
This can be easily performed by converting b into an address for reference. More specifically, when instructions such as a load bar, an AND bar, and an OR bar are described with respect to the contact C1, the actual access address is replaced with the address of the contact reference space 204a, which is the actual memory address described in the program. An address “0100” for referring to the virtual inversion contact reference space 204b from “0000”
Should be converted to

However, it goes without saying that individual instructions may be interpreted by the interpreter at the time of execution of the instructions, instead of the compiler. In such a case, the address may be converted by the same method as described above.

When the virtual inversion contact reference space 204b corresponding to the contact reference space 204a is virtually accessed, for example, the address "of the contact reference space 204a"
The load instruction of the ladder program (in this case, the contact C1 is the contact a) in which the data indicating the state of the contact C1 stored in “0000” is read and stored in the register,
The PLC 20 of the present invention can be used in a conventional general-purpose microprocessor.
However, LD C1 is realized by executing one instruction of mem 0000 → reg A. Here, reg A indicates an arbitrary register.

Specifically, from the CPU 50 to the RAM 204
The address "0000" of the contact reference space 204a is output to the decoder 51. The decoder 51 decodes this address and outputs "0000" as an address to the contact reference space 204a. On the other hand, since the decoder 51 outputs the read data inversion signal #RD of “0”, as described above, the data “1” read from the contact reference space 204 a passes through the gate 55 as it is, and the CPU 50 Is input to The data "1" is stored in the register as data indicating the state of the contact C1. Therefore, the data finally stored in the register is data indicating the actual state of the contact C1, which is the a contact.

However, when the contact C1 is a contact b, the conventional general-purpose microprocessor actually becomes a load bar instruction as described above, so that LDB C1: mem 0000 → reg A, #reg A → reg Although two instructions are required like A, the PLC 20 of the present invention is realized by executing one instruction of LDB C1: mem 0100 → reg A as in the case of the a contact.

More specifically, the CPU 50 sends the RAM 204
The address "0100" of the contact reference space 204a is output to the decoder 51. The decoder 51 decodes this address and outputs "0000" as an address to the contact reference space 204a. On the other hand, since the decoder 51 outputs the read data inversion signal #RD of “1”, the data “1” read from the contact reference space 204a is inverted by the gate 56 as described above,
The data is input to the CPU 50 as "0".
The data "0" obtained by inverting the data of "1" is stored in the register as data indicating the state of the contact point C1. Therefore, the data finally stored in the register is the contact C which is the b contact.
Since it can be regarded as data indicating the actual state of 1, there is no need to read out again from the register and invert it.

Further, for example, a memory address "000"
The AND instruction of the ladder program that reads the state of the contact C2 of 1 ", performs AND operation with the data indicating the state of a certain contact stored in the register, and stores the result in the register again (contact C2 is a contact a) Both the conventional general-purpose microprocessor and the PLC 20 of the present invention can be realized by executing one instruction of AND C2: reg A ∧ mem 0001 → reg A.

More specifically, from the CPU 50 to the RAM 204
Is output to the decoder 51. The decoder 51 decodes this address and outputs "0001" as an address to the contact reference space 204a. On the other hand, since the decoder 51 outputs the read data inversion signal #RD of “0”, the data “0” read from the contact reference space 204 a is directly transmitted to the CPU 50 via the gate 55 as described above. Is entered. The "0" data is ANDed with the contents of the register as it is as the data indicating the state of the contact point C2, and the result is stored in the register as it is.

However, when the contact C2 is a contact b, the conventional general-purpose microprocessor actually performs an AND bar instruction as described above. ANB C2: #reg A → reg A, reg A∨mem 0001 → reg A, #
Although three instructions such as reg A → reg A are required, in the PLC 20 of the present invention, ANB C2: reg A∧mem 0101 → reg A is executed by executing one instruction.

More specifically, from the CPU 50 to the RAM 204
The address "0101" of the contact reference space 204a is output to the decoder 51. The decoder 51 decodes this address and outputs "0001" as an address to the contact reference space 204a. On the other hand, since the decoder 51 outputs the read data inversion signal #RD of "1", the data "0" read from the contact reference space 204a is inverted by the gate 56 as described above.
The data is input to the CPU 50 as "1".
The data "1" obtained by inverting the data "1" is ANDed with the contents of the register as data indicating the state of the contact point C2, and the result is stored in the register as it is. Therefore,
The data finally stored in the register can be regarded as data indicating the actual state of the contact C2, which is the b-contact, so that there is no need to read out again from the register and invert it.

Further, for example, the memory address "001"
The OR instruction of the ladder program (contact C3 is a contact) for reading data indicating the state of the contact C3 of 0 ", performing OR operation on the data of the register, and storing the result in the register again, is a conventional general-purpose microprocessor. The PLC 20 of the present invention is also realized by executing one instruction of OR C3: reg A → mem 0010 → reg A.

More specifically, the CPU 50 sends the RAM 204
The address "0010" of the contact reference space 204a is output to the decoder 51. The decoder 51 decodes this address and outputs "0010" as an address to the contact reference space 204a. On the other hand, since the decoder 51 outputs the read data inversion signal #RD of “0”, as described above, the data “1” read from the contact reference space 204 a is directly transmitted to the CPU 50 via the gate 55. Is entered. The data of “1” is ORed with the contents of the register as it is as the data indicating the state of the contact point C3, and the result is stored in the register as it is.

However, when the contact C3 is a contact b, the conventional general-purpose microprocessor actually performs an OR instruction as described above. Therefore, ORB C3: #reg A → reg A, reg A∧ mem 0010 → reg A, #
Although three instructions such as reg A → reg A are required, the PLC 20 of the present invention is realized by executing one instruction of ORB C3: reg A∨mem 0110 → reg A.

More specifically, the CPU 50 sends the RAM 204
Is output to the decoder 51. The decoder 51 decodes this address and outputs "0010" as an address to the contact reference space 204a. On the other hand, since the decoder 51 outputs the read data inversion signal #RD of “1”, the data “1” read from the contact reference space 204a is inverted by the gate 56 as described above,
The data is input to the CPU 50 as "0".
Is ORed with the contents of the register as data indicating the state of the contact point C3, and the result is stored in the register as it is. Therefore,
Finally, the data stored in the register can be regarded as data indicating the actual state of the contact C3, which is the b-contact, so that there is no need to read the register again and invert it.

The configuration of the data output circuit 500 shown in FIG. 3 described above is merely an example, and it goes without saying that another configuration may be employed as long as the circuit exerts the same function.

In the above-described embodiment, the present invention is applied to the PLC 20 connected to the personal computer 10.
At 0, the ladder program can be simulated, so that the present invention may be applied to the personal computer 10.

[0061]

As described in detail above, according to the present invention,
Even in a programmable controller using a general-purpose microprocessor, each instruction relating to the contact b can be executed by one instruction, so that it can be executed at a higher speed than when a conventional general-purpose microprocessor is used.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing typical instruction words used in a ladder program.

FIG. 2 is a block diagram illustrating a configuration example of a system for executing a ladder program including a programmable controller according to the present invention.

FIG. 3 is a logic circuit diagram showing an example of a configuration of a memory access circuit of a programmable controller according to the present invention, that is, a data output circuit.

FIG. 4 is a RAM of the programmable controller of the present invention.
FIG. 3 is a schematic diagram showing a configuration of a memory space of FIG.

[Explanation of symbols]

 Reference Signs List 20 PLC (Programmable Controller) 50 CPU 51 Decoder 54 AND Gate 56 Inverting Gate 202 MPU 203 ROM (Compiler) 204 RAM 204a Contact Reference Space

Claims (3)

[Claims] 1. A non-conducting state of an a-contact and a conducting state of a b-contact according to sequence control have a predetermined value, and a conducting state of an a-contact and a non-conducting state of a b contact have a complementary relationship with the predetermined value. A memory for storing data indicated by values, and executing a command constituting a sequence program for processing data indicating a state of each contact stored in the memory in combination with a general-purpose microprocessor command; In the programmable controller that performs control, when data indicating the state of contact a is read from the memory, the value is output as it is, and when data indicating the state of contact b is read from the memory, the value is output. A data output circuit that inverts and outputs a signal. The data read from the memory is used as it is, and the data output circuit inverts the data read from the memory when executing the sequence program instruction for processing the b contact. A programmable controller characterized by what it does. 2. When compiling each instruction of the sequence program, a memory address included in an instruction relating to each a contact is kept as it is, and a memory address included in an instruction relating to each b contact is associated with the predetermined relationship. A data output circuit that decodes a memory address included in each instruction; and outputs a value read from the memory as it is based on a decoding result by the decoding means. 2. The programmable controller according to claim 1, further comprising means for inverting and outputting. 3. The non-conducting state of the a-contact and the conducting state of the b-contact according to the sequence control have a predetermined value, and the conducting state of the a-contact and the non-conducting state of the b contact have a complementary relationship with the predetermined value. A memory for storing data represented by values, a
When the data indicating the state of the contact is read from the memory, the value is output as it is, and when the data indicating the state of the contact b is read from the memory, the value is inverted and output. And a programmable controller that performs sequence control by executing, in combination with a general-purpose microprocessor instruction, an instruction that constitutes a sequence program for processing data indicating the state of each contact stored in the memory. The state of the b-contact stored in the memory is indicated by programming with a general-purpose microprocessor instruction so that the data of the b-contact stored in the memory is inverted by the data output circuit and stored in a register. Load bar instruction of a sequence program for storing data in the register And a general-purpose microprocessor instruction for performing an AND operation on data obtained by inverting the data of the b-contact stored in the memory by the data output circuit and data stored in the register and storing the result in the register. By programming with, an AND bar instruction of a sequence program for performing an AND operation on the data indicating the state of the contact b stored in the memory and the data indicating the state of a certain contact stored in the register, and stored in the memory The data obtained by inverting the data at the contact b by the data output circuit and the data stored in the register are OR-operated and programmed by a general-purpose microprocessor instruction so as to store the data in the register. Data indicating the status of contact b stored in the register and stored in the register Programmable controller and having a Oaba instruction sequence program that OR operation on the data indicating the state of a contact being.