JPH10107163A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize lower voltage of a non-volatile memory element mounted on a semiconductor integrated circuit device, and to raise yield of the semiconductor integrated circuit device. SOLUTION: Relating to the semiconductor integrated circuit device comprising a non-volatile memory element Q, a length W1 along the gate width direction of the interface between a charge storage gate electrode FG, and a first gate insulation film 3 is made shorter than a length W2 along the gate width direction of the interface between the charge storage gate electrode FG and the second gate insulation film 12. Relating to its manufacturing method, on a center area of the surface of the gate insulation film 3, a gate material 4 of profile of inverted trapezoid along gate's longitudinal direction is formed, and on the side wall surface of the gate material 4, a side wall spacer is formed. In addition, a thermal oxidation insulation film is formed on an active area of the main surface of a substrate 1. Further, using an anisotropic etching for forming a protective film on the side wall and an insotropic etching with the protective film as mask, the gate material 4 is patterned for prescribing a length along gate's width direction, for forming the charge storage gate electrode FG.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having a first surface on an active region on a main surface of a semiconductor substrate.
A non-volatile memory in which a charge storage gate electrode (floating gate electrode) is formed with a gate insulating film interposed and a control gate electrode (control gate electrode) is formed on the charge storage gate electrode with a second gate insulating film interposed The present invention relates to a technology effective when applied to a semiconductor integrated circuit device having a storage element.

[0002]

2. Description of the Related Art As a semiconductor integrated circuit device, a semiconductor integrated circuit device called a flash memory is disclosed in, for example, JP-A-6-77437. In this semiconductor integrated circuit device, a plurality of nonvolatile memory elements for performing a writing operation and an erasing operation by a tunnel effect are arranged in a matrix to constitute one memory block. A plurality of memory blocks are arranged in a matrix to form a memory array unit.

The nonvolatile memory element is formed in an active region on a main surface of a semiconductor substrate. This nonvolatile memory element mainly includes a semiconductor substrate used as a channel forming region, a first gate insulating film, a charge storage gate electrode (floating gate electrode), a second gate insulating film, and a control gate electrode (control gate electrode). , And a pair of semiconductor regions (impurity regions) that are a source region and a drain region.

The nonvolatile memory element is arranged at an intersection of a word line extending along the gate length direction and a data line extending along the gate width direction. Word lines are
A plurality of nonvolatile memory elements arranged along the direction in which the word lines extend are integrated with respective control gate electrodes, and are formed of, for example, a polycrystalline silicon film into which impurities are introduced. The data line is electrically connected to each drain region of a plurality of nonvolatile memory elements arranged along the direction in which the data line extends through a selection transistor, for example, an aluminum film or an aluminum alloy film. And the like. This data line is formed above the word line.

A pair of semiconductor regions, which are a source region and a drain region of the nonvolatile memory element, respectively, are a pair of semiconductor regions which are a source region and a drain region of another nonvolatile memory element arranged along the gate width direction. It is formed continuously along the gate width direction so as to be integrated with each of the regions. That is, one semiconductor region that is a source region of the nonvolatile memory element is configured as a local source line, and the other semiconductor region that is a drain region is configured as a local data line. Hereinafter, a manufacturing process of a semiconductor integrated circuit device having a nonvolatile memory element will be described.

First, a field insulating film for defining the length of the active region on the main surface along the gate length direction is formed on the inactive region on the main surface of the p-type semiconductor substrate by a known selective oxidation method. This field insulating film continuously extends along the gate width direction.

Next, a first gate insulating film is formed on the active region on the main surface of the p-type semiconductor substrate, and then polycrystalline silicon doped with impurities is formed on the central region of the first gate insulating film. A first gate material is formed of a film, the upper surface of which is covered with an oxidation-resistant mask, and whose length along the gate length direction is defined. Each of the first gate material and the oxidation resistant mask continuously extends along the gate width direction.

Next, an n-type impurity is introduced into the active region on the main surface of the p-type semiconductor substrate in a self-aligned manner with respect to the field insulating film and the first gate material, thereby forming a pair of a source region and a drain region. An n-type semiconductor region is formed. Each of the pair of n-type semiconductor regions serving as the source region and the drain region is connected to each of the pair of n-type semiconductor regions serving as the source region and the drain region of another nonvolatile memory element arranged along the gate width direction. It extends continuously along the gate width direction so as to be integrated.

Next, a sidewall spacer is formed on each of two opposing side walls in the gate length direction of the first gate material. Sidewall spacers, p-type CVD on the entire surface, for example, a silicon oxide film on the main surface of the semiconductor substrate (C hemic including on the surface of the oxidation-resistant mask
After depositing at al V apor D eposition) process, it is formed by applying anisotropic etching to the silicon oxide film. The side wall spacer is similar to the first gate material,
It extends continuously along the gate width direction.

Next, an n-type impurity is introduced into the active region on the main surface of the p-type semiconductor substrate in a self-aligned manner with respect to the field insulating film and the side wall spacer, thereby forming a pair of n + A type semiconductor region is formed. Each of the pair of n + -type semiconductor regions serving as the source region and the drain region is connected to each of the pair of n + -type semiconductor regions serving as the source region and the drain region of another nonvolatile memory element arranged along the gate width direction. It extends continuously along the gate width direction so as to be integrated. By this step, a local source line and a local data line are formed.

Next, a thermal oxidation process is performed to form a pair of thermal oxide insulating films on the active region on the main surface of the p-type semiconductor substrate between the field insulating film and the sidewall spacer. Each of the pair of thermal oxide insulating films extends continuously along the gate width direction similarly to the first gate material, and covers the respective surfaces of the pair of n + -type semiconductor regions.

Next, the oxidation-resistant mask is removed, and thereafter, a polycrystalline silicon film doped with an impurity is formed on the surface of the first gate material and has a length along the gate length direction. A prescribed second gate material is formed. The second gate material continuously extends along the gate width direction, like the first gate material.

Next, a second gate insulating film is formed on the surface of the second gate material, and then a third gate insulating film made of a polycrystalline silicon film doped with impurities is formed on the surface of the second gate insulating film. A gate material is formed.

Next, the third gate material, the second gate insulating film, the second gate material, and the first gate material are each sequentially patterned to define a length along a gate width direction. A control gate electrode and a word line are formed from the gate material, and a charge storage gate electrode is formed from each of the second gate material and the first gate material. By this step, a nonvolatile memory element is formed.

[0015]

The present inventor has studied the above-mentioned semiconductor integrated circuit device, and has found the following problems.

(1) In the semiconductor integrated circuit device,
The coupling ratio (capacitive coupling ratio) of the nonvolatile memory element is
The capacitance generated in the first gate insulating film between the semiconductor substrate (channel formation region) and the charge storage gate electrode is C1, and the capacitance generated in the second gate insulating film between the charge storage gate electrode and the control gate electrode is C2. When [C2 / (C1 + C
2)]. On the other hand, the voltage Vcg is applied to the control gate electrode.
Is applied, the voltage Vfg of the charge storage gate electrode becomes
It is represented by [1 / (C1 / C2 + 1)] × Vcg. That is, by increasing the coupling ratio of the nonvolatile memory element, the voltage Vfg of the charge storage gate electrode can be increased, so that the voltage Vcg applied to the control gate electrode can be set low. Voltage can be reduced.

However, the coupling ratio of the nonvolatile memory element becomes smaller as the nonvolatile memory element becomes finer due to higher integration. For this reason, the voltage Vfg of the charge storage gate electrode becomes low, so that the voltage applied to the control gate electrode must be set high, and the voltage of the nonvolatile memory element cannot be reduced.

(2) In the manufacturing process of the semiconductor integrated circuit device, as shown in FIG. 38 (cross-sectional view), on the active region on the main surface of the semiconductor substrate 1 between the field insulating film 2 and the sidewall spacer 8. When a pair of thermal oxide insulating films 10 is formed on the semiconductor substrate 1 between the first gate material 4 and the semiconductor substrate 1,
A gate bar beak (thermally oxidized insulating film) 10A grows from the side wall surface side of the first gate material 4 toward the center thereof, and the cross section along the gate length direction of the first gate material 4 changes into a trapezoidal shape.
The side wall spacer 8 covers a part of the first gate member 4 on the side wall surface side. For this reason, when patterning is performed on the first gate material 4 by anisotropic etching to define the length along the gate width direction, as shown in FIG. 39 (cross-sectional view), a part of the first gate material 4 is formed. 4A remains, a short circuit occurs between the nonvolatile memory elements arranged in the gate width direction, and the yield of the semiconductor integrated circuit device is significantly reduced. In FIG. 38, reference numeral 5 denotes an oxidation-resistant mask, and in FIGS. 38 and 39, reference numeral 9 denotes a pair of n + -type semiconductor regions that are a source region and a drain region.

An object of the present invention is to provide a technique capable of reducing the voltage of a nonvolatile memory element mounted on a semiconductor integrated circuit device. Thereby, the chip area can be reduced.

Another object of the present invention is to provide a manufacturing technique which achieves the above object.

Another object of the present invention is to provide a technique capable of increasing the yield of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0023]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A charge storage gate electrode is formed on an active region on a main surface of a semiconductor substrate with a first gate insulating film interposed therebetween, and is controlled on the charge storage gate electrode with a second gate insulating film interposed. A semiconductor integrated circuit device having a nonvolatile memory element having a gate electrode formed thereon, wherein a length of an interface between the charge storage gate electrode and the first gate insulating film along a gate width direction is set to the charge storage gate electrode. And the length of the interface between the gate and the second gate insulating film along the gate width direction.

(2) A charge storage gate electrode is formed on the active region on the main surface of the semiconductor substrate with a first gate insulating film interposed therebetween, and is controlled on the charge storage gate electrode with a second gate insulating film interposed. A method for manufacturing a semiconductor integrated circuit device having a nonvolatile memory element having a gate electrode formed thereon, comprising: (a)
Forming a gate material having a defined length along a gate length direction on the surface of the first gate insulating film; forming a second gate insulating film on the surface of the gate material; (2) forming a control gate electrode having a defined length along the gate width direction on the surface of the gate insulating film;
(B) patterning the second gate insulating film to define a length along a gate width direction by using an anisotropic etching method using an etching gas containing carbon and fluorine; Performing a step of over-etching the gate material exposed from the insulating film; and (c) patterning the gate material using an isotropic etching method to define a length along a gate width direction. Forming a charge storage gate electrode made of a gate material;

(3) A charge storage gate electrode is formed on the active region on the main surface of the semiconductor substrate with a first gate insulating film interposed therebetween, and is controlled on the charge storage gate electrode with a second gate insulating film interposed. A method of manufacturing a semiconductor integrated circuit device, comprising: a nonvolatile memory element having a gate electrode formed thereon; and a plurality of nonvolatile memory elements arranged along a gate width direction.
(A) A length along a gate length direction is defined on a central region of a surface of the first gate insulating film, a cross section along the gate length direction is formed in an inverted trapezoidal shape, and is continuous along a gate width direction. (B) continuously extending along the gate width direction on each of two opposing side walls in the gate length direction of the gate material. Forming a side wall spacer;
(C) performing a thermal oxidation process to form a thermal oxide insulating film extending continuously along the gate width direction in an active region on the main surface of the semiconductor substrate; and (d) forming a gate on the gate material. Forming a charge storage gate electrode made of the gate material by performing patterning for defining a length along the width direction.

According to the above means (1), the capacitance C2 generated in the second gate insulating film between the charge storage gate electrode and the control gate electrode, and the capacitance C2 between the charge storage gate electrode and the semiconductor substrate (channel formation region) Since the coupling ratio [C2 / (C1 + C2)] of the nonvolatile memory element expressed by the capacitance C1 generated in the first gate insulating film between the two can be increased, the voltage Vfg of the charge storage gate electrode can be increased. . As a result, the voltage Vcg applied to the control gate electrode
Can be set low, so that the voltage of the nonvolatile memory element can be reduced.

Further, since the voltage of the nonvolatile memory element can be reduced, it is not necessary to provide a high voltage circuit, and the integration degree of the semiconductor integrated circuit device can be increased correspondingly.

According to the above-mentioned means (2), a pattern for defining the length along the gate width direction is formed on the second gate insulating film by using an anisotropic etching method using an etching gas containing carbon and fluorine. When performing the etching and over-etching the gate material exposed from the second gate insulating film, the deposition component containing carbon as a main component is formed on the side wall surface of the control gate electrode, the side wall surface of the second gate insulating film, and the over-etching. Since the protective film adheres to the side wall surfaces of the formed gate material and a protective film is formed on these side wall surfaces, patterning is performed by using an isotropic etching method to define a length of the gate material along the gate width direction. To form a charge storage gate electrode made of a gate material, the side wall surface of the control gate electrode,
The side wall surface of the gate insulating film and the side wall surface of the over-etched gate material are not side-etched. Therefore,
The length of the interface between the charge storage gate electrode and the first gate insulating film along the gate width direction may be shorter than the length of the interface between the charge storage gate electrode and the second gate insulating film along the gate width direction. it can.

According to the above means (3), the thermal oxidation treatment is performed to form a thermal oxide insulating film extending continuously along the gate width direction on the active region on the main surface of the semiconductor substrate. Between the gate material and the semiconductor substrate, a gate bar beak (thermally oxidized insulating film) grows from the side wall surface side of the gate material toward the central portion thereof, and the growth of the gate bird's beak causes the gate material to grow in the gate length direction. The cross-section along the gate changes from an inverted trapezoidal shape to a rectangular shape, and it is possible to suppress the state where the side wall spacers cover a part of the side wall surface side of the gate material, so that the gate material defines a length along the gate width direction. When forming a charge storage gate electrode made of a gate material by performing fining, a part of the gate material does not remain between the charge storage gate electrodes in the gate width direction. As a result, a short circuit between the nonvolatile memory elements arranged in the gate width direction can be prevented, so that the yield of the semiconductor integrated circuit device can be increased.

[0031]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) This embodiment is a first embodiment in which the present invention is applied to a flash memory (semiconductor integrated circuit device).

FIG. 1 is an equivalent circuit diagram of a main part of the flash memory, FIG. 2 is a plan view of the main part of the flash memory, and FIG. 3 is a sectional view taken along line AA shown in FIG. FIG. 4 is a sectional view taken along the line BB.
Note that, in FIG. 2, a thermal oxide insulating film 10, an interlayer insulating film 15, a data line DL, and the like, which will be described later, are omitted for easy viewing.

As shown in FIG. 1, the flash memory according to the present embodiment has nonvolatile memory elements Q for performing a write operation and an erase operation by a tunnel effect, which are arranged in a matrix.
One memory block MB. A plurality of memory blocks MB are arranged in a matrix to form a memory array unit.

The nonvolatile memory element Q is arranged at the intersection of a word line WL extending along the gate length direction and a data line DL extending along the gate width direction. The word line WL is integrated with and electrically connected to each control gate electrode of the plurality of nonvolatile memory elements Q arranged along the direction in which the word line WL extends.

Each drain region of the plurality of nonvolatile memory elements Q arranged along the direction in which the data line DL extends is connected to one semiconductor region of the selection transistor ST1 via the local data line LDL. It is electrically connected. The other semiconductor region of the selection transistor ST1 is electrically connected to the data line DL. Also,
Each source region of the plurality of nonvolatile storage elements Q arranged along the direction in which the data line DL extends is electrically connected to one semiconductor region of the selection transistor ST2 via the local source line LSL. Have been. The other semiconductor region of the selection transistor ST2 is connected to the source line SL
Is electrically connected to In the flash memory configured as described above, the erasing operation of the nonvolatile memory element Q can be performed for each word line, each memory block MB, or the entire memory array unit.

Next, a specific structure of the nonvolatile memory element Q will be described with reference to FIGS. 2, 3 and 4. FIG.

As shown in FIG. 3, the nonvolatile memory element Q is formed in an active region on the main surface of a p-type semiconductor substrate 1 made of single crystal silicon. This nonvolatile memory element Q
A p-type semiconductor substrate 1, a gate insulating film 3, a charge storage gate electrode (floating gate electrode) FG, a gate insulating film 12, a control gate electrode (control gate electrode) CG, a source region, It is composed of a drain region. The source region includes an n-type semiconductor region 6 and an n + -type semiconductor region 9. The drain region includes an n-type semiconductor region 7 and an n + -type semiconductor region 9
It is composed of That is, the nonvolatile memory element Q has n
It is composed of a field effect transistor of channel conductivity type.

The gate insulating film 3 has a thickness of, for example, 8 nm.
It is formed of a silicon oxide film having a thickness set to about the same.
The gate insulating film 12 is formed of, for example, a laminated film in which a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially laminated. The first silicon oxide film is, for example, 5 [nm].
The thickness of the silicon nitride film is, for example, 10 [n].
m], and the second silicon oxide film is, for example, 4
The thickness is set to about [nm].

The charge storage gate electrode FG comprises a gate material 4 and a gate material 1 laminated on the surface of the gate material 4.
1. The gate material 4 is, for example, 100 [n]
m] and is formed of a polycrystalline silicon film. The gate material 11 is formed of, for example, a polycrystalline silicon film having a thickness of about 50 [nm]. These polycrystalline silicon films are doped with impurities that reduce the resistance value during or after the deposition.

The length of the gate material 4 along the gate length direction defines the gate length of the charge storage gate electrode FG. The length of the gate material 4 along the gate length direction is set to, for example, about 0.4 [μm].

In the gate length direction of the gate material 4,
Side wall spacers 8 are formed on the respective surfaces of the two side walls facing each other. This sidewall spacer 8 is formed of, for example, a silicon oxide film.

The control gate electrode CG is made of a gate material (13).
It is formed with. The gate material (13) is, for example, 200
It is formed of a polycrystalline silicon film having a thickness of about [nm]. The polycrystalline silicon film is doped with an impurity for reducing the resistance value during or after the deposition.

The control gate electrode CG is integrated with a word line WL extending along the gate length direction, and is connected to another nonvolatile memory element Q arranged along the direction in which the word line WL extends. It is electrically connected to the control gate electrode CG.

The n-type semiconductor region 6 as the source region
Is formed of an n-type impurity introduced in a self-alignment manner with respect to the field insulating film 2 and the gate material 4. The n-type semiconductor region 7 serving as a drain region is formed of n-type impurities introduced in a self-alignment manner with respect to the field insulating film 2 and the gate material 4. The n-type semiconductor region 7 serving as the drain region has a slightly higher impurity concentration than the n-type semiconductor region 6 serving as the source region.

The n + type semiconductor region 9, which is the source region,
Each of the n + -type semiconductor regions 9 serving as a drain region is formed of an n-type impurity introduced in a self-alignment manner with respect to the field insulating film 2 and the sidewall spacer 8. Each of the n + -type semiconductor region 9 as the source region and the n + -type semiconductor region 9 as the drain region has a higher impurity concentration than the n-type semiconductor region 7 as the drain region. That is, in the non-volatile memory element Q, the LDD ( L igh) in which a part of the drain region on the channel formation region side is set to an impurity concentration lower than the impurity concentration of the other region.
It is composed of tly D oped D rain) structure.

The field insulating film 2 is formed on the inactive region on the main surface of the p-type semiconductor substrate 1 and defines the length of the active region on the main surface of the p-type semiconductor substrate 1 along the gate length direction. I have. That is, the length along the gate length direction of the active region on the main surface of the p-type semiconductor substrate 1 is defined by the pair of field insulating films 2 formed on the non-active region on the main surface of the p-type semiconductor substrate 1. I have. Each of the pair of field insulating films 2
A silicon oxide film formed by a known selective oxidation method,
For example, the thickness is set to about 400 [nm]. Each of the pair of field insulating films 2 extends continuously along the gate width direction as shown in FIG.
The nonvolatile memory elements Q arranged in the direction in which L extends extend are electrically separated.

The n + type semiconductor region 9, which is the source region,
As shown in FIG. 2, each of the n + -type semiconductor regions 9 serving as a drain region is an n + -type semiconductor region 9 serving as a source region of a nonvolatile memory element Q arranged along the gate width direction and an n + -type serving as a drain region. It extends continuously along the gate width direction so as to be integrated with each of the mold semiconductor regions 9.
Although not shown in FIG. 2, each of the n-type semiconductor region 6 serving as a source region and the n-type semiconductor region 7 serving as a drain region is arranged along the gate width direction similarly to the n + -type semiconductor region 9. N, which is the source region of the nonvolatile memory element Q
Semiconductor region 6, n-type semiconductor region 7 serving as a drain region
And extends continuously along the gate width direction so as to be integrated with each of them. That is, each of the source region and the drain region of the nonvolatile memory element Q is electrically connected to each of the source and drain regions of another nonvolatile memory element Q arranged along the gate width direction.

The n + type semiconductor region 9, which is the source region,
Each of the n-type semiconductor regions 6 has a local source line (LSL)
Is configured as Also, the drain region is provided.
Each of the n + -type semiconductor region 9 and the n-type semiconductor region 7 is configured as a local data line (LDL). That is, the flash memory according to the present embodiment includes a local source line (LSL) and a local data line (LDL) in the p-type semiconductor substrate 1.
Are embedded in a structure embedding each of
It has a D-type circuit configuration.

The data writing to the nonvolatile memory element Q is performed, for example, by controlling the control gate electrode CG and the drain region.
(n-type semiconductor region 7, n + -type semiconductor region 9), a predetermined voltage is applied to charge storage gate electrode FG (gate material 4, gate material 11), and electrons are stored in charge storage gate electrode FG. Electron tunneling through the gate insulating film 3 from the FG to the drain regions (7, 9)
nneling). The data in the nonvolatile memory element Q is erased, for example, by applying a predetermined voltage to the control gate electrode CG, inverting the channel formation region to n-type, and accumulating electrons in the inverted channel formation region. Gate electrode F
G is performed by electron tunneling through the gate insulating film 3.

As shown in FIG. 3, this is the source region.
The surface of the n + type semiconductor region 9 is covered with a thermal oxide insulating film 10,
The surface of the n + -type semiconductor region 9 serving as the drain region is covered with a thermal oxide insulating film 10. Each of the pair of thermal oxide insulating films 10 is formed in an active region on the main surface of the p-type semiconductor substrate 1 between the field insulating film 2 and the gate material 4. Each of the pair of thermal oxide insulating films 10 continuously extends along the gate width direction. A pair of thermal oxide insulating films 10
Are formed of a silicon oxide film formed by a thermal oxidation process, and have a thickness of, for example, about 30 [nm].

As shown in FIG. 4, the length of the gate material 4 along the gate width direction defines the gate width of the charge storage gate electrode FG. The length of the gate material 4 along the gate width direction is set to, for example, about 0.4 [μm].

The length of the gate member 4 along the gate width direction is shorter than the length of the gate member 11 along the gate width direction. That is, the length W1 along the gate width direction at the interface between the charge storage gate electrode FG and the gate insulating film 3
Is shorter than the length W2 of the interface between the charge storage gate electrode FG and the gate insulating film 12 along the gate width direction.

As described above, the length W1 along the gate width direction at the interface between the charge storage gate electrode FG and the gate insulating film 3 is obtained.
Is shorter than the length W2 along the gate width direction at the interface between the charge storage gate electrode FG and the gate insulating film 12, so that the charge storage gate electrode FG and the p-type semiconductor substrate 1 are interposed. The area occupied by the gate insulating film 3 can be made smaller than the area occupied by the gate insulating film 12 interposed between the control gate electrode CG and the charge storage gate electrode FG. Since the capacitance C1 generated in the gate insulating film 3 between the semiconductor substrate 1 and the capacitor C2 generated in the gate insulating film 12 between the charge storage gate electrode FG and the control gate electrode CG can be reduced, the capacitance C2 can be reduced. It is possible to increase the coupling ratio [C2 / (C1 + C2)] of the nonvolatile memory element Q, which is expressed by the capacitance C1.

As shown in FIG. 3, the length of the gate material 11 along the gate length direction is longer than the length of the gate material 4 along the gate length direction. That is, the length of the interface between the charge storage gate electrode FG and the gate insulating film 12 along the gate length direction is longer than the length of the interface between the charge storage gate electrode FG and the gate insulating film 3 along the gate length direction. It is configured.

As described above, the length of the interface between the charge storage gate electrode FG and the gate insulating film 12 along the gate length direction is
The gate insulating film interposed between the control gate electrode CG and the charge storage gate electrode FG is configured to be longer than the length of the interface between the charge storage gate electrode FG and the gate insulating film 3 along the gate length direction. 12 can be made larger than the area occupied by the gate insulating film 3 interposed between the charge storage gate electrode FG and the p-type semiconductor substrate 1, and the charge storage gate electrode FG and the control gate electrode CG Between the charge storage gate electrode CG and the p-type semiconductor substrate 1 between the charge storage gate electrode CG and the p-type semiconductor substrate 1.
Therefore, the coupling ratio [C2 / (C1 + C2)] of the nonvolatile memory element Q represented by the capacitance C2 and the capacitance C1 can be further increased.

An insulating film 14 is formed on the surface of the control gate electrode CG. This insulating film 14 is formed of, for example, a silicon oxide film.

An interlayer insulating film 15 is formed on the entire surface of the main surface of the p-type semiconductor substrate 1 including the surface of the insulating film 14. On the surface of the interlayer insulating film 15, a data line DL extending along the gate width direction is formed. The interlayer insulating film 15 is formed of, for example, a silicon oxide film, and the data line DL is formed of, for example, a metal film such as an aluminum film or an aluminum alloy film.

Next, a method of manufacturing a flash memory having the nonvolatile memory element will be described with reference to FIGS. 5 to 16 (cross-sectional views for explaining the manufacturing method). 5 to 10 are cross-sectional views taken along the line AA shown in FIG. 2. FIGS. 11 to 16 are sectional views taken along the line BB shown in FIG.
It is sectional drawing in the position of a line.

First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, on the non-active region on the main surface of the p-type semiconductor substrate 1, a field insulating film 2 for defining the length of the active region on the main surface along the gate length direction is formed. The field insulating film 2 is formed of, for example, a thermal silicon oxide film formed by a known selective oxidation method, and continuously extends along the gate width direction.

Next, a gate insulating film 3 is formed on the active region on the main surface of the p-type semiconductor substrate 1 whose length along the gate length direction is defined by the field insulating film 2. This gate insulating film 3 is formed of a thermal silicon oxide film.

Next, a polycrystalline silicon film is formed on the entire surface of the main surface of the p-type semiconductor substrate 1 including the surface of the gate insulating film 3 by, for example, the CVD method. During or after the deposition, an impurity that reduces the resistance value is introduced into the polycrystalline silicon film.

Next, an oxidation resistant mask 5 extending along the gate width direction is formed on a part of the surface of the polycrystalline silicon film on the gate insulating film 3. This oxidation resistant mask 5
Is formed of, for example, a silicon nitride film.

Next, the polycrystalline silicon film is patterned to form a gate material 4 having a prescribed length along the gate length direction on a part of the surface of the gate insulating film 3.

Next, an n-type impurity is selectively introduced into the active region on the main surface of the p-type semiconductor substrate 1 in a self-aligned manner with respect to the field insulating film 2 and the gate material 4, thereby forming an n-type source region. A type semiconductor region 6 is formed. This n-type semiconductor region 6 extends continuously along the gate width direction.

Next, an n-type impurity is selectively introduced into the active region on the main surface of the p-type semiconductor substrate 1 in a self-aligned manner with respect to the field insulating film 2 and the gate material 4, thereby forming an n-type drain region. A type semiconductor region 7 is formed. This n-type semiconductor region 7 extends continuously along the gate width direction. The manufacturing process up to this point is shown in FIG.

Next, a silicon oxide film is formed on the entire surface of the main surface of the p-type semiconductor substrate 1 including the surface of the oxidation-resistant mask 5 by, for example, a CVD method. By performing the etching, sidewall spacers 8 are formed on each of two opposing side walls of the gate material 4 in the gate length direction. The sidewall spacers 8 extend continuously along the gate width direction. In this step, the oxidation-resistant mask 5 is also etched, and its film thickness is reduced.

Next, an n-type impurity is introduced into the active region on the main surface of the p-type semiconductor substrate 1 in a self-aligned manner with respect to the field insulating film 2 and the side wall spacer 8, thereby forming a source region and a drain region. A pair of n + type semiconductor regions 9
To form Each of the pair of n + -type semiconductor regions 9 continuously extends along the gate width direction. The manufacturing process up to this point is shown in FIG.

Next, a thermal oxidation process is performed to form a pair of thermal oxide insulating films 10 on the active region on the main surface of the p-type semiconductor substrate 1 between the field insulating film 2 and the sidewall spacers 8.
To form Each of the pair of thermal oxide insulating films 10 continuously extends along the gate width direction. In this step, each surface of the pair of n + -type semiconductor regions 9 is covered with each of the pair of thermal oxide insulating films 10. The manufacturing steps up to this point are shown in FIG.

Next, the oxidation resistant mask 5 is removed.

Next, a polycrystalline silicon film is formed on the entire surface of the main surface of the p-type semiconductor substrate 1 including the surface of the gate material 4 by, for example, the CVD method. During or after the deposition, an impurity that reduces the resistance value is introduced into the polycrystalline silicon film.

Next, patterning is performed on the polycrystalline silicon film to form a gate material 11 having a defined length along the gate length direction. The gate material 11 extends continuously along the gate width direction. FIG. 8 (A)
(A cross-sectional view taken along line -A).

Next, p including the surface of the gate material 11
A gate insulating film 12 is formed on the entire main surface of the mold semiconductor substrate 1. The gate insulating film 12 is formed of, for example, a stacked film in which a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially stacked. The gate insulating film 12 may be formed of a single layer of a silicon oxide film or a stacked film of a silicon oxide film and a silicon nitride film.

Next, a gate material 13 is formed on the entire surface of the second gate insulating film 13. The gate material 13 is formed of, for example, a polycrystalline silicon film deposited by a CVD method. During or after the deposition of the polycrystalline silicon film, an impurity for reducing the resistance value is introduced. The manufacturing steps up to this point are shown in FIG.

Next, an insulating film 14 is formed on the entire surface of the gate material 13. This insulating film 14 is formed, for example, by CVD.
It is formed of a silicon oxide film deposited by a method. FIGS. 10 (cross-sectional view taken along line AA) and FIG. 11 (B-
(A cross-sectional view taken along line B).

Next, patterning is performed on the insulating film 14 to define the length along the gate width direction, and the insulating film 14 is formed in the word line forming region on the surface of the gate material 13. The insulating film 14 extends continuously along the gate length direction. FIG. 12 (a cross-sectional view taken along line BB) showing the manufacturing process up to this point.
Shown in

Next, using the insulating film 14 as an etching mask, the gate material 13 is patterned to define the length along the gate width direction, and the gate material 13 is formed on the surface of the gate insulating film 12 in the gate width direction. A control gate electrode CG and a word line (WL) having a defined length are formed. This patterning is performed by an anisotropic etching method.
The manufacturing steps up to this point are shown in FIG.

Next, using an anisotropic etching method using an etching gas containing carbon (C) and fluorine (F), FIG.
As shown in (cross-sectional view taken along the line BB), the gate insulating film 12 is patterned to define a length along a gate width direction, and the gate material 11 exposed from the gate insulating film 12 is formed. Is over-etched. As the etching gas, a gas having a condition in which the proportion of carbon and fluorine in the gas is [fluorine / carbon ≦ 4] is used. In this step, the deposited component containing carbon as a main component adheres to the side wall surface of the control gate electrode CG, the side wall surface of the gate insulating film 12, and the side wall surface of the overetched gate material 11, and protects these side wall surfaces. The film 12a is formed.

Next, as shown in FIG. 15 (a cross-sectional view taken along the line BB), the length W1 along the gate width direction at the interface between the charge storage gate electrode FG and the gate insulating film 3 is defined as the charge storage gate. Etching is performed so as to be shorter than the length W2 along the gate width direction at the interface between the electrode FG and the gate insulating film 12. This etching includes, for example, the following two methods (1) and (2).

Method (1) Using the isotropic etching method, as shown in FIG. 15 (a cross-sectional view taken along the line BB), the gate material 11 and the gate material 4 are respectively arranged along the gate length direction. By patterning the length, a charge storage gate electrode FG made of the gate material 11 and the gate material 4 is formed. In this step, the protective film 12a containing carbon as a main component is formed on the side wall surface of the control gate electrode CG, on the side wall surface of the gate insulating film 12, and on the side wall surface of the overetched gate material 11. The side wall surface of the control gate electrode CG, the side wall surface of the gate insulating film 12, and the side wall surface of the overetched gate material 11 are not side-etched. That is, since the protective film 12a functions as a mask in the isotropic etching, the gate material 11 and the gate material 4 in the portion where the protective film 12a is not formed on the side wall are side-etched every time the gate material 11 and the gate material 4 are etched in the main surface direction. .

Method (2) First, by anisotropic etching using an etching gas containing chlorine gas, as shown in FIG. 16, each of the gate material 11 and the gate material 4 is reduced to a length W2 in the gate width direction. Process straight so that it becomes. Next, by using an isotropic etching method, each of the gate material 11 and the gate material 4 in a portion where the protective film 12a is not formed on the side wall is side-etched,
A charge storage gate electrode FG having a length W1 in the gate width direction as shown in FIG. 15 is formed. In the method (2), the step of straightly processing the gate material 11 and the gate material 4 and the step of side-etching each of the gate material 11 and the gate material 4 are separate steps, and therefore, the respective steps are optimized. It is possible to process with better control than the method (1).

Thus, the length W1 along the gate width direction at the interface between the charge storage gate electrode CG and the gate insulating film 3 is obtained.
Can be made shorter than the length W2 along the gate width direction at the interface between the charge storage gate electrode CG and the gate insulating film 12. In addition, by the isotropic etching in the methods (1) and (2), the first state in which the sidewall spacers 8 are covered as shown in FIGS.
Since the gate material 4 is removed, a short circuit between the nonvolatile memory elements Q adjacent in the gate width direction is prevented.

Next, an interlayer insulating film 15 is formed on the entire main surface of the p-type semiconductor substrate 1 including the surface of the control gate electrode CG and the surface of the word line WL. A data line DL extending along the gate length direction is formed on the surface of the semiconductor device. The interlayer insulating film 15 is formed of, for example, a silicon oxide film, and the data line DL is formed of, for example, a metal film such as an aluminum film or an aluminum alloy film.

Next, an interlayer insulating film is formed above the data line DL,
By forming the wiring, the final protective film, and the like, the flash memory of this embodiment is almost completed.

As described above, according to the present embodiment, the following effects can be obtained.

(1) The charge storage gate electrode FG is formed on the active region on the main surface of the p-type semiconductor substrate 1 with the gate insulating film 3 interposed therebetween.
A flash memory (semiconductor integrated circuit device) having a non-volatile memory element Q in which a control gate electrode CG is formed on the charge storage gate electrode FG with a gate insulating film 12 interposed therebetween. The length W1 along the gate width direction at the interface between the gate electrode FG and the gate insulating film 3 is compared with the length W2 along the gate width direction at the interface between the charge storage gate electrode FG and the gate insulating film 12. Make it short.

With this configuration, the charge storage gate electrode FG
A capacitance C2 generated in the gate insulating film 12 between the gate electrode and the control gate electrode CG, and a capacitance C1 generated in the gate insulating film 3 between the charge storage gate electrode FG and the p-type semiconductor substrate (channel formation region) 1. Since the coupling ratio [C2 / (C1 + C2)] of the nonvolatile memory element Q can be increased, the voltage Vfg of the charge storage gate electrode FG can be increased. As a result, the voltage Vcg applied to the control gate electrode CG can be set low, so that the voltage of the nonvolatile memory element Q can be reduced.

Further, since the voltage of the nonvolatile memory element Q can be reduced, it is not necessary to provide a high voltage circuit, and the integration degree of the flash memory can be increased correspondingly.

Further, the voltage of the nonvolatile memory element Q can be reduced without reducing the effective channel length of the nonvolatile memory element Q.

(2) The charge storage gate electrode FG is composed of the gate material 4 and the gate material 11 laminated on the surface of the gate material 4, and the interface between the gate material 11 and the gate insulating film 12 is formed. The length along the gate length direction is configured to be longer than the length along the gate length direction at the interface between the gate material 4 and the gate insulating film 3.

With this configuration, the charge storage gate electrode FG
A capacitance C2 generated in the gate insulating film 12 between the gate electrode and the control gate electrode CG, and a capacitance C1 generated in the gate insulating film 3 between the charge storage gate electrode FG and the p-type semiconductor substrate (channel formation region) 1. Since the coupling ratio [C2 / (C1 + C2)] of the nonvolatile memory element Q can be further increased, the voltage of the nonvolatile memory element Q can be further reduced.

(3) The charge storage gate electrode FG is formed on the active region on the main surface of the p-type semiconductor substrate 1 with the gate insulating film 3 interposed therebetween.
And a method of manufacturing a flash memory (semiconductor integrated circuit device) having a nonvolatile memory element Q in which a control gate electrode CG is formed on the charge storage gate electrode FG with a gate insulating film 12 interposed therebetween, The gate insulating film 3
A gate material 4 and a gate material 11 whose lengths along the gate length direction are defined on the surface of the gate material 11, and then a gate insulating film 12 is formed on the surface of the gate material 11,
Using a step of forming a control gate electrode CG having a defined length along the gate width direction on the surface of the gate insulating film 12 and an anisotropic etching method using an etching gas containing carbon and fluorine, The gate insulating film 12 is patterned to define a width along a gate width direction, and the gate material 11 exposed from the gate insulating film 12 is formed.
A step of performing over-etching on the gate material 11 and the gate material 4 by using an isotropic etching method.
Forming a charge storage gate electrode FG made of the gate material 11 and the gate material 4 by patterning to define a length along the gate width direction.

According to this structure, the gate insulating film 12 is patterned by using an anisotropic etching method using an etching gas containing carbon and fluorine to define a length along a gate width direction. When the gate material 11 exposed from the film 12 is over-etched, a deposition component containing carbon as a main component is formed on the side wall surface of the control gate electrode CG, the side wall surface of the gate insulating film 12 and the side of the over-etched gate material 11. Since the protective film 12a is adhered to the wall surface and the protective film 12a is formed on these side wall surfaces, the length along the gate width direction is defined for each of the gate material 11 and the gate material 4 by using an isotropic etching method. When patterning is performed to form the charge storage gate electrode FG made of each of the gate material 11 and the gate material 4, the side wall surface of the control gate electrode CG, the gate insulating film The side wall surface of the second side wall surface and over the etched gate material 11 is not side-etched. Accordingly, the length of the interface between the charge storage gate electrode FG and the gate insulating film 3 along the gate width direction is shorter than the length of the interface between the charge storage gate electrode FG and the gate insulating film 12 along the gate width direction. be able to.

In this embodiment, the case where the charge storage gate electrode FG is constituted by each of the gate material 4 and the gate material 11 has been described. However, the charge storage gate electrode FG may be constituted only by the gate material 4. . In this case, in the manufacturing process, patterning is performed on the gate insulating film 12 to define the length along the gate width direction, and the gate material 4 exposed from the gate insulating film 12 is over-etched.

(Embodiment 2) This embodiment is a second embodiment in which the present invention is applied to a flash memory (semiconductor integrated circuit device).

FIG. 17 is a sectional view of a main part of the flash memory along the gate length direction (a sectional view taken along the line A1-A1 shown in FIG. 19). FIG. 18 is a sectional view of the flash memory in the gate width direction. FIG. 19 is a cross-sectional view of a main part
FIG. 3 is a cross-sectional view taken along the line B1).

The flash memory according to the present embodiment has the structure shown in FIG.
As shown in FIG. 1, a p-type semiconductor substrate 1 made of, for example, single crystal silicon is mainly used. In the active region on the main surface of the p-type semiconductor substrate 1, a nonvolatile memory element Qf that performs a write operation and an erase operation by a tunnel effect is formed. The nonvolatile memory element Qf mainly includes a p-type semiconductor region 1 used as a channel forming region, a gate insulating film 3, a charge storage gate electrode (floating gate electrode) F
G, a gate insulating film 12, a control gate electrode (control gate electrode) CG, and a pair of n + -type semiconductor regions 20, which are a source region and a drain region.

As shown in FIGS. 17 and 18, the nonvolatile memory element Qf includes a data line DL extending along the gate length direction and a word line W extending along the gate width direction.
It is arranged at the intersection with L. A plurality of the nonvolatile memory elements Q are arranged along the direction in which the data lines DL extend, and a plurality of the nonvolatile memory elements Q are arranged along the direction in which the word lines WL extend. Note that the method of writing and erasing data in the nonvolatile memory element Qf is the same as in the first embodiment.

One n + type semiconductor region 20 of the nonvolatile storage element Qf is also used as the other n + type semiconductor region 20 of another nonvolatile storage element Qf arranged in the direction in which the data line DL extends. I have. Further, the control gate electrode CG of the nonvolatile memory element Qf is integrated with the control gate electrode FG of another nonvolatile memory element Qf arranged along the direction in which the word line WL extends, and is configured as a word line WL. Have been.

On the inactive region on the main surface of the p-type semiconductor substrate 1, a field insulating film 2 for defining the length of the active region on the main surface in the gate width direction is formed. The field insulating film 2 extends continuously along the gate length direction, and electrically isolates the nonvolatile memory elements Qf arranged in the direction in which the word lines WL extend.

P including the surface of the control gate electrode CG
An interlayer insulating film 15 is formed on the entire main surface of the semiconductor substrate 1. On the surface of this interlayer insulating film 15, a data line DL extending along the gate length direction is formed.

As shown in FIG. 17, the length L1 along the gate length direction at the interface between the charge storage gate electrode FG and the gate insulating film 3 is different from the gate length at the interface between the charge storage gate electrode FG and the gate insulating film 12. It is configured to be shorter than the length L2 along the long direction.

As described above, the length L1 along the gate length direction at the interface between the charge storage gate electrode FG and the gate insulating film 3 is obtained.
Is shorter than the length L2 along the gate width direction at the interface between the charge storage gate electrode FG and the gate insulating film 12, so that the charge storage gate electrode FG and the p-type semiconductor substrate 1 are interposed. The area occupied by the gate insulating film 3 can be made smaller than the area occupied by the gate insulating film 12 interposed between the control gate electrode CG and the charge storage gate electrode FG. Since the capacitance C1 generated in the gate insulating film 3 between the semiconductor substrate 1 and the capacitor C2 generated in the gate insulating film 12 between the charge storage gate electrode FG and the control gate electrode CG can be reduced, the capacitance C2 can be reduced. Coupling ratio of the nonvolatile memory element Qf [C2 / (C1 + C2)]
Can be increased.

Next, a method for manufacturing the flash memory will be described with reference to FIGS. 20 to 23 (cross-sectional views for explaining the manufacturing method). 20 to 23.
FIG. 3 is a sectional view along a gate length direction.

First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, on the non-active region on the main surface of the p-type semiconductor substrate 1, a field insulating film 2 for defining the length of the active region on the main surface along the gate length direction is formed. The field insulating film 2 is formed of, for example, a thermal silicon oxide film formed by a known selective oxidation method, and continuously extends along the gate width direction.

Next, a gate insulating film 3 is formed on the active region on the main surface of the p-type semiconductor substrate 1 whose length along the gate length direction is defined by the field insulating film 2. This gate insulating film 3 is formed of a thermal silicon oxide film.

Next, a gate material 4 having a defined length along the gate width direction is formed on the central region of the surface of the gate insulating film 3. The gate material 4 is formed of, for example, a polycrystalline silicon film into which impurities are introduced.

Next, a gate insulating film 11 is formed on the entire surface of the main surface of the p-type semiconductor substrate 1 including the surface of the gate material 4, and then on the surface of the gate insulating film 12 in the gate width direction. Is defined, and a gate material 13 extending along the gate length direction is formed. The gate insulating film 12
For example, it is formed of a laminated film in which a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially laminated. Gate material 13
Is formed of, for example, a polycrystalline silicon film into which impurities are introduced.

Next, a mask 21 extending continuously along the gate width direction is formed on a predetermined region on the surface of the gate material 13. The mask 21 is formed of, for example, a silicon oxide film. FIG. 20 shows the manufacturing process up to this point.

Next, using the mask 21 as an etching mask, the gate material 13 is patterned to define a length along the gate length direction, and is patterned on the surface of the gate insulating film 12 along the gate length direction. A control gate electrode CG and a word line (WL) having a defined length are formed. This patterning is performed by an anisotropic etching method.
FIG. 21 shows the manufacturing process up to this point.

Next, using an anisotropic etching method using an etching gas containing carbon (C) and fluorine (F), as shown in FIG. Is performed, and the gate material 4 exposed from the gate insulating film 12 is over-etched. As the etching gas, a gas having a condition in which the proportion of carbon and fluorine in the gas is [fluorine / carbon ≦ 4] is used. In this step, the deposited component containing carbon as a main component adheres to the side wall surface of the control gate electrode CG, the side wall surface of the gate insulating film 12, and the side wall surface of the overetched gate material 4, and protects these side wall surfaces. The film 12a is formed.

Next, the method (1) of the first embodiment, the method
In the same manner as (2), as shown in FIG. 23, the gate material 4 is subjected to patterning for defining a length along the gate length direction to form a charge storage gate electrode FG made of the gate material 4 I do. In this step, the protective film 12a containing carbon as a main component is formed on the side wall surface of the control gate electrode CG, on the side wall surface of the gate insulating film 12, and on the side wall surface of the overetched gate material 4. In the isotropic etching, the side wall surface of the control gate electrode CG,
The side wall surface of the gate insulating film 12 and the side wall surface of the over-etched gate material 4 are not side-etched, and the portion of the gate material 1 where the side wall is not protected by the protective film 12a.
1. Side walls of the gate material 4 are side-etched. Therefore, the length L1 along the gate length direction at the interface between the charge storage gate electrode CG and the gate insulating film 3 is compared with the length L2 along the gate length direction at the interface between the charge storage gate electrode CG and the gate insulating film 12. Can be shortened.

Next, an n-type impurity is introduced into the active region on the main surface of the p-type semiconductor substrate 1 by self-alignment with the charge storage gate electrode FG, and a pair of n + -type semiconductors serving as a source region and a drain region are formed. A region 20 is formed, and then an interlayer insulating film 15 is formed on the entire surface of the main surface of the p-type semiconductor substrate 1 including the surface of the control gate electrode CG and the surface of the word line WL.
Thereafter, a data line DL extending along the gate length direction is formed on the surface of the interlayer insulating film 15. The interlayer insulating film 15 is formed of, for example, a silicon oxide film, and the data line DL is formed of, for example, a metal film such as an aluminum film or an aluminum alloy film.

Next, an interlayer insulating film is formed above the data line DL,
By forming the wiring, the final protective film, and the like, the flash memory of this embodiment is almost completed.

As described above, according to the present embodiment, the following functions and effects can be obtained.

(1) The charge storage gate electrode FG is formed on the active region on the main surface of the p-type semiconductor substrate 1 with the gate insulating film 3 interposed therebetween.
A flash memory (semiconductor integrated circuit device) having a non-volatile memory element Q in which a control gate electrode CG is formed on the charge storage gate electrode FG with a gate insulating film 12 interposed therebetween. The length L1 along the gate length direction at the interface between the gate electrode FG and the gate insulating film 3 is compared with the length L2 along the gate length direction at the interface between the charge storage gate electrode FG and the gate insulating film 12. Make it short.

With this configuration, the charge storage gate electrode FG
A capacitance C2 generated in the gate insulating film 12 between the gate electrode and the control gate electrode CG, and a capacitance C1 generated in the gate insulating film 3 between the charge storage gate electrode FG and the p-type semiconductor substrate (channel forming region) 1. Since the coupling ratio [C2 / (C1 + C2)] of the nonvolatile memory element Q can be increased, the voltage Vfg of the charge storage gate electrode FG can be increased. As a result, the voltage Vcg applied to the control gate electrode CG can be set low, so that the voltage of the nonvolatile memory element Q can be reduced.

Further, since the voltage of the nonvolatile memory element Q can be reduced, it is not necessary to provide a high voltage circuit, and the integration degree of the flash memory can be increased correspondingly.

(2) The charge storage gate electrode FG is formed on the active region on the main surface of the p-type semiconductor substrate 1 with the gate insulating film 3 interposed therebetween.
And a method of manufacturing a flash memory (semiconductor integrated circuit device) having a nonvolatile memory element Q in which a control gate electrode CG is formed on the charge storage gate electrode FG with a gate insulating film 12 interposed therebetween, The gate insulating film 3
A gate material 4 having a defined length along the gate width direction is formed on the surface of the gate material 4, and then a gate insulating film 12 is formed on the surface of the gate material 4.
Forming a control gate electrode CG having a defined length along the gate length direction on the surface of the gate insulating film 2 by using an anisotropic etching method using an etching gas containing carbon and fluorine. 12, performing patterning for defining a length along the gate length direction, and performing over-etching on the gate material 4 exposed from the gate insulating film 12, and using the isotropic etching method to form the gate. Forming a charge storage gate electrode FG made of the gate material 4 by patterning the material 4 to define a length along the gate width direction.

According to this structure, the gate insulating film 12 is patterned by using an anisotropic etching method using an etching gas containing carbon and fluorine to define the length along the gate length direction. When the gate material 4 exposed from the film 12 is over-etched, the deposited component mainly composed of carbon contains the side wall surface of the control gate electrode CG, the side wall surface of the gate insulating film 12 and the side of the over-etched gate material 4. Since the protective film 12a adheres to the wall surface and is formed on these side wall surfaces, the gate material 4 is patterned by using an isotropic etching method so as to define a length along a gate length direction. When forming the charge storage gate electrode FG made of each of the gate materials 4, the side wall surface of the control gate electrode CG, the side wall surface of the gate insulating film 12, and The sidewall surface of the gate member 11 is not side-etched. Therefore, the length L1 along the gate length direction at the interface between the charge storage gate electrode FG and the gate insulating film 3
Can be made shorter than the length L2 along the gate length direction at the interface between the charge storage gate electrode FG and the gate insulating film 12.

(Embodiment 3) This embodiment is a third embodiment in which the present invention is applied to a flash memory (semiconductor integrated circuit device).

FIG. 24 is a plan view of a main part of the flash memory, FIG. 25 is a sectional view taken along the line CC shown in FIG. 24, and FIG. 26 is a sectional view taken along the line DD shown in FIG. FIG. 27 is a cross-sectional view taken along a line, and FIG.
FIG. 1 is a sectional view taken along a line E, and FIG. 1 is an equivalent circuit diagram of a main part of the flash memory. Note that in FIG. 24, a thermal oxide insulating film 10 (described later)
The illustration of the interlayer insulating film 15, the data lines DL, and the like is omitted.

In the flash memory of this embodiment, as shown in FIG. 1, nonvolatile memory elements Q for performing a writing operation and an erasing operation by a tunnel effect are arranged in a matrix.
One memory block MB. A plurality of memory blocks MB are arranged in a matrix to form a memory array unit.

The nonvolatile memory element Q is arranged at the intersection of a word line WL extending along the gate length direction and a data line DL extending along the gate width direction. The word line WL is integrated with and electrically connected to each control gate electrode of the plurality of nonvolatile memory elements Q arranged along the direction in which the word line WL extends.

Each drain region of the plurality of nonvolatile memory elements Q arranged along the direction in which the data line DL extends is connected to one semiconductor region of the selection transistor ST1 via the local data line LDL. It is electrically connected. The other semiconductor region of the selection transistor ST1 is electrically connected to the data line DL. Also,
Each source region of the plurality of nonvolatile storage elements Q arranged along the direction in which the data line DL extends is electrically connected to one semiconductor region of the selection transistor ST2 via the local source line LSL. Have been. The other semiconductor region of the selection transistor ST2 is connected to the source line SL
Is electrically connected to In the flash memory configured as described above, the erasing operation of the nonvolatile memory element Q can be performed for each word line, each memory block MB, or the entire memory array unit.

Next, a specific structure of the nonvolatile memory element Q will be described with reference to FIGS. 24, 25, 26, and 27. FIG.

As shown in FIG. 25, the nonvolatile memory element Q is formed in an active region on the main surface of a p-type semiconductor substrate 1 made of single crystal silicon. This nonvolatile memory element Q
Are mainly a p- type semiconductor substrate 1 used as a channel formation region, a gate insulating film 3, a charge storage gate electrode (floating gate electrode) FG, a gate insulating film 12, a control gate electrode (control gate electrode) CG, It is composed of a source region and a drain region. The source region is n
Semiconductor region (n-type impurity region) 6 and n + type semiconductor region (n
+ Type impurity region) 9. The drain region is
An n-type semiconductor region (n-type impurity region) 7 and an n + -type semiconductor region (n + -type impurity region) 9 are provided. That is, the nonvolatile memory element Q is formed of an n-channel conductivity type field effect transistor.

The gate insulating film 3 has a thickness of, for example, 8 nm.
It is formed of a silicon oxide film having a thickness set to about the same.
The gate insulating film 12 is formed of, for example, a laminated film in which a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially laminated. The first silicon oxide film is, for example, 5 [nm].
The thickness of the silicon nitride film is, for example, 10 [n].
m], and the second silicon oxide film is, for example, 4
The thickness is set to about [nm].

The charge storage gate electrode FG comprises a gate material 4 and a gate material 1 laminated on the surface of the gate material 4.
1. Each of the gate material 4 and the gate material 11 is formed of, for example, a polycrystalline silicon film. These polycrystalline silicon films are doped with impurities that reduce the resistance value during or after the deposition.

The length of the gate material 4 along the gate length direction defines the gate length of the charge storage gate electrode FG. The length of the gate material 4 along the gate length direction is set to, for example, about 0.4 [μm].

In the gate length direction of the gate material 4,
Side wall spacers 8 are formed on the respective surfaces of the two side walls facing each other. This sidewall spacer 8 is formed of, for example, a silicon oxide film.

The control gate electrode CG is made of a gate material (13).
It is formed with. The gate material (13) is formed of, for example, a polycrystalline silicon film. The polycrystalline silicon film is doped with an impurity for reducing the resistance value during or after the deposition.

The control gate electrode CG is integrated with a word line WL extending along the gate length direction, and is connected to another nonvolatile memory element Q arranged along the direction in which the word line WL extends. It is electrically connected to the control gate electrode CG.

The n-type semiconductor region 6 as the source region
Is formed of an n-type impurity introduced in a self-alignment manner with respect to the field insulating film 2 and the gate material 4. The n-type semiconductor region 7 serving as a drain region is formed of n-type impurities introduced in a self-alignment manner with respect to the field insulating film 2 and the gate material 4. The n-type semiconductor region 7 serving as the drain region has a slightly higher impurity concentration than the n-type semiconductor region 6 serving as the source region.

The n + type semiconductor region 9, which is the source region,
Each of the n + -type semiconductor regions 9 serving as a drain region is formed of an n-type impurity introduced in a self-alignment manner with respect to the field insulating film 2 and the sidewall spacer 8. Each of the n + -type semiconductor region 9 as the source region and the n + -type semiconductor region 9 as the drain region has a higher impurity concentration than the n-type semiconductor region 7 as the drain region.

The field insulating film 2 is formed on the inactive region on the main surface of the p-type semiconductor substrate 1 and defines the length of the active region on the main surface of the p-type semiconductor substrate 1 along the gate length direction. I have. That is, the length along the gate length direction of the active region on the main surface of the p-type semiconductor substrate 1 is defined by the pair of field insulating films 2 formed on the non-active region on the main surface of the p-type semiconductor substrate 1. I have. Each of the pair of field insulating films 2
It is formed of a silicon oxide film formed by a known selective oxidation method. As shown in FIG. 22, each of the pair of field insulating films 2 extends continuously along the gate width direction, and electrically connects between the nonvolatile memory elements Q arranged in the direction in which the word lines WL extend. Separated.

The n + type semiconductor region 9, which is the source region,
Each of the n + -type semiconductor regions 9 serving as the drain region is shown in FIG.
As shown in FIG. 7, the gate is integrated with the n + -type semiconductor region 9 as the source region and the n + -type semiconductor region 9 as the drain region of the nonvolatile memory element Q arranged along the gate width direction. It extends continuously along the width direction. Although not shown in FIG. 24, each of the n-type semiconductor region 6 serving as a source region and the n-type semiconductor region 7 serving as a drain region is arranged along the gate width direction similarly to the n + -type semiconductor region 9. And extends continuously along the gate width direction so as to be integrated with the n-type semiconductor region 6 as the source region and the n-type semiconductor region 7 as the drain region of the nonvolatile memory element Q. . That is, each of the source region and the drain region of the nonvolatile memory element Q is electrically connected to each of the source and drain regions of another nonvolatile memory element Q arranged along the gate width direction.

The n + type semiconductor region 9, which is the source region,
Each of the n-type semiconductor regions 6 has a local source line (LSL)
Is configured as Also, the drain region is provided.
Each of the n + -type semiconductor region 9 and the n-type semiconductor region 7 is configured as a local data line (LDL). That is, the flash memory according to the present embodiment includes a local source line (LSL) and a local data line (LDL) in the p-type semiconductor substrate 1.
Are embedded in a structure embedding each of
It has a D-type circuit configuration.

As shown in FIG. 25, the surface of the n + -type semiconductor region 9 as the source region is covered with a thermal oxide insulating film 10, and the surface of the n + -type semiconductor region 9 as the drain region is covered with the thermal oxide insulating film 10. Covered with. Each of the pair of thermal oxide insulating films 10 is formed in an active region on the main surface of the p-type semiconductor substrate 1 between the field insulating film 2 and the gate material 4. Each of the pair of thermal oxide insulating films 10 continuously extends along the gate width direction. A pair of thermal oxide insulating films 1
Each of 0 is formed of a silicon oxide film formed by a thermal oxidation process.

As shown in FIG. 26, the length of the gate material 4 along the gate width direction defines the gate width of the charge storage gate electrode FG. The length of the gate material 4 along the gate width direction is set to, for example, about 0.4 [μm].

As shown in FIG. 27, between the nonvolatile memory elements Q in the gate width direction, the gate material 4,
Each of the gate material 11 and the gate material (13) does not extend.

Next, a method of manufacturing a flash memory having the nonvolatile memory element will be described with reference to FIGS.
(A cross-sectional view for explaining the manufacturing method) will be described.
Note that FIGS. 28 to 32 are cross-sectional views taken along the line CC shown in FIG. 24, and FIGS. 33 to 35 are cross-sectional views taken along the line DD shown in FIG. 36 and 37
FIG. 25 is a sectional view taken along line EE shown in FIG. 24.

First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, on the non-active region on the main surface of the p-type semiconductor substrate 1, a field insulating film 2 for defining the length of the active region on the main surface along the gate length direction is formed. The field insulating film 2 is formed of, for example, a thermal silicon oxide film formed by a known selective oxidation method, and continuously extends along the gate width direction.

Next, a gate insulating film 3 is formed on the active region on the main surface of the p-type semiconductor substrate 1 whose length along the gate length direction is defined by the field insulating film 2. This gate insulating film 3 is formed of a thermal silicon oxide film.

Next, a polycrystalline silicon film is formed on the entire surface of the main surface of the p-type semiconductor substrate 1 including the surface of the gate insulating film 3 by, for example, the CVD method. During or after the deposition, an impurity that reduces the resistance value is introduced into the polycrystalline silicon film.

Next, an oxidation resistant mask 5 extending along the gate width direction is formed on a part of the surface of the polycrystalline silicon film on the gate insulating film 3. This oxidation resistant mask 5
Is formed of, for example, a silicon nitride film.

Next, the polycrystalline silicon film is patterned to define a length along a gate length direction on a part of the surface of the gate insulating film 3 and a cross section along the gate length direction is inverted. A gate material 4 formed in a shape and continuously extending in the gate width direction is formed. The manufacturing process here is shown in FIG. 28 (a cross-sectional view taken along line CC).

Next, an n-type impurity is selectively introduced into the active region on the main surface of the p-type semiconductor substrate 1 in a self-aligned manner with respect to the field insulating film 2 and the gate material 4, thereby forming an n-type source region. A type semiconductor region 6 is formed. This n-type semiconductor region 6 extends continuously along the gate width direction.

Next, an n-type impurity is selectively introduced into the active region on the main surface of the p-type semiconductor substrate 1 in a self-aligned manner with respect to the field insulating film 2 and the gate material 4, thereby forming an n-type drain region. A type semiconductor region 7 is formed. This n-type semiconductor region 7 extends continuously along the gate width direction.

Next, a silicon oxide film is formed on the entire surface of the main surface of the p-type semiconductor substrate 1 including the surface of the oxidation-resistant mask 5 by, for example, the CVD method. A sidewall spacer 8 is formed on each of two opposing side walls in the gate length direction of the gate material 8 by performing a reactive etching. The sidewall spacers 8 extend continuously along the gate width direction. In this step, the oxidation-resistant mask 5 is also etched, and its film thickness is reduced. The manufacturing process up to this point is shown in FIG.
(A cross-sectional view taken along line C).

Next, an n-type impurity is introduced into the active region on the main surface of the p-type semiconductor substrate 1 in a self-aligned manner with respect to the field insulating film 2 and the side wall spacer 8, thereby forming a source region and a drain region. A pair of n + type semiconductor regions 9
To form Each of the pair of n + -type semiconductor regions 9 continuously extends along the gate width direction. The manufacturing process up to this point is shown in FIG. 30 (cross-sectional view taken along line CC).

Next, a thermal oxidation treatment is performed, and FIG.
As shown in FIG.
P-type semiconductor substrate 1 between gate and sidewall spacer 8
A pair of thermal oxide insulating films 10 is formed on the active region on the main surface of FIG. Each of the pair of thermal oxide insulating films 10 continuously extends along the gate width direction. In this step, a pair of
Each surface of the n + type semiconductor region 9 has a pair of thermal oxide insulating films 1
0 each. In this step, between the gate material 4 and the p-type semiconductor substrate 1, a gate bird's beak (thermal oxide insulating film) 1 is formed from the gate material 4 toward the center thereof.
0A grows, and the growth of the gate bird's beak 10A causes the cross section of the gate material 4 along the gate length direction to change from an inverted trapezoidal shape to a rectangular shape. Can be prevented from being covered. The manufacturing process up to this point is shown in FIG. 31 (cross-sectional view taken along line CC).

Next, the oxidation resistant mask 5 is removed.

Next, a polycrystalline silicon film is formed on the entire main surface of the p-type semiconductor substrate 1 including the surface of the gate material 4 by, for example, the CVD method. During or after the deposition, an impurity that reduces the resistance value is introduced into the polycrystalline silicon film.

Next, the polycrystalline silicon film is patterned to form a gate material 11 whose length along the gate length direction is defined. The gate material 11 extends continuously along the gate width direction.

Next, p including the surface of the gate material 11
A gate insulating film 12 is formed on the entire main surface of the mold semiconductor substrate 1. The gate insulating film 12 is formed of, for example, a stacked film in which a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially stacked. A first silicon oxide film, a silicon nitride film,
Each of the second silicon oxide films is formed by, for example, a CVD method.

Next, a gate material 13 is formed on the entire surface of the gate insulating film 13. Gate material 13 is formed of, for example, a polycrystalline silicon film deposited by a CVD method. During or after the deposition of the polycrystalline silicon film, an impurity for reducing the resistance value is introduced.

Next, an insulating film 14 is formed on the entire surface of the gate material 13. This insulating film 14 is formed, for example, by CVD.
It is formed of a silicon oxide film deposited by a method. FIGS. 32 (cross-sectional view taken along the line CC) and FIG. 33 (D-
(A sectional view taken along line D).

Next, patterning is performed on the insulating film 14 so that a word line forming region on the surface of the gate material 13 is
An insulating film 14 having a defined length along the gate width direction is formed. The insulating film 14 extends continuously along the gate length direction.

Next, using the insulating film 14 as an etching mask, the gate material 13 and the gate insulating film 12 are sequentially patterned to define the length along the gate width direction, and the gate material 13 and the gate insulating film 12 are sequentially patterned along the gate width direction. A control gate electrode CG and a word line WL having a defined length are formed, and
Gate insulating film 12 having a defined length along the gate width direction
To form This patterning is performed by an anisotropic etching method. FIG. 34 (D-D)
FIG. 36 (a cross-sectional view taken along line EE).

Next, patterning for defining the length along the gate width direction is sequentially performed on each of the gate material 11 and the gate material 4 to form a charge storage gate electrode made of the gate material 11 and the gate material 4. FG is formed. The steps so far are shown in FIG. 35 (cross-sectional view taken along line DD) and FIG.
(A sectional view taken along line E). In this step, the cross section of the gate material 4 along the gate width direction is formed in a rectangular shape, and a portion of the gate material 4 on the side of the side wall surface is not covered with the side wall spacer 8. As shown in FIG. 7, the nonvolatile memory element Q in the gate width direction
A part of the gate material 4 does not remain between them.
This patterning is performed by, for example, anisotropic etching.

Next, an interlayer insulating film 15 is formed on the entire surface of the main surface of the p-type semiconductor substrate 1 including the surface of the control gate electrode CG and the surface of the word line WL. A data line DL extending along the gate length direction is formed on the surface of the semiconductor device. The interlayer insulating film 15 is formed of, for example, a silicon oxide film, and the data line DL is formed of, for example, a metal film such as an aluminum film or an aluminum alloy film.

Next, an interlayer insulating film is formed above the data line DL,
By forming the wiring, the final protective film, and the like, the flash memory of this embodiment is almost completed.

As described above, according to the present embodiment, the following operational effects can be obtained.

The charge storage gate electrode FG is formed on the active region on the main surface of the p-type semiconductor substrate 1 with the gate insulating film 3 interposed therebetween, and the gate insulating film 1 is formed on the charge storage gate electrode FG.
2. A method of manufacturing a flash memory (semiconductor integrated circuit device) having a nonvolatile memory element Q on which a control gate electrode CG is formed with a plurality of nonvolatile memory elements 2 interposed therebetween, and arranging a plurality of nonvolatile memory elements Q along the gate width direction A length along the gate length direction is defined on a central region of the surface of the gate insulating film 3, a cross section along the gate length direction is formed in an inverted trapezoidal shape, and is continuous along the gate width direction. Forming a gate material 4 that extends in a row, and a side extending continuously along the gate width direction on each of two opposing side walls in the gate length direction of the gate material 4. A step of forming a wall spacer 8 and a thermal oxidation process are performed to form a thermal oxide insulating film 10 continuously extending along the gate width direction on the active region on the main surface of the p-type semiconductor substrate 1. Step and the gate material 4 Subjected to patterning to define the length along the gate width direction, comprising forming a charge storage gate electrode FG made of the gate material 4.

According to this configuration, when thermal oxidation is performed to form thermal oxide insulating film 10 extending continuously along the gate width direction on the active region on the main surface of p-type semiconductor substrate 1,
Between the gate member 4 and the p-type semiconductor substrate 1, a gate bar beak is formed from the side wall surface side of the gate member 4 toward the center thereof.
(Thermally oxidized insulating film) 10A grows, and the growth of the gate bird's beak 10A changes the cross section of the gate material 4 along the gate length direction into a rectangular shape. Suppresses the state in which the gate material 4 is covered, when the gate material 4 is patterned to define the length along the gate width direction, and the charge storage gate electrode FG made of the gate material 4 is formed, the charge in the gate width direction is reduced. Part of the gate material 4 does not remain between the storage gate electrodes FG. As a result, a short circuit between the nonvolatile memory elements Q arranged in the gate width direction can be prevented.
The yield of the semiconductor integrated circuit device can be improved.

As described above, the invention made by the present inventors is described below.
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

For example, the patterning of the charge storage gate electrode FG in the third embodiment may use the method (1) or the method (2) in the first embodiment.

For example, the present invention can be applied to a one-chip microcomputer (semiconductor integrated circuit device) provided with a memory array unit having a nonvolatile storage element.

[0174]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

In a semiconductor integrated circuit device having a nonvolatile memory element, the voltage of the nonvolatile memory element can be reduced.

Further, the degree of integration of the semiconductor integrated circuit device can be increased.

Further, the yield of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a flash memory according to a first embodiment of the present invention;
FIG. 3 is an equivalent circuit diagram of a main part of (semiconductor integrated circuit device).

FIG. 2 is a plan view of a main part of the flash memory.

FIG. 3 is a sectional view taken along a line AA shown in FIG. 2;

FIG. 4 is a sectional view taken along the line BB shown in FIG. 2;

FIG. 5 is a cross-sectional view for explaining a method for manufacturing the flash memory.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 7 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 8 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 9 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 10 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 11 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 12 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 13 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 14 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 15 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 16 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 17 is a flash memory according to a second embodiment of the present invention;
FIG. 3 is a sectional view of a main part of a (semiconductor integrated circuit device).

FIG. 18 is a sectional view of a main part of the flash memory.

FIG. 19 is a plan view of a main part of the flash memory.

FIG. 20 is a cross-sectional view for describing the method for manufacturing the flash memory.

FIG. 21 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 22 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 23 is a sectional view for illustrating the method for manufacturing the flash memory.

FIG. 24 is a flash memory according to a third embodiment of the present invention;
FIG. 3 is a plan view of a main part of (semiconductor integrated circuit device).

25 is a sectional view taken along the line CC shown in FIG. 24.

26 is a sectional view taken along the line DD shown in FIG. 24.

FIG. 27 is a cross-sectional view taken along a line EE shown in FIG.

FIG. 28 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 29 is a cross-sectional view for describing the method for manufacturing the flash memory.

FIG. 30 is a cross-sectional view for describing the method for manufacturing the flash memory.

FIG. 31 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 32 is a cross-sectional view for describing the method for manufacturing the flash memory.

FIG. 33 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 34 is a cross-sectional view for describing the method for manufacturing the flash memory.

FIG. 35 is a cross-sectional view for explaining the method for manufacturing the flash memory.

FIG. 36 is a cross-sectional view for describing the method for manufacturing the flash memory.

FIG. 37 is a cross-sectional view for describing the method for manufacturing the flash memory.

FIG. 38 is a cross-sectional view for explaining the conventional flash memory manufacturing method.

FIG. 39 is a cross-sectional view for explaining a conventional flash memory manufacturing method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p-type semiconductor substrate, 2 ... thermal oxidation insulating film, 3 ... 1st gate insulating film, 4 ... gate material, 5 ... oxidation resistant mask, 6 ...
n-type semiconductor region, 7 ... n-type semiconductor region, 8 ... sidewall spacer, 9 ... n + -type semiconductor region, 10 ... thermal oxide insulating film, 11 ... gate material, 12 ... second gate insulating film, 13 ...
Gate material, 14: insulating film, 15: interlayer insulating film, WL: word line, DL: data line, FG: charge storage gate electrode (floating gate electrode), CG: control gate electrode
(Control gate electrode), Q: nonvolatile storage element.

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Akihiko Konno 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Tsutomu Okazaki 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd.Device Development Center, Ltd. (72) Inventor Masataka Kato 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Tetsuo Adachi 5-2-1, Josuihoncho, Kodaira-shi, Tokyo (72) Inventor Osamu Tsuchiya 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd.

Claims (16)

[Claims] 1. A charge storage gate electrode is formed on an active region on a main surface of a semiconductor substrate with a first gate insulating film interposed therebetween.
A semiconductor integrated circuit device having a nonvolatile memory element in which a control gate electrode is formed on a charge storage gate electrode with a second gate insulating film interposed therebetween, wherein the charge storage gate electrode, the first gate insulating film, Wherein the length of the interface along the gate width direction is shorter than the length of the interface between the charge storage gate electrode and the second gate insulating film along the gate width direction. Circuit device. 2. The charge storage gate electrode comprises a first gate material and a second gate material laminated on a surface of the first gate material, wherein the first gate material, the first gate insulating film, The length of the interface along the gate width direction along the gate width direction is shorter than the length of the interface between the second gate material and the second gate insulating film along the gate width direction. 2. The semiconductor integrated circuit device according to 1. 3. The length of the interface between the second gate material and the second gate insulating film in the gate length direction is the length of the interface between the first gate material and the first gate insulating film in the gate length direction. 3. The structure according to claim 2, wherein the length is longer than the length.
3. The semiconductor integrated circuit device according to 1. 4. The semiconductor according to claim 1, wherein the control gate electrode is integrated with a word line extending along a gate length direction. Integrated circuit device. 5. A charge storage gate electrode is formed on an active region on a main surface of a semiconductor substrate with a first gate insulating film interposed therebetween.
A semiconductor integrated circuit device having a nonvolatile memory element in which a control gate electrode is formed on a charge storage gate electrode with a second gate insulating film interposed therebetween, wherein the charge storage gate electrode, the first gate insulating film, Wherein the length of the interface along the gate length direction is shorter than the length of the interface between the charge storage gate electrode and the second gate insulating film along the gate length direction. Circuit device. 6. The semiconductor integrated circuit device according to claim 5, wherein said control gate electrode is integrated with a word line extending along a gate width direction. 7. A charge storage gate electrode is formed on an active region on a main surface of a semiconductor substrate with a first gate insulating film interposed therebetween.
A method for manufacturing a semiconductor integrated circuit device having a nonvolatile memory element in which a control gate electrode is formed on a charge storage gate electrode with a second gate insulating film interposed therebetween, comprising the following steps: Of manufacturing a semiconductor integrated circuit device. (A) forming a gate material having a defined length along a gate length direction on the surface of the first gate insulating film, and then forming a second gate insulating film on the surface of the gate material; Forming a control gate electrode having a defined length along a gate width direction on a surface of the second gate insulating film;
(B) patterning the second gate insulating film to define a length along a gate width direction by using an anisotropic etching method using an etching gas containing carbon and fluorine; Over-etching the gate material exposed from the insulating film; and (c) patterning the gate material by using an isotropic etching method to define a length along a gate width direction. Forming a charge storage gate electrode made of a material. 8. The second gate insulating film is formed of a laminated film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated, and the gate material is a polycrystalline silicon film or an amorphous silicon film. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the semiconductor integrated circuit device is formed. 9. The method according to claim 7, wherein said control gate electrode is integrated with a word line extending along a gate length direction. . 10. The semiconductor device according to claim 1, wherein a first surface is formed on an active region on a main surface of the semiconductor substrate.
Manufacturing of a semiconductor integrated circuit device having a nonvolatile memory element in which a charge storage gate electrode is formed with a gate insulating film interposed and a control gate electrode is formed on the charge storage gate electrode with a second gate insulating film interposed A method for manufacturing a semiconductor integrated circuit device, comprising: (A) forming a gate material having a defined length along a gate width direction on the surface of the first gate insulating film, and then forming a second gate insulating film on the surface of the gate material; Forming a control gate electrode having a defined length along a gate length direction on a surface of the second gate insulating film;
(B) patterning the second gate insulating film to define a length along a gate length direction by using an anisotropic etching method using an etching gas containing carbon and fluorine; Over-etching the gate material exposed from the insulating film; (c) patterning the gate material by using an isotropic etching method to define a length along a gate length direction; Forming a charge storage gate electrode made of a material. 11. The second gate insulating film is a silicon oxide film,
11. The semiconductor according to claim 10, wherein the gate material is formed of a polycrystalline silicon film or an amorphous silicon film, and is formed of a laminated film in which a silicon nitride film and a silicon oxide film are sequentially stacked. A method for manufacturing an integrated circuit device. 12. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein said control gate electrode is integrated with a word line extending along a gate width direction. . 13. The over-etching in the step (b) includes over-etching the gate material and forming a protective film on a side wall of the gate material. 13. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the method is performed by using the film as a mask. 14. The method according to claim 1, further comprising the step of patterning the gate material between the steps (b) and (c) by using an anisotropic etching method using a chlorine-based etching gas. A method for manufacturing a semiconductor integrated circuit device. 15. A semiconductor device comprising: a first substrate having an active region on a main surface thereof;
A nonvolatile storage element having a charge storage gate electrode formed with a gate insulating film interposed therebetween and a control gate electrode formed on the charge storage gate electrode with a second gate insulating film interposed therebetween; A method for manufacturing a semiconductor integrated circuit device in which a plurality of elements are arranged along a gate width direction,
A method for manufacturing a semiconductor integrated circuit device, comprising the following steps. (A) A length along a gate length direction is defined on a central region of a surface of the first gate insulating film, a cross section along the gate length direction is formed in an inverted trapezoidal shape, and is continuous along a gate width direction. Forming a gate material that extends in a continuous manner, and (b) a side continuously extending along the gate width direction on each of two opposing side wall surfaces in the gate length direction of the gate material. Forming a wall spacer, and (c) performing a thermal oxidation process on the active region on the main surface of the semiconductor substrate.
Forming a thermal oxide insulating film extending continuously along the gate width direction; and (d) patterning the gate material to define a length along the gate width direction, and accumulating the charge made of the gate material. Forming a gate electrode; 16. The method according to claim 15, wherein the patterning for defining the length along the gate width direction is performed by an anisotropic etching method.