JPH10106263A - Decoder circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent multi-selection of decode signals by pronging a decoder circuit with a pulse generating circuit for outputting a control signal based on an external clock signal. SOLUTION: A synchronous type DRAM has a plurality of Y address counter circuits 11 which receive an external synchronous input signal CLK and a plurality of Y address buffer circuits 12 which receive a plurality of external addresses Ao to Ai as inputs. Further, the DRAM has a plurality of Y address predecoder circuits 43 which receive a reset signal RST which is output from internal Y address signals TAo to YAj and a pulse generating circuit 433 as input, and is controlled by the pulse generating circuit 433 which outputs a control signal based on an external synchronous input signal CLK. Only when the control signal is at a specific level, the internal Y address signals TAo to YAj are decoded by the Y address predecoder circuits 43.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a decoder circuit in a synchronous semiconductor memory device.

[0002]

2. Description of the Related Art In a conventional DRAM, a Y address counter circuit to which an external synchronizing input signal (CLK) is input, an address count signal which is an output of the Y address counter circuit, and an external input address are input to form an internal Y address counter. A Y address buffer circuit for outputting an address signal. The internal Y address signal output from the Y address buffer circuit is input to the Y address predecoder circuit, and the Y address predecoder circuit outputs a predecode signal to the Y address decoder circuit.

[0003]

However, in the above-described conventional example, there is a problem that skew occurs between the respective internal Y addresses and multiple selection of a decode signal occurs. That is, the Y address counter circuit and the address buffer circuit are independent circuits, and the resistance value and the capacitance value on the output signal line of each circuit are different. Therefore, skew occurs between the internal Y addresses. This skew causes a shift in the activation timing of the predecode signal, and as a result, multiple selection occurs in which a decode signal to be originally selected and another decode signal are simultaneously selected. As an example of a defect when multiple selection occurs, a phenomenon occurs in which data once written to a normal address during a write operation is rewritten due to occurrence of multiple selection.

[0004]

According to the present invention, in order to solve the above problems, a pulse generating circuit for outputting a control signal based on an external clock signal is provided in a decoder circuit. Decoding means is controlled so that the internal address signal is decoded only when this control signal is at a predetermined level. As a specific configuration, the decoding circuit of the present invention includes:
A pulse generation circuit that outputs a control signal based on an external clock signal; an internal address generation unit that outputs an internal address signal based on an external address signal and an external clock signal; A first decoding means for decoding an internal address signal and outputting a first decode signal only when the first decode signal is at a second level, and a second decode means for decoding the first decode signal and outputting a second decode signal. Decoding means.

[0005]

FIG. 1 shows an example of the configuration of a Y address system of a synchronous DRAM according to a first embodiment of the present invention. This DRAM has an external synchronization input signal CL
A plurality of Y address counter circuits 11 having K as an input
And a plurality of Y address buffer circuits 12 to which address count signals C0 to Cj output from the Y address counter circuit 11 and a plurality of external input addresses A0 to Aj are input, and an external synchronization input signal CLK. A pulse generation circuit 433. Furthermore, this DRA
M denotes a plurality of Ys which receive the internal Y address signals YA0 to YAj output from the Y address buffer circuit 12 and the reset signal RST output from the pulse generation circuit 433 as inputs.
The address predecoder circuit 43, and predecode signals PS11 to PS11 output from the Y address predecoder circuit 43
And a Y address decoder circuit 14 to which PSj4 is input. In the Y address decoder circuit 14, decode signals S0 to Sn, which are outputs of the Y address decoder circuit 14, are input to the gate, and the source is the data bus DB /.
Through a plurality of NMOS transistors 15 having a drain connected to the bit line BL / BLb and a drain connected to the bit line BL / BLb, the drain is connected to a sense amplifier circuit and a memory array unit 16 including memory cells. ing.

FIG. 2 is a circuit diagram of the Y address predecoder circuit 43, the pulse generation circuit 433, and the Y address decoder circuit 14 in FIG. Note that Y in FIG.
The address predecoder circuit 43 will be described separately for a first Y address predecoder circuit 431 and a second Y address predecoder circuit 432. The pulse generation circuit 433 is
Two-input NAND element 433a and three inverter rows 43
3b. External synchronization input signal CLK is input to the input of inverter train 433b. 2-input NAND
One input of the element 433a is connected to the external synchronization input signal CLK.
Is input, and the other input is an inverter train 433b.
Output is connected. Then, the pulse generation circuit 433 outputs a reset signal RST. The first Y address predecoder circuit 431 includes four 3-input NAND elements 43
1a, 431b, 431c, and 431d.
The three-input NAND element 431a includes a negative logic signal YA0b of the internal Y address and a negative logic signal YA1b of the internal Y address.
And a reset signal RST, and outputs a predecode signal PS11. The three-input NAND element 431b is
A positive logic signal YA0 of the internal Y address, a negative logic signal YA1b of the internal Y address, and a reset signal RST are input, and a predecode signal PS12 is output. 3 input NA
The ND element 431c is a negative logic signal YA of the internal Y address.
0b, the positive logic signal YA1 of the internal Y address and the reset signal RST are input, and the predecode signal PS13 is output. The three-input NAND element 431d outputs a positive logical signal YA0 of the internal Y address and a positive logical signal Y of the internal Y address.
A1 and a reset signal RST are input, and a predecode signal PS14 is output.

The second Y address predecoder circuit 132
Are four 3-input NAND elements 432a, 432b, 4
32c and 432d. The three-input NAND element 432a includes a negative logic signal YA2b of the internal Y address, a negative logic signal YA3b of the internal Y address, and a reset signal R.
ST is input and outputs a predecode signal PS21. The three-input NAND element 432b includes a positive logical signal YA2 of the internal Y address and a negative logical signal YA3 of the internal Y address.
b and the reset signal RST are input, and the predecode signal PS22 is output. 3-input NAND element 432c
Are input to the negative logic signal YA2b of the internal Y address, the positive logic signal YA3 of the internal Y address, and the reset signal RST.
And outputs a predecode signal PS23. 3
The input NAND element 432d receives the positive logic signal YA2 of the internal Y address, the positive logic signal YA3 of the internal Y address, and the reset signal RST, and receives the predecode signal PS2.
4 is output. The Y address decoder circuit 14 includes a plurality of two-input NOR elements 14a to 14p. The predecode signal PS11 is input to one input of the two-input NOR element 14a, the predecode signal PS21 is input to the other input, and the decode signal S0 is output. A predecode signal PS12 is input to one input of the two-input NOR element 14b, a predecode signal PS21 is input to the other input, and a decode signal S1 is output. A predecode signal PS13 is input to one input of the two-input NOR element 14c, a predecode signal PS21 is input to the other input, and a decode signal S2 is output. A predecode signal PS14 is input to one input of the two-input NOR element 14d, a predecode signal PS21 is input to the other input, and a decode signal S3 is output. Hereinafter, similarly, a two-input NOR element 1
4e to 14p has a predecode signal PS1
1, PS12, PS13, PS14 are input in order,
The other input is a predecode signal PS2 every four elements.
2, PS23 and PS24 are input and the decode signal S4
To S15.

FIG. 3 is a timing chart showing operation waveforms according to the first embodiment. First, each internal address signal and address count signal are previously set to a ground potential (hereinafter referred to as low level), each predecode signal and reset signal are set to a power supply potential (hereinafter referred to as high level),
It is assumed that each decode signal is set to a low level. Here, an example in which a low-level external input address is input at time t0 will be described. At time t0, address count signals C0, C1, C2, and C3, which are pulse signals that activate and increment the internal Y address signal, are activated. By this signal, the internal Y addresses YA0b, YA1b, YA2
b, YA3b change from low level to high level. Here, when the reset signal RST, which is a pulse signal controlled by the external synchronization input signal CLK, changes from the high level to the low level, the predecode signals PS11 and PS21 remain at the high level during this low level period. Thereafter, when the reset signal changes from the low level to the high level, the predecode signals PS11 and PS21 change from the high level to the low level. As a result, the decode signal S0 changes from a low level to a high level.

At time t1, when address count signal C0 is activated, internal Y address YA0b changes from high level to low level, and internal Y address Y
A0 changes from a low level to a high level. Here, when the reset signal RST changes from the high level to the low level,
The predecode signals PS11 and PS21 change from low level to high level, and the decode signal S0 changes from high level to low level. Thereafter, when the reset signal RST changes from low level to high level, the predecode signal PS1
2. PS21 changes from high level to low level. As a result, the decode signal S1 changes from a low level to a high level. At time t2, when the address count signals C0, C1 are activated, the internal Y address YA0, YA0,
YA1b changes from high level to low level, and internal Y addresses YA0b and YA1 change from low level to high level. When the reset signal RST changes from high level to low level, the predecode signals PS12 and PS21 change from low level to high level, and the decode signal S1 changes from high level to low level. When the reset signal changes from low level to high level, the predecode signal PS1
3 changes from the high level to the low level. As a result, the decode signal S2 changes from a low level to a high level.

At time t3, when the address count signal C0 is activated, the internal Y address YA0b changes from the high level to the low level, and the internal Y address YA0b changes.
0 changes from a low level to a high level. Reset signal R
When ST changes from the high level to the low level, the predecode signals PS13 and PS21 change from the low level to the high level, and the decode signal S2 changes from the high level to the low level. When the reset signal changes from low to high, the predecode signal PS14 changes from high to low. As a result, the decode signal S3 changes from a low level to a high level. At time t4, when the address count signals C0, C1, C2 are activated, the internal Y addresses YA0, YA1, YA2b change from the high level to the low level and the internal Y addresses YA0b, YA
1b and YA2 change from low level to high level. When the reset signal changes from the high level to the low level, the predecode signals PS14 and PS21 change from the low level to the high level, and the decode signal S3 changes from the high level to the low level. When the reset signal changes from low to high, the predecode signals PS11 and PS22 change from high to low. As a result, the decoded signal S
4 changes from a low level to a high level. Thereafter, the same operation is repeated to synchronize with the external synchronization input signal CLK,
A continuous decode signal having a non-selected section is selected. Thereafter, although omitted in FIG. 3, the selected decode signal turns on the NMOS transistor 15 shown in FIG. 1, connects the bit lines BL / BLb and the data bus DB / DBb, and writes or reads data. Perform the operation.

As described above, according to the first embodiment,
By providing the reset signal RST generated by the external synchronization input signal CLK, the activation timing of each predecode signal depends only on the reset signal RST without depending on the skew of the internal Y address. Therefore, multiple selection of the decode signal can be prevented. Further, since the external synchronization input signal CLK is used as the input signal of the pulse generation circuit, control of the synchronous DRAM is easy. Further, since a reset signal is input to each of the predecoder circuits in common, the configuration of each of the predecoder circuits can be made the same, and the unified control of a plurality of predecoder circuits can be performed. can get.

FIG. 4 shows an example of the configuration of a Y address system of a synchronous DRAM according to a second embodiment of the present invention. As in the first embodiment, the DRAM of the second embodiment includes a plurality of Y address counter circuits 11 to which an external synchronization input signal CLK is input, and an address count signal which is an output of the Y address counter circuit 11. C0-C
It has a plurality of Y address buffer circuits 12 that receive j and a plurality of external input addresses A0 to Aj, and a pulse generation circuit 433 that receives an external synchronization input signal CLK. Further, a Y address predecoder circuit 43 which receives the internal Y address signals YA0 and YA0b output from the Y address buffer circuit 12 and a reset signal RST output from the pulse generation circuit 433, and an output from the Y address buffer circuit 12 Internal Y address signal Y
A plurality of Y-address pre-decoder circuits 13 which receive A1 to YAjb as inputs, and a Y-address decoder circuit 14 which receives pre-decode signals PS11 to PSj4 output from the Y-address predecoder circuit 43 and the Y-address predecoder circuit 13 as inputs. And In the Y address decoder circuit 14, decode signals S0 to Sn, which are outputs of the Y address decoder circuit 14, are input to the gate, the source is connected to the data bus DB / DBb, and the drain is connected to the bit line BL / BLb. Multiple NMs
Via the OS transistor 15, the bit lines BL / BLb
Are connected to a memory array unit 16 including a sense amplifier circuit and a memory cell.

FIG. 5 is a circuit diagram of the Y address predecoder circuit 43, the Y address predecoder circuit 43, the pulse generation circuit 433, and the Y address decoder circuit 14 in FIG. Note that the Y address predecoder circuit 43 in FIG.
And the second Y address predecoder circuit 433. The pulse generation circuit 433 includes a two-input NAND element 433a and three inverter rows 433b. External synchronization input signal CLK is input to the input of inverter train 433b. The external synchronization input signal CLK is input to one input of the two-input NAND element 433a, the output of the inverter train 433b is input to the other input, and the reset signal RST is output from the output. First Y
The address predecoder circuit 431 includes four 3-input NAs.
It is composed of ND elements 431a, 431b, 431c, and 431d. The three-input NAND element 431a receives as inputs the negative logic signal YA0b of the internal Y address, the negative logic signal YA1b of the internal Y address, and the reset signal RST, and outputs a predecode signal PS11. 3 input NA
The ND element 431b receives as inputs the positive logic signal YA0 of the internal Y address, the negative logic signal YA1b of the internal Y address, and the reset signal RST, and receives the predecode signal PS1.
2 is output. The input of the 3-input NAND element 431c is input to the negative logic signal YA0 of the internal Y address, the positive logic signal YA1 of the internal Y address, and the reset signal RST.
The predecode signal PS13 is output. 3-input NAND
The element 431d has a positive logic signal Y of an internal Y address
A0, a positive logic signal YA1 of the internal Y address, and a reset signal RST are input, and a predecode signal PS14 is output.

Second Y address predecoder circuit 433
Are four two-input NAND elements 132a, 132b, 1
32c and 132d. The 2-input NAND element 132a has a negative logic signal YA2 of the internal Y address as an input.
b and the negative logic signal YA3b of the internal Y address are input, and a predecode signal PS21 is output. 2-input NA
The ND element 132b receives as inputs a positive logic signal YA2 of the internal Y address and a negative logic signal YA3b of the internal Y address, and outputs a predecode signal PS22. The two-input NAND element 132c has a negative logic signal YA2b of an internal Y address and a positive logic signal YA3 of an internal Y address as inputs.
And outputs a predecode signal PS23. 2
The input NAND element 132d has as inputs the positive logical signal YA2 of the internal Y address and the positive logical signal YA of the internal Y address.
3 is input, and a predecode signal PS24 is output.
The Y address decoder circuit 14 includes a plurality of two-input NOR elements 14a to 14p. 2-input NOR element 1
A predecode signal PS11 and a predecode signal PS21 are input to the input of 4a, and a decode signal S0 is output. The predecode signal PS12 and the predecode signal PS21 are input to the input of the two-input NOR element 14b, and output the decode signal S1. 2-input NOR element 1
The input of 4c receives the predecode signal PS13 and the predecode signal PS21, and outputs the decode signal S2. The pre-decode signal PS14 and the pre-decode signal PS21 are input to the input of the two-input NOR element 14d, and output the decode signal S3. Hereinafter, similarly, two inputs N
The predecode signal P is input to the inputs of the OR elements 14e to 14p.
S11, PS12, PS13, PS14 and predecode signals PS22, PS23, PS24 are input for every four elements, and decode signals S4 to S15 are output.

FIG. 6 shows a synchronous DRAM according to a second embodiment.
6 is a timing chart showing operation waveforms of FIG. Each internal address signal and address count signal are previously set to a ground potential (hereinafter referred to as low level), and each predecode signal and reset signal are set to a power supply potential (hereinafter referred to as high level).
It is assumed that each decode signal is set to a low level. Hereinafter, an example in which a low-level external input address is input at time t0 will be described. At time t0, address count signals C0, C1, C2, and C3, which are pulse signals that activate and increment the internal Y address signal, are activated. By this signal, the internal Y addresses YA0b, YA1b, YA2
b, YA3b change from low level to high level. Here, when the reset signal RST, which is a pulse signal controlled by the external synchronization input signal CLK, changes from the high level to the low level, the predecode signal PS11 remains at the high level during this low level section. Thereafter, when the reset signal changes from the low level to the high level, the predecode signal PS11 changes from the high level to the low level. As a result, the decode signal S0 changes from a low level to a high level. At time t1, when address count signal C0 is activated, internal Y address YA0
b changes from the high level to the low level, and the internal Y address YA0 changes from the low level to the high level. Here, when the reset signal RST changes from the high level to the low level, the predecode signal PS11 changes from the low level to the high level, and the decode signal S0 changes from the high level to the low level. Thereafter, when the reset signal RST changes from the low level to the high level, the predecode signal PS12 changes from the high level to the low level. As a result, the decode signal S1 changes from a low level to a high level.

At time t2, when address count signals C0 and C1 are activated, internal Y address YA0, YA0,
YA1b changes from high level to low level, and internal Y addresses YA0b and YA1 change from low level to high level. When the reset signal RST changes from the high level to the low level, the predecode signal PS12 changes from the low level to the high level, and the decode signal S1 changes from the high level to the low level. When the reset signal changes from low to high, the predecode signal PS13 changes from high to low. As a result, the decode signal S2 changes from a low level to a high level. At time t3, when the address count signal C0 is activated,
The internal Y address YA0b changes from the high level to the low level, and the internal Y address YA0 changes from the low level to the high level. When the reset signal RST changes from the high level to the low level, the predecode signal PS13 changes from the low level to the high level, and the decode signal S2 changes from the high level to the low level. When the reset signal changes from low to high, the predecode signal PS14 changes from high to low. As a result, the decode signal S3 changes from a low level to a high level.

At time t4, when the address count signals C0, C1, C2 are activated, the internal Y address Y
A0, YA1, YA2b change from high level to low level, and internal Y addresses YA0b, YA1b, YA2
Goes from a low level to a high level. As a result, the predecode signal PS21 changes from the low level to the high level, and the predecode signal PS22 changes from the high level to the low level. Here, when the reset signal RST changes from the high level to the low level, the predecode signal PS1
4 changes from low level to high level, and the decode signal S3 changes from high level to low level. When the reset signal changes from a low level to a high level, the predecode signal PS1
1 changes from the high level to the low level. As a result, the decode signal S4 changes from a low level to a high level. Thereafter, the same operation is repeated, and a continuous decode signal having a non-selection period in synchronization with the external synchronization input signal CLK is selected. Thereafter, although omitted in FIG. 6, the selected decode signal causes the NM shown in FIG.
The OS transistor 15 is turned on, and the bit line BL / B
Lb and the data bus DB / DBb are connected to perform a write or read operation.

As described above, according to the second embodiment, similarly to the first embodiment, an effect is obtained that the multiple selection of the decoded signal can be prevented. Further, by providing only the first Y address predecoder circuit as the circuit to which the reset signal is input by the clock, the effect of reducing the pattern area and current consumption can be obtained. That is, 3
Since only one circuit uses an input NAND element and the other uses a two-input NAND element, the pattern area can be reduced. Further, in the first embodiment, the predecode signal repeats a high level and a low level every clock cycle. However, in the second embodiment, the current consumption can be reduced because it is every four clock cycles.

[0019]

As described in detail above, according to the present invention, there is obtained an effect that multiple selection of a decoded signal can be prevented.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a Y address system according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram of a Y address decoder according to the first embodiment;

FIG. 3 is a timing chart showing operation waveforms according to the first embodiment;

FIG. 4 is a configuration block diagram of a Y address system according to a second embodiment of the present invention;

FIG. 5 is a circuit diagram of a Y address decoder according to a second embodiment;

FIG. 6 is a timing chart showing operation waveforms according to the second embodiment;

[Explanation of symbols]

 11. . . Y address counter circuit 12. . . 13. Y address buffer circuit . . Y address decoder circuit 43. . . Y address predecoder circuits 431a-d, 432a-d. . . 3-input NAND elements 132a to 132d. . . 2-input NAND elements 14a to p. . . Two-input NOR element 433. . . Pulse generation circuit

Claims (2)

[Claims] A pulse generating circuit for outputting a control signal based on an external clock signal; an internal address generating means for outputting an internal address signal based on an external address signal and the external clock signal; And a first decoding means for decoding the internal address signal and outputting a first decoded signal only when the control signal is at a predetermined level, and a second decoding means for decoding the first decoded signal and outputting a second decoded signal. And a second decoding means for outputting the decoding signal of (a). 2. A pulse generating circuit for outputting a control signal based on an external clock signal, an internal address generating means for outputting an internal address signal based on an external address signal and the external clock signal, and an internal address and control signal. And a first decoding means for decoding the internal address signal and outputting a first decode signal only when the control signal is at a predetermined level, and a second decode signal for decoding the internal address. A second decoding means for outputting the first and second decoding signals, and a third decoding means for decoding the first and second decoding signals.
And a third decoding means for outputting a decoding signal of (c).