JPH10105139A - Screen division device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inexpensive screen division device which has small interference between video signals. SOLUTION: Four kind of video signals are divided into two groups consisting of two kind of video signals, which are switched by switches 2a and 2b at each horizontal synchronism rate and stored in memories 8a and 8b through A/D converters 6a and 6b. Then they are read out of the memories 8a and 8b at double the frequency and compressed, and converted from digital to analog by a D/A converter 12; and then video signals #1 and #2 are arranged, side by side, in a time corresponding to the upper half of' a nmonitor display and video signals >=3 and >=4 are displayed; side by side, in a, time corresponding to the lower half, so that the four kind of video signals are compressed and displayed on a single monitor at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a screen division device capable of simultaneously viewing × N types of video signals.

[0002]

2. Description of the Related Art In a conventional device of this type, a plurality of types of video signals are stored in a memory using one sampling means, and after compression, are extracted as a single video signal. Therefore, crosstalk was easily generated between input video signals. In addition, since a raster scan memory such as a first-in first-out (FIFO) memory cannot be used for both reading and writing, and A / D conversion is performed on a pixel-by-pixel basis, a high-speed A / D converter is required. The device could not be configured.

As a conventional apparatus, for example, Japanese Patent Laid-Open No.
The operation of the image four-segmentation apparatus described in Japanese Patent Publication No. 0792 will be described with reference to FIG. FIG. 5A shows video # 1,
Shown are combinations of four types of video signals of # 2, # 3, and # 4 in units of horizontal scanning lines, and (b) shows E ₁ , ₂ and E ₃ , _{4 in} (a).
(C) shows a signal combined on a pixel-by-pixel basis. In the figure, H indicates a horizontal synchronization signal, and PC indicates one pixel.

[0006] Four types of video signals form four types of combinations in units of horizontal scanning lines and pixels, and four types of quarter-compressed screens are generated by sequentially switching pixels and sampling in these four types of combinations.

That is, the horizontal scanning lines are divided into odd-numbered lines (2N-1) and even-numbered lines (2N) as shown in FIG. 5 (a), and further, as shown in FIG. A set of video signals, here video # 1 and # 2, video # 3 and # 4
In each of the sets, a virtual number is assigned to a pixel in one horizontal scanning line in a case where the pixel is temporarily sampled, divided into odd-numbered pixels (2P−1) and even-numbered pixels (2P), and { (2N-1) and (2P-1)} to video signal # 2
{(2N-1) = (2P)}, video signal # 3 is {(2N) = (2P)}.
P-1)} and {(2N) (2P)} are assigned to the video signal # 4, and only the assigned pixels are switched in memory units in the order shown in FIG. By storing the data and reading it out from the memory at a rate twice as high as the sampling rate, it is output as a single video signal, and four types of video signals are displayed on one monitor.

[0006]

In the technique of the conventional screen division device configured as described above, since it is necessary to switch the video signal in pixel units, the video signal is switched, for example, as shown in FIG. When the luminance (brightness) is extremely different between # 1 and # 2, as shown in FIG. 6B, a rapid change cannot be followed in a pixel unit time PCt, so the input video signal # 1 , # 2. The actual signal S1 shown by the solid line becomes duller than the ideal signal S shown by the broken line. Therefore, there has been a problem that a sudden change in one video signal has an influence on another video signal, and this appears on a monitor. Also, like a FIFO memory,
A raster scan memory cannot be used for both reading and writing, and A / D conversion is performed on a pixel basis.
There is also a problem that a D converter is required and an inexpensive device cannot be configured.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide an inexpensive screen splitting device which causes less interference between video signals.

[0008]

SUMMARY OF THE INVENTION In view of the above-mentioned object, a first aspect of the present invention is to display N × ² images on one screen by N ×
This is a screen division device for dividing and displaying N trixes, and displaying N × N kinds of video signals side by side.
Selecting means for selecting N video signals in parallel for each group in order at a horizontal synchronization rate, memory means for storing the video signals as image data, In parallel with each group, N video signals are sampled successively and sequentially for each horizontal scan, and the number of N signals is equal to the number of groups.
Means for storing a set of pixel data as a series of pixel data in the memory means, and reading and switching the N sets of video signals from the memory means at N times the sampling rate and every 1 / N of the vertical synchronization rate. A screen comprising: means for extracting a compressed data string as a single video signal; and control signal generating means for generating a signal for controlling a horizontal synchronizing signal, a vertical synchronizing signal, and a reproduction clock. In the splitting device.

According to a second aspect of the present invention, the writing means includes N A / D converters for A / D converting a video signal, and averages conversion errors of the A / D converters. N
2. The screen dividing apparatus according to claim 1, further comprising an exchange unit for exchanging the A / D converters one after another for use.

[0010] The third invention of the present invention is a method for producing a three
3. The screen dividing apparatus according to claim 1, wherein each of the components is provided with each of the components to perform color display.

According to a fourth aspect of the present invention, a color display is performed by providing each of the above means for each of the three components of luminance and two types of difference signals. In the device.

According to a fifth aspect of the present invention, four screens are displayed on one screen.
The screen dividing apparatus according to any one of claims 1 to 4, wherein the screen dividing apparatus is a four-screen dividing apparatus for dividing and displaying individual images in a 2 x 2 matrix.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a configuration diagram of a screen dividing apparatus according to an embodiment of the present invention. In particular, here, as shown in FIG. 2, a screen that divides and displays four images in a 2 × 2 matrix on one screen. A description will be given by showing a four-split device.

In the figure, 2a and 2b are video input switches, 4a, 4b and 14 are low-pass filters (LP
F), 6a, 6b are A / D converters, 8a, 8b are FIF
O memory, 10 is flip-flop (F / F), 12 is D
An A / A converter 16 is a synchronous component adder whose output is supplied to a monitor (not shown) which performs screen division display. 1
8a to 18c are AND gates, 20 is a vertical counter, 2
2 is a horizontal counter, 24a to 24d are decoders, 26a
26d are set / reset flip-flops, 28a and 28b are 1/2 frequency divider circuits, 30 is an inverting circuit, 32a
And 32b are differentiating circuits.

H is a horizontal synchronization rate signal, V is a vertical synchronization rate signal, and fs is a reproduction clock. Vertical counter 20, horizontal counter 22, decoders 24a to 24
d, set / reset flip-flops 26a to 26d
Are a vertical effective area signal VEA, a vertical effective upper half area signal VEUA, and a vertical effective lower half area signal VE for supplying these signals to the AND gates 18a to 18c.
A DA and a horizontal effective area signal HEA are respectively generated, and outputs of the AND gates 18a to 18c are supplied to A / D converters 6a and 6b and FIFO memories 8a and 8b.

The 1/2 frequency dividing circuit 28b, the inverting circuit 30, and the differentiating circuits 32a and 32b respectively provide a write reset signal WRS and a read reset signal RRS for supplying the FIFO memories 8a and 8b from the vertical synchronizing rate signal V. Occur.

The video input switch 2 constitutes a selection means, the FIFO memories 8a and 8b constitute a memory means, and a low-pass filter including the FIFO memories 8a and 8b.
The (LPF) 4a, 4b and the means for storing the video signal sampled by the A / D converters 6a, 6b in the memory means as a series of pixel data.

Similarly, a flip-flop (F / F) 10, a D / A converter 12, a low-pass filter (LPF) 14, and a synchronous component adder 16 including FIFO memories 8a and 8b.
Constitutes means for extracting a compressed data string from the memory means as a single video signal, and AND gates 18a to 18a-1
8c, vertical counter 20, horizontal counter 22, decoders 24a to 24d, set / reset flip-flop 26
a to 26d, 1/2 frequency dividing circuits 28a and 28b, inverting circuit 30, and differentiating circuits 32a and 32b constitute control signal generating means.

According to the present invention, the four types of input video signals # 1 to # 4 are divided into two groups, and the first group of two types of video signals # 1 and # 2 are sampled at odd-numbered horizontal scanning lines. Is divided into a video signal # 1 to be sampled and a video signal # 2 to be sampled for the even-numbered video signal, and another set of two types of video signals # 3 and # 4 of the second group is made to be a total of four types. . At the time of display, input video signals of horizontally adjacent screens on the monitor are put into the same group, and after compression, the input video signals displayed in the first half of the horizontal scanning lines are sampled at odd-numbered horizontal scanning lines. . The same effect can be obtained even if the input video signal displayed in the first half is an even number and the input video signal displayed in the second half is an odd number.

First, for example, an input video signal # 1 displayed in the first half of a horizontal scanning line after compression is continuously sampled for one horizontal scanning line and stored in the memory 8a. Next, the input video signal is switched, and the input video signal # 2 to be displayed in the latter half after compression is continuously sampled for one horizontal scanning line, and is stored in the memory 8a.
To save. The above operation is repeated for one field period (for one screen), and a data string in which two types of input video signals are alternately switched on a horizontal scanning line basis is formed on one memory. By performing the above operation in two sets synchronously, four types of input video signals #
1 to # 4 are stored in two sets of memories 8a and 8b.

Next, in the first half between the vertical synchronization rates V, the above 1
All the input video signals # 1 to # 4 can be read by reading the memory 8a of the set in succession at a rate twice the sampling rate and reading the memory 8b in the second set continuously in the latter half of the vertical synchronization rate V. Are displayed simultaneously on a single monitor screen in a compressed format. That is, the video input signal is switched in units of horizontal scanning lines, stored in the memory after sampling, and continuously read out from the memory at twice the speed to generate a compressed video signal in units of horizontal scanning lines.

The video input switches 2a and 2b have a total of four input terminals and two output terminals. This switch 2
Since a and b are switched by the horizontal synchronization rate signal H, the video signals # 1 and # 3 pass first, and then the video signals # 2 and # 4 pass. Each output terminal signal of the switches 2a and 2b passes through low-pass filters (LPF) 4a and 4b, and becomes a signal having no high-frequency component causing aliasing distortion at the time of sampling. Low-pass filter (LPF) 4
The signals that have passed through a and b are digitized by the A / D converters 6a and 6b at the AND gate 18a for each clock limited by the horizontal effective area signal HEA and the vertical effective area signal VEA. This sampling clock has a frequency half that of the reproduction clock fs in order to perform compression. A pixel is generated for each sampling clock, but the pixel is generated from one type of continuous input video signal in one scanning line period.

The video signals digitized by the A / D converters 6a and 6b are written into FIFO memories 8a and 8b, respectively. The FIFO memories 8a and 8b have a read pointer and a write pointer, and are reset at the following timings. The vertical synchronizing rate signal V is frequency-divided by a 1/2 frequency dividing circuit 28b and further differentiated by a differentiating circuit 32a.
And the write pointer is initialized by the write reset signal WRS. Further, the output of the 1/2 frequency dividing circuit 28b is inverted by the inverting circuit 30, and the read pointer is initialized by the read reset signal RRS through the differentiating circuit 32b. In this manner, the read reset and the write reset are shifted by two periods of the vertical synchronization rate signal V, and the FIFO memory 8
Areas a and 8b are fixed to two fields.

The outputs of the FIFO memories 8a and 8b pass through a flip-flop (F / F) 10 for blanking generation, are converted into analog signals by a D / A converter 12, and a low-pass filter (LPF) 14 reduces high-frequency components. After the synchronous component is added by the synchronous component adder 16, the signal is sent to the monitor as a single video signal and displayed. FIG. 2 shows a display example.

The horizontal synchronizing rate signal H is counted, and a start signal and an end signal are generated by the decoders 24a to 24c from the output of the vertical counter 20 reset at the vertical synchronizing signal rate V, respectively. 26c, the vertical effective area signal VE
A, Create a vertical effective upper half area signal VEUA and a vertical effective lower half area signal VEDA. Further, the reproduction clock fs is counted, a start signal and an end signal are generated by the decoder 24d from the output of the horizontal counter 22 reset by the horizontal synchronization rate signal H, and the horizontal effective area signal HEA is generated by the set / reset flip-flop 26d. create.

The sampling of the A / D converters 6a and 6b and the writing to the FIFO memories 8a and 8b are performed by dividing the reproduction clock fs by the 1/2 frequency dividing circuit 28a, and by vertically outputting the output of the set / reset flip-flop 26a. This is performed according to an AND condition by the AND gate 18a between the effective area signal VEA and the horizontal effective area signal HEA output from the set / reset flip-flop 26d.

On the other hand, reading from the FIFO memory 8a in which the video signals # 1 and # 2 have been written is performed by the reproduction clock fs, the vertical effective upper half area signal VEUA output from the set / reset flip-flop 26b and the set / reset flip-flop 26d. This is performed according to an AND condition by the AND gate 18b with the output horizontal effective area signal HEA. Also, the FIF in which video signals # 3 and # 4 are written
Reading from the O memory 8b is performed by using a reproduction clock fs,
The vertical effective lower half area signal VEDA of the output of the set / reset flip-flop 26c and the horizontal effective area signal HEA of the output of the set / reset flip-flop 26d
And the AND condition by the AND gate 18c.

The vertical effective area signal VEA is between 1 and 254 in the count of the horizontal synchronization rate signal H, the vertical effective upper half area signal VEUA is between 1 and 127, and the vertical effective lower half area signal VEDA is between 128 and 254. , And the horizontal effective area signal HEA is output during the count value of the reproduction clock fs from 1 to 704.

Embodiment 2 Further, the difference between the two A / D converters 6a and 6b may be relatively large in a signal having a low luminance due to an error between the two A / D converters 6a and 6b, and may exceed the detection limit on the monitor. Therefore, as shown in FIG. 3, the A / D converters 6a and 6b used in units of two horizontal scanning lines are used.
, The errors of the A / D converters 6a and 6b can be averaged for each scanning line, and can be suppressed below the detection limit on the monitor. In FIG. 3, the A / D converter 6a,
6b, the horizontal synchronization rate signal H is set to 1 /
The video input switches 2c, 2d, the digital switches 34a, 3
By switching at 4b, the A / D converter is exchanged every two horizontal scanning lines. The video input switches 2c and 2d, the digital switch 34
a and 34b constitute exchange means.

Embodiment 3 In the case of black and white video, only the luminance component is sufficient, so the configuration shown in FIG. 1 may be used. However, in order to support full color, R, G, B or luminance and two types of differential signals (for example, The present configuration is applied to each of the three components such as a signal and a difference signal for blue), and the three components are executed in parallel. FIG.
An example of a circuit configuration corresponding to full color in which the present configuration is provided to each of the three components G and B is shown.

In each of the embodiments described above, the four-screen splitting apparatus for displaying four images on one screen in a 2 × 2 matrix is described. However, the present invention is not limited to this. Instead, by adding a series of circuit elements and changing the division ratio of the control signal, it is possible to realize a screen N division device that divides and displays N ² images in an N × N matrix.

[0032]

As described above, according to the first aspect of the present invention, in a screen dividing apparatus for dividing and displaying N ² images on one screen in an N × N matrix,
Selection means for dividing the video signals of various types into N groups, each of which is composed of N groups for displaying the video signals side by side, and sequentially selecting N video signals in parallel for each group at a horizontal synchronization rate; A memory means for storing data as data; and a memory means for sequentially sampling N video signals in parallel for each group one by one for each horizontal scan, and as a series of N sets of pixel data for the number of groups. And N sets of video signals are sequentially switched and read from the memory means at a rate N times the sampling rate and every 1 / N of the vertical synchronization rate, and the compressed data sequence is converted into a single video signal. And a control signal generating means for generating a signal for controlling the horizontal synchronizing signal, the vertical synchronizing signal and the reproduction clock, so that the luminance between the input video signals can be reduced. Even when the listening different, is divided into a matrix of N × N can be displayed on a single monitor without interact with N ² pieces of video signals with each other, switching the image data further in pixel units A / Since there is no need to perform D conversion, it is not necessary to use a high-speed A / D converter, and an effect such as being able to provide an inexpensive screen division device is obtained.

In the second invention of the present invention, the writing means includes N A / D converters for A / D converting a video signal.
In the case where a converter is included, an exchange means for sequentially replacing and using N A / D converters in order to average the conversion error of the A / D converter is provided. There are obtained effects such as provision of a screen division device characterized in that the conversion error of the converter is reduced.

According to a third aspect of the present invention, R, G,
Since each of the above-described units is provided for each of the three components of B, effects such as the provision of the above-described screen division device for performing color display can be obtained.

According to a fourth aspect of the present invention, since each of the above means is provided for each of the three components of luminance and two types of difference signals, the screen dividing apparatus for performing color display is provided as in the third aspect of the present invention. The effect of being able to provide is obtained.

In the fifth aspect of the present invention, the above N
The effect is obtained that the above-described screen splitting device can be provided that splits and displays four images on a single screen in a 2 × 2 matrix form.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a screen division device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a display example of the screen division device of FIG.

FIG. 3 is a diagram showing a partial configuration of a screen division device according to another embodiment of the present invention.

FIG. 4 is a configuration diagram of a screen division device according to still another embodiment of the present invention.

FIG. 5 is a diagram for explaining the operation of a conventional screen division device.

FIG. 6 is a diagram for explaining a problem of a conventional screen division device.

[Explanation of symbols]

2a to 2d Video input switches, 4a, 4b, 14
Low-pass filter (LPF), 6a, 6b A / D converter, 8a, 8b FIFO memory, 10 flip-flop (F / F), 12 D / A converter, 16 synchronous component adder, 18a-18c AND gate, 20 Vertical counter, 22 horizontal counter, 24a to 24d decoder, 26a to 26d set / reset flip-flop, 28a to 28c 1/2 frequency divider, 30 inverting circuit, 32a, 32b differentiating circuit, 34a, 34b Digital switch.

Claims (5)

[Claims] 1. A screen dividing apparatus for dividing and displaying N ² images in an N × N matrix on one screen, wherein N images for displaying N × N kinds of video signals are arranged side by side. Selecting means for dividing the video signals into N groups, and selecting N video signals in parallel for each group in order at a horizontal synchronization rate; memory means for storing the video signals as image data; Means for simultaneously sampling the N video signals successively and repeatedly for each horizontal scan and storing them in the memory means as a set of N sets of pixel data in the memory means; Means for sequentially switching and reading out N sets of video signals at twice the rate and every 1 / N of the vertical synchronization rate, and extracting a compressed data stream as a single video signal; a horizontal synchronization signal, a vertical synchronization signal, From the fine reproduction clock and control signal generating means for generating a signal for controlling the screen dividing device characterized by comprising a. 2. The writing means according to claim 1, wherein
An exchange means is provided which includes N A / D converters for performing D conversion, and which exchanges and uses the N A / D converters in order to average conversion errors of the A / D converters. 2. The screen division device according to claim 1, wherein: 3. The screen dividing apparatus according to claim 1, wherein each of the three components of R, G, and B is provided with the respective means to perform color display. 4. The screen dividing apparatus according to claim 1, wherein each of the means is provided for each of three components of luminance and two kinds of difference signals to perform color display. 5. The screen division device according to claim 1, wherein the screen division device is a screen division device for dividing and displaying four images in a 2 × 2 matrix on one screen. apparatus.