JPH0998574A - Power supply circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress overcurrent in starting or switching from absence recording mode to television mode by applying a bias voltage continuously to a detection means when the oscillation frequency of a signal for controlling a switching means exceeds a predetermined frequency. SOLUTION: When an FET 6 is turned on to generate a flyback voltage in the primary winding 4, a flyback voltage is also generated simultaneously in the secondary winding 8 and a forward bias voltage is applied to secondary rectifier diodes 11, 14, 17. The voltage is smoothed through smoothing capacitors 12, 15, 18 and outputted as a DC power supply voltage 13, 16, 19. A bias voltage is applied continuously to a detection means, i.e., an overcurrent detection terminal 48, when the oscillation frequency of a signal for controlling a switching means, i.e., transistors 55, 56, exceeds a predetermined frequency. According to the circuitry, overcurrent can be suppressed in starting or switching from absence recording mode to television mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply circuit used in a television receiver or the like.

[0002]

2. Description of the Related Art FIG. 3 shows the configuration of a self-excited flyback converter as an example of a conventional switching power supply.

In FIG. 3, 1 is a power supply voltage obtained by rectifying and smoothing a commercial AC power supply, 2 is a voltage smoothing electrolytic capacitor, 3 is a transformer, 4 is a primary side winding of the transformer 3, 5 is a control circuit of a switching power supply, 6 is a switching element using a field effect transistor (hereinafter referred to as FET), 7 is a photocoupler, 8 is a secondary winding of the transformer 3, 9 is a relay, 10 is a diode, 11, 14, and 17 are secondary of the transformer 3. Diodes for rectifying the voltage generated in the side winding, 12, 15,
18 is an electrolytic capacitor for smoothing the voltage rectified by the rectifying diodes 11, 14, 17 respectively, 13, 16, 19
Is a DC output voltage on the secondary side, 20 is an error amplifier, 21, 2
2 is a current limiting resistor, 23 and 24 are zener diodes for stabilizing the voltage at the output 19, 25 is a transistor for switching the stabilizing output, 26, 27 and 2
8 is a resistor, 29 is an electrolytic capacitor, 30 is a control signal from a microcomputer, 31 is a resonance capacitor connected between the drain and source terminals of the FET 6, 32 is a minute resistor for detecting the current flowing in the FET 4, 33, 34 Is a voltage dividing resistor, 35 is a noise removing capacitor, 36 is a gate resistance of the FET 6, 37 is a bias winding of the transformer 3, 38 is a diode for rectifying the voltage generated in the bias winding 37, 39 is a noise removing resistor, Reference numeral 40 is an electrolytic capacitor that smoothes the voltage rectified by the diode 38, 41 and 42 are resistors and capacitors that form a delay integrating circuit, 43 is an overvoltage detection zener diode, 44 is a starting resistor, and 4 is a starting resistor.
5, 46 are resistors for soft start at startup and electrolytic capacitors, 47 is an output terminal for driving the FET 6 of the control circuit 5,
Reference numeral 48 is an overcurrent detection input terminal of the control circuit 5, 49 is a transformer reset detection input terminal of the control circuit 5, 50 is a feedback terminal of the control circuit 5, 51 is a ground terminal of the control circuit 5, and 52 is overvoltage detection of the control circuit 5. An input terminal, 53 is a power supply voltage input terminal of the control circuit 5, and 54 is a G of the power supply voltage 1.
The ND terminal and the inverted triangle in the figure are marks of the primary side GND.

In FIG. 3, the voltage of the secondary side output 13 is 14
It is 0 V, and a deflection / high voltage circuit is connected as a load. When the relay 9 is on, voltage stabilization is performed at the output 13, the deflection / high voltage circuit operates, and it is a normal mode in which the user can listen to television (hereinafter referred to as television mode). The voltage of the secondary side output 19 is 14V, and a signal processing circuit or the like is connected as a load. When the relay 9 is off, the high voltage / deflection circuit does not operate because the output 13 is off, but voltage stabilization is performed at the output 19 and 140 V.
The rest of the output voltages are generated, satellite broadcasting is received, a signal is output to an external connection terminal, and recording is possible on an externally connected VTR (hereinafter referred to as an answering machine mode). Switching between answering mode and TV mode
It can be easily performed by the user in the TV mode by setting it with a remote controller or the like.

Next, the operation in the television mode will be described with reference to FIG. FIG. 4 shows the waveform of each part in the television mode. At this time, the control signal 30
Is L, relay 9 is on, transistor 25
Is off.

In FIG. 4, (a) is the drive waveform VOUT of the FET 6 output by the control circuit 5, and (b) is the FET.
In the current waveform ID flowing through 6, the direction from the drain terminal to the source terminal is positive. In (c), the current ID is detected as a voltage by the minute resistor 32, divided by the resistors 33 and 34, and noise is removed by the capacitor 35 to detect the overcurrent.
Is inputted to the control circuit 5. The voltage waveform VCL inputted to the circuit is (d) is the drain-source terminal voltage VDS of the FET 6, (e) is the output voltage VS of the bias winding 37, and (f) is integrated by the integrator circuits 41 and 42 into the control circuit 5. It is an input voltage waveform VDL. When VOUT becomes H at time t1, FET6 turns on and the current ID
Begins to flow. At that time, a magnetic flux is generated in the transformer 3 by the primary current flowing in the primary winding 4 to accumulate energy, and at the same time an induced voltage is also generated in the secondary winding 8 of the transformer 3. , 14 and 17 are configured to generate an induced voltage in the direction of reverse bias, so that the secondary side current does not flow. At this time, an induced voltage is also generated in the bias winding 37 at the same time, but since it is configured so as to be generated in a phase opposite to VOUT, VS becomes a negative voltage at this time and passes through the integrating circuits 41 and 42 to the reset detection terminal. The voltage waveform VDL input to is clamped at 0V by the clamp circuit built in the control circuit 5. When the ON period determined by the control circuit 5 ends, VOUT becomes L at time t2 and the FET 6 turns off. When the FET 6 is turned off, a flyback voltage is generated in the primary winding 4 and at the same time, a flyback voltage is also generated in the secondary winding 8 and a voltage is forward biased to the secondary side rectifying diodes 11, 14, 17. Since it is applied, the energy stored in the transformer 3 is released as a secondary current through the secondary winding 8, is smoothed by the smoothing capacitors 12, 15, 18 and is output as the DC power supply voltage 13, 16, 19. . At this time, the flyback voltage VS generated in the primary side bias winding 37 has a waveform like VDL by the integrating circuits 41 and 42 and is input to the reset detection terminal 49. Time t3
When all the energy accumulated in the transformer 3 is released as a secondary current, the flyback voltage induced in the secondary winding 8 is inverted and the secondary side rectifying diodes 11, 1
Since 4 and 17 are reverse biased, the secondary current is turned off.
The flyback voltage generated in the primary winding is also inverted,
The energy stored in the resonance capacitor 31 is released and starts to resonate with the inductance of the primary winding 4,
The drain-source voltage VDS of the FET 6 decreases as shown in (d). At this time, by setting the integration constants 41 and 42 so that VDL becomes 0 V at time t4, the control circuit 5 turns on at time t4, and VOUT is output as H. The operation after VOUT becomes H is the same as the operation from time t1.

Next, the operation of stably controlling the output voltage in the television mode will be described. The error amplifier 20 has a built-in reference voltage. If the power supply voltage 13 is lower than the reference voltage, the current flowing through the light emitting diode of the photocoupler 7 decreases, the base current of the light receiving side transistor decreases, and the collector current also decreases. When the collector current, that is, the current IFB flowing out from the feedback terminal 50 decreases, the control circuit 5 extends the ON period of VOUT to increase the current flowing in the FET 6 and increase the energy stored in the transformer 3 per unit time. At this time, the current flowing through the secondary winding also increases, energy is stored in the electrolytic capacitor 12, and the output voltage 13 rises. The output voltage 13 is the error amplifier 20.
When it becomes higher than the reference voltage of, the output voltage 13 is lowered by the operation which is completely opposite to the above. Output voltage 1
Even if the voltage of 3 fluctuates, the voltage is controlled to be always constant.

Next, the operation of the answering machine mode will be described with reference to FIG. FIG. 5 shows the waveform of each part in the answering machine mode. At this time, the control signal 30 is H, the relay 9 is off, and the transistor 25 is on. In FIG. 5, (a) to (f) show waveforms at the same locations as in FIG. The basic operation is the same as the TV mode, but 140V is not generated at the output 13 because the relay 9 is off, and the power consumption is lower than that in the TV mode because the deflection / high voltage circuit does not operate.
The difference is that the ON period is small as shown by VOUT in FIG. In general, if the ON period is short, the energy accumulated in the transformer 3 is also released in a short time, the OFF period becomes short, and the oscillation frequency becomes high, which makes it difficult to take measures against interference. The minimum value of the off period is set in advance in the circuit 5 so that the off period does not become smaller than the set value even when the load is light as in the answering machine mode. The operation after turning off will be described. When the FET 6 is turned off at time t2, a voltage is generated at the secondary side outputs 16 and 19 as in the above-described operation. At this time, since the energy stored in the transformer 3 is small, the flyback voltage induced in the secondary winding 8 is inverted when all the energy stored in the transformer 3 is discharged as a secondary current at time t3. Since the secondary side rectifying diodes 14 and 17 are reverse biased, the secondary current is turned off. The flyback voltage generated in the primary winding is also inverted, and the energy stored in the resonance capacitor 31 is released and starts to resonate with the inductance of the primary winding 4, so that the drain-source voltage VDS of the FET 6 is (D)
It vibrates as shown in. At the same time, the input voltage VDL of the reset detection terminal 49 also falls below the threshold value, but since it is earlier than the preset minimum off period, the control circuit 5 continues to output L to VOUT. When the minimum off period ends, time t
It turns on at 4 and H is output to VOUT. VOUT is H
After that, the operation is repeated from time t1.

Next, the operation for stably controlling the output voltage in the answering machine mode will be described. Since the relay 9 is turned off and the output 13 is 0V, no current flows in the error amplifier 20, and the current of the photocoupler 7 flows from the output 19 through the resistor 22, the Zener diode 23, the photocoupler 7, the Zener diode 24, and the transistor 25. . At this time, the Zener voltages of the Zener diodes 23 and 24 and the forward voltage of the light emitting diode 7 are 3.3 V and 10 V, respectively.
If V and 0.7 V are set, the output 19 can be stabilized at 14 V by stacking them. The stabilizing operation of the control circuit 5 when the output 19 is higher or lower than 14V is the same as that in the above-mentioned television mode, but the load connected to the output 19 is the signal processing circuit, and the load current is The output voltage 19 is sufficiently stabilized because there is almost no load change at several hundred mA.

Next, the overcurrent protection operation will be described with reference to FIG. When VOUT becomes H at time t1 and the FET6 is turned on, a current ID starts to flow in the FET6, and the voltage waveform VCL is input to the overcurrent detection terminal 48 corresponding to the ID. Now, when ID continues to rise and VCL reaches the threshold value Vth at time t2, the control circuit 5 immediately pulls down VOUT to L. When VOUT becomes L, FET6 turns off, so the current ID also turns off, and the current does not continue to flow and the FET does not continue to flow.
6 is protected from damage due to overcurrent. It should be noted that this operation operates for each pulse of VOUT and does not stop the operation of the power supply. Therefore, even if the load on the secondary side is momentarily overloaded, the operation continues without any problem. FIG.
In order to explain the overcurrent protection circuit, it is drawn that VCL reaches Vth, but VCL does not reach Vth in the normal load range.

Next, the operation at startup will be described with reference to FIGS. 6 and 7. Figure 6 shows the waveform of each part at startup,
(A) is a drive waveform VOUT of the FET 6 output by the control circuit 5, and (b) is a current waveform ID flowing through the FET 6, and the direction of flow from the drain terminal to the source terminal is positive. (C) is a voltage waveform VC which detects the current ID as a voltage by the minute resistor 32, divides it by the resistors 33 and 34, removes noise by the capacitor 35, and is input to the overcurrent detection terminal 48.
L and (d) are voltage waveforms VDL integrated by the integrating circuits 41 and 42 and input to the control circuit 5. Figure 7 shows
The waveforms of the respective parts when the answering machine mode is switched to the television mode, and (a) to (d) are the same as those in FIG. 6. First, description will be made with reference to FIG. At the time of startup, the relay 9 is turned off by the control signal 30 from the microcomputer, and the transistor 25 is turned on. Therefore, the voltage is stabilized by the output 19. As the power supply voltage 1 rises, the voltage VCC inputted to the power supply voltage input terminal 53 of the control circuit 5 also rises. When Vcc reaches the starting voltage of the control circuit 5, the control circuit 5 starts operating, and when H is output to VOUT at time t1, the FET 6 turns on and the current ID starts to flow. The operation until turning off at time t2 is the same as in the above-described steady state. FET
When 6 is turned off, a flyback voltage is generated in the primary winding 4, the secondary winding 8, and the primary side bias winding 27. Then 1
The flyback voltage generated in the secondary side bias winding 37 has not yet risen sufficiently and the voltage V which is input to the reset detection terminal 49 of the control circuit 5 through the integrating circuits 41 and 42.
DL has not yet reached the threshold as shown in FIG. 6 (d).
Since the control circuit 5 cannot detect the reset of the transformer from VDL and cannot set the off period by VDL, the minimum off period preset in the control circuit 5 is turned on at time t3 as the off period at this time. At this time, the transformer 3 does not completely discharge the stored energy, and turns on while storing the energy.
When VOUT becomes H at time t3, the current ID flows through the FET 6 and energy is further accumulated in the transformer 3. However, since energy remains in the transformer 3 as described above, the transformer 3 is in a magnetic saturation state, The inductance of 3 decreases, and an excessive current flows through the primary winding 4 and the FET 6. The ID waveform at this time rises sharply,
A steep voltage waveform is input to the overcurrent detection terminal 48 as shown in FIG. 6C, the overcurrent is prevented by the above-mentioned overcurrent protection operation, and the terminal turns off at time t4. At this time, the control circuit 5 is configured to output a constant voltage from the control circuit 5 to the overvoltage detection terminal 52 at the same time as starting.
5. Since the bias voltage Vbias is applied to the overcurrent detection terminal 48 via the electrolytic capacitor 46, the threshold for overcurrent detection apparently decreases and the overcurrent can be suppressed to a small level (this The operation will be referred to as a soft start hereinafter). Since the electric charges accumulated in the electrolytic capacitor 46 are discharged by the resistors 32, 33, 34, the bias voltage applied to the overcurrent detection terminal 48 gradually decreases and becomes zero in a few msec. The operation after turning off is a repetition of the above operation. The magnetic saturation state of the transformer 3 continues until the voltage VDL input to the reset detection terminal 49 gradually rises and exceeds the threshold value. When the voltage exceeds the threshold value, the off period is set until VDL becomes L. That is, it spreads during the period until the transformer 3 finishes discharging energy to the secondary side. The operation after VDL exceeds the threshold value is the same as in the answering machine mode. After the secondary side voltage is stabilized, initialization data is sent from the microcomputer to the signal processing circuit, and the control signal 30 is set to L and the relay 9 is turned on after the signal processing circuit stabilizes after several hundred msec. At the same time, the transistor 25 is turned off, and the output 13
That is, 140V is turned on. The operation at this time is basically the same as that at the time of starting, but the overcurrent detection terminal 48
Since the bias voltage applied to the control circuit 5 is generated only when the control circuit 5 is started, the soft start is not applied at this time. The operation at this time will be described with reference to FIG. When the relay 9 is turned on and then turned on for the first time at time t1, the control circuit 5 extends the ON period to allow the current to flow through the FET 6 and turns off at time t2 in order to increase the secondary side output 13. At this time, since the voltage of the secondary side output 13 is still zero, the voltage of the primary side bias winding 37 also decreases according to the winding ratio, and the input voltage VDL of the reset detection terminal 49 does not reach the threshold value. Therefore, the control circuit 5 is turned on at t3 after the preset minimum off period as in the start-up, so that the transformer 3 enters the magnetic saturation state and the current ID flowing through the FET 6 flows sharply.
As described above, since the soft start is not applied at this time, the peak value of ID becomes larger than that at the start. This state continues until VDL gradually rises and exceeds the threshold,
When the threshold value is exceeded, the off period is set until VDL becomes L, that is, until the transformer 3 finishes discharging energy to the secondary side. The operation after VDL exceeds the threshold value is the same as in the TV mode. Although the start-up has been described above, the same operation as above is performed when the user operates the remote controller or the like to switch from the recorded message mode to the television mode.

[0012]

However, in the above-mentioned configuration, since the soft start cannot be heard at the time of start-up and at the time of switching from the recorded mode to the television mode, the FET 6 is not used.
There is a problem that the current flowing in the FET 6 becomes large and stress is applied to the FET 6 to destroy it in the worst case.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a power supply circuit capable of suppressing an overcurrent at the time of start-up and at the time of switching from the recorded mode to the television mode.

[0014]

To achieve the above object, a television power supply circuit of the present invention detects a transformer, a switch means for controlling a current flowing through the transformer, and a current flowing through the switch means. Means for suppressing the current flowing through the switch means when the current flowing through the switch means exceeds a predetermined value, and the oscillation frequency of the signal for controlling the switch means becomes equal to or higher than a predetermined frequency. And a means for continuously applying a bias voltage to the detection means.

[0015]

With the above structure, it is possible to suppress an overcurrent at the time of start-up and at the time of switching from the recording mode to the television mode, and it is possible to prevent the destruction of the FET.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a self-excited flyback converter which is an embodiment of the present invention. 1 in this figure
The steps from to 54 are the same as those of the conventional example shown in FIG. 55,
56 is a transistor, 57, 58 and 59 are resistors, 60 is a capacitor, 61, 62 and 63 are resistors, and 64 is a diode.

The operation will be described with reference to FIG. FIG.
Shows the waveforms of various parts at the same timing as in FIG. 7 when a large current flows through the FET 6 at the time of start-up and when switching from the recording mode to the television mode.

In FIG. 2, (a) is a drive waveform VOUT of the FET 6 output by the control circuit 5, and (b) is FE.
The direction of current flowing from T6 to the source terminal is positive in the current waveform ID. (C) is the current ID
Is detected as a voltage by the minute resistor 32, divided by the resistors 33 and 34, noise is removed by the capacitor 35, and the overcurrent detection terminal 4
The voltage waveform VCL input to 8 is (d) is the integration circuit 41,
Voltage waveform V integrated by 42 and input to the control circuit 5
DL, (e) is the collector voltage VA of the transistor 55 and VOUT of (d) is inverted and waveform shaped. (F) is the terminal voltage VB of the capacitor 60 and VA of (e) is resistor 5
(G) is the base voltage VC of the transistor 56 and VB of (f) is added to the base of the transistor 56 via the resistor 61. (h)
Is the emitter voltage VD of transistor 56. FIG.
The operation after turning off at time t2 will be described. At the time t2, when VOUT becomes L, VA becomes H because it is its inversion, and it is integrated by the resistor 59 and the capacitor 60 and gradually rises like VB. The voltage of VB is applied to the base of the transistor 56 via the resistor 61, and the transistor 56 turns on when the threshold value of the transistor is exceeded. Transistor 56 is at time t
When turned on at 2 ', the collector voltage is divided by the resistors 62 and 63 to the emitter of the transistor 56, and a voltage such as VD is output. Since this VD is added as Vbias to the overcurrent detection terminal 48 via the diode 64,
CL rises stepwise as shown in (c). If the transformer 3 is turned on at time t3 in this state, as in the case of FIG. 7 of the conventional example, the transformer 3 is magnetically saturated and ID rises sharply as shown in (b), but in the conventional example of FIG.
As is the case with the addition of, the apparent overcurrent detection threshold is lowered and the overcurrent is suppressed. The value of the resistor 59 and the capacitor 60 is set so that VB is discharged and the voltage drops until it is turned off at time t4, but it does not drop below the threshold value of the transistor. After that, VD maintains H until VDL gradually rises and exceeds the threshold value, and the overcurrent of ID continues to be suppressed. VDL at time tn
Exceeds the threshold value, the off period is extended until the transformer 3 finishes discharging energy at time tn + 1 as described in the explanation at the time of startup. When VDL becomes L at time tn + 1, VOUT is turned on and VB is discharged, so that the voltage gradually decreases. When VB falls below the threshold value of the transistor 56 at time tn + 1 ', the transistor 56 is turned off and V
Since D becomes L, the bias voltage Vbi added to VCL
as becomes zero. At this time, since the magnetic saturation of the transformer 3 has disappeared, VCL increases from time tn + 1, but at time tn + 1 ′, the bias voltage Vbias becomes zero, so that VCL reaches the threshold value and overcurrent protection does not work. Absent. The operation is the same as that described in the television mode thereafter.

In FIG. 2, even before time t2, VF becomes H and a bias voltage is applied to VCL. At this time, however, the load is light and the ID is small in the recording mode, so that the overcurrent protection does not work. Also, in the normal TV mode, since the ON period is extended, VD is discharged during the ON period, and VD
F does not continue to be high, VCL does not reach the threshold value, and unnecessary overcurrent protection does not work. After that, the same operation as that described in the television mode is performed.

The oscillation frequency is about 250k in the absence mode.
Since the frequency of both Hz and TV mode is 80 to 120 kHz and the frequency of both modes does not change continuously, even if there are variations in the values of the resistor 59 and the capacitor 60, continuous only in the absence recording mode. Then, the transistor 56 can be turned on and Vbias can be continuously supplied to VCL.

In general, the control circuit 5 is integrated into an IC, and if the protection circuit of the present invention is formed in the IC, no increase in cost will occur.

In addition, since the soft start can be applied by the protection circuit of the present invention even at the time of starting, the conventional soft start resistor 45 and electrolytic capacitor 46 of FIG. 3 can be eliminated and the cost can be reduced.

In the present embodiment, the charging / discharging of the capacitor is used to detect the oscillation frequency, but any circuit other than the capacitor may be used as long as the circuit can detect the oscillation frequency. It goes without saying that, for example, a structure in which a frequency counter is used and Vbias is added to VCL by the switch means when the frequency exceeds a preset frequency is of course acceptable.

[0025]

According to the television power supply circuit of the present invention, overcurrent can be suppressed at the time of start-up and at the time of switching from the recording mode to the television mode, and the safety and reliability of the power supply can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a power supply circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms of the power supply circuit in the embodiment.

FIG. 3 is a configuration diagram of a conventional power supply circuit.

FIG. 4 is a diagram showing operation waveforms of a conventional power supply circuit.

FIG. 5 is a diagram showing operation waveforms of a conventional power supply circuit.

FIG. 6 is a diagram showing operation waveforms of a conventional power supply circuit.

FIG. 7 is a diagram showing operation waveforms of a conventional power supply circuit.

[Explanation of symbols]

 1 Power Supply Voltage 2 Electrolytic Capacitor 3 Transformer 4 Primary Winding 5 Control Circuit 6 FET 7 Photocoupler 8 Secondary Winding 9 Relay 10 Diode 11, 11, 17 Rectifying Diode 13, 16, 19 Power Supply Voltage 20 Error Amplifier 23, 24 Zener 25 Transistor 30 Control Signal 31 Resonance Capacitor 32 Current Detection Micro Resistor 37 Bias Winding 48 Overcurrent Detection Terminal 49 Reset Detection Terminal 51 GND Terminal 52 Overvoltage Detection Terminal 54 GND Terminal 55, 56, Transistor 60 Diode

Claims (1)

[Claims] 1. A transformer, a switch means for controlling a current flowing through the transformer, a means for detecting a current flowing through the switch means, and a switch means for the switch means when the current flowing through the switch means exceeds a predetermined value. A means for suppressing a flowing current and a means for continuously applying a bias voltage to the detection means when the oscillation frequency of a signal for controlling the switch means becomes equal to or higher than a predetermined frequency. Power supply circuit.