JPH0998308A - Field discrimination device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To guarantee stable and consecutive execution of parity discrimination of fields. SOLUTION: A field discrimination circuit 22 conducting parity discrimination of field and providing an output of a binary level field discrimination signal is monitored by a field discrimination monitor circuit 24. The field discrimination monitor circuit 24 collates a field inversion signal whose level is inverted for each field and outputted from a field inversion circuit 23 with the field discrimination signal and outputs selectively the field discrimination signal when they are in phase or outputs selectively the field inversion signal when they are in opposite phase in place of the field discrimination signal. Thus, the stable and consecutive execution of field discrimination is guaranteed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field discriminating apparatus which collates a field discriminating signal with a field inversion signal so that stable and continuous field discrimination can be executed.

[0002]

2. Description of the Related Art In-vehicle television receivers used for displaying maps on navigation devices often use a video display device for displaying a video on a liquid crystal display panel. In a liquid crystal display panel of a liquid crystal display device of this type, liquid crystal elements are arranged in a line in a horizontal and vertical direction in accordance with a pixel arrangement of, for example, 320 × 240 dots. The RGB three-primary color image data is supplied to the display of the liquid crystal display panel through the image processing circuit, and the composite sync signal which is a composite of the horizontal sync pulse and the vertical sync pulse is supplied to the drive circuit for two-dimensionally scanning the liquid crystal display panel. While being supplied directly, it is also supplied to the field discrimination circuit and the scanning line thinning circuit. This is because it is necessary to thin out the number of scanning lines of the television signal in accordance with the pixel arrangement of the liquid crystal display panel. For example, the PAL system or the SE system in which the number of scanning lines in one field is 312.5.
In the case of a CAM system television signal, it is necessary to perform processing such as line thinning at a rate of one in seven lines. However, in the interlaced scanning method in which one frame is composed of two fields, if the scanning lines at the same position are thinned out in the even field and the odd field that form one frame, the loss of visual information will occur in the same position. Concentrated
It has been known that the image quality is deteriorated, and therefore, it is common to make the thinning points of the scanning lines different between the even field and the odd field.

From such a background, a field discriminating circuit for discriminating an even field and an odd field from a synchronizing signal included in a video signal is indispensable. In the NTSC signal, when one of the two fields forming one frame has completed vertical scanning, the horizontal scanning period is normally 1
Fields ending with / 2 are called odd fields, and fields when the horizontal scanning period is completely ending are called even fields for distinction. Therefore, in the conventional field discriminating circuit 1 shown in FIG. 3, the odd field is started at the first edge of the first equalizing pulse, while the even field is set to 2 when the vertical scanning is restarted.
Focusing on the fact that it is started at the first edge of the th equalizing pulse, the field discrimination is performed. That is, since the odd field and the even field can be distinguished by distinguishing the level of the horizontal sync pulse at the falling edge of the vertical sync pulse, the composite sync signal waveform is first integrated by the integrating circuit 2. This integration circuit 2
Is charged in the period between sync pulses and discharged in the pulse width period of the sync pulse itself. Therefore, during the horizontal synchronizing pulse period in which the horizontal synchronizing pulses are arranged at regular time intervals, the flip-flop circuit 3 that performs a latch operation using the synchronizing pulse as a clock compares the output of the integrating circuit 2 with the threshold voltage to determine the magnitude. Continues to be cleared by the output of 4. However, FIG.
When the vertical blanking period shown in (D) is reached, the pulse period of the equalizing pulse is shortened to about 1/2 of the pulse period of the horizontal synchronizing pulse so far, so that the terminal voltage of the integrating circuit 2 becomes equal to that of the comparator 4. Will not exceed the threshold voltage of
The polarity of the Q output of the flip-flop circuit 3 is inverted every equalizing pulse. Since the horizontal scanning period of the odd-numbered field ends in half the normal period, that is, the same period as one equalizing pulse, the polarity change mode of the Q output of the flip-flop circuit 3 is reversed between the odd-numbered field and the even-numbered field. It will be. In other words, the level of the Q output of the flip-flop circuit 3 at the falling edge of the vertical sync pulse differs between the even field and the odd field. Therefore, here, the Q output of the flip-flop circuit 5 is latched by the latch circuit 6 which uses the vertical synchronizing pulse separated by the vertical synchronizing separating circuit 5 from the composite synchronizing signal as a clock, and the latched output is inverted to output the output transistor 7 of the output transistor 7. It is configured to output from the emitter. The field discrimination signal output from the emitter has a high level in an odd field and a low level in an even field.

[0004]

The conventional field discriminating circuit 1 described above is premised on a standard signal in which equalized pulses are properly inserted. Therefore, when a weak signal is received in an area where the electric field strength is weak, When receiving a non-standard signal such as a non-interlaced signal which is disturbed by external noise, the field discrimination circuit 1 malfunctions,
There is a problem that the field discrimination signal is inaccurate and is not stable, and as a result, the interlace operation and the non-interlace operation are not normally performed. In particular, in the case of display by a liquid crystal display panel in which the number of display dots is less than the number of scanning lines, the number of scanning fields of the original video signal should be thinned out even if the odd fields and the even fields should be different. By mistakenly discriminating that the field is an odd field or an even field, the same scanning line portion is actually thinned repeatedly, and, for example, the Roman letter "E" is displayed as "F". As a result, the original image information is lost, and the quality of the displayed image is easily impaired. On the other hand, in order to cope with the loss of field information associated with such a video signal, a field discriminating apparatus which corrects the lost field information and outputs a pulse having a frequency of 1/2 of the vertical synchronization pulse as a field pulse is provided. ,
It is disclosed in Japanese Patent Application Laid-Open No. 4-53365, "Field determination correction device".

As shown in FIG. 5, the field discriminating apparatus 11 pays attention to the fact that the field discriminating signal output from the field discriminating circuit 1 is fixed at one level when the field information is missing. The output of the discrimination circuit 1 is supplied to the data input terminal of the flip-flop circuit 12 which uses the clock as a clock, while the vertical sync separation circuit 13 is supplied.
The vertical synchronizing pulse extracted by is divided by a 1/2 divider circuit 14, and the vertical synchronizing pulse delayed by a certain time is supplied to a data input terminal by a delay circuit 15, and the Q output of the flip-flop circuit 12 is used as an alternative field. 1/2 to be the discrimination signal
This is used to specify the polarity of the divided vertical synchronizing pulse. This polarity designation is performed by the 2-input 1-select output type selection circuit 16, and the output of the 1/2 frequency divider circuit 14 is inverted in polarity by the inverter circuit 17 and supplied to its A input terminal.
The output of the 1/2 divider circuit 14 is directly supplied to the B input terminal. Field information is missing, field discrimination circuit 1
When the field discrimination signal output by is fixed at one level, the flip-flop circuit currently holds 1 /
The frequency-divided vertical sync pulse is output to the selection input terminal S of the selection circuit 16. Based on the output of the flip-flop circuit 12, the selection circuit 16 is the same as the output of the flip-flop circuit 12 among the divided vertical synchronizing pulses input from the A terminal and the B terminal, which are either forward rotation or inversion. A polarity signal is selected and output as a substitute field discrimination signal.

As described above, in the field discriminating apparatus 11 having the above-described configuration, when the field information is lost and the field discriminating signal output from the field discriminating circuit 1 is fixed at one level, the flip-flop circuit 12 is currently held. Selective circuit 16 for selecting 1/2 divided delayed vertical sync pulse
Output to the selection input terminal S of the
Of the frequency-divided vertical synchronizing pulses for normal rotation or inversion inputted to the terminal, the flip-flop circuit 12
The signal having the same polarity as that of the output of FIG. 6 is selected and output as the alternative field discrimination signal. However, in reality, when the Q output of the flip-flop circuit 12 is fixed at the level when an abnormality occurs, the signal shown in FIG. As shown in A) to (F), the output of the selection circuit 16 is not inverted for each field, and there is a problem that the field discrimination is no longer useful.

The present invention has been made in view of the above conventional problems, and an object of the present invention is to appropriately back up the erroneous discrimination of the field discriminating circuit and enable a normal image display.

[0008]

In order to solve the above problems and achieve the above object, the present invention relates to a video signal in which an even field and an odd field form one frame,
A field discriminating circuit for discriminating even and odd fields based on the characteristics of the equalizing pulse included in the vertical blanking period of the composite synchronizing signal and outputting a field discriminating signal of binary level, and a vertical synchronizing circuit contained in the composite synchronizing signal. A field inversion circuit that toggles by a pulse and outputs a field inversion signal whose level is inverted for each field is collated with the field discrimination signal and the field inversion signal, and if the state is in phase, the field discrimination signal is selectively output. However, it is characterized by comprising a field discrimination monitoring circuit for selectively outputting the field inversion signal as an alternative field discrimination signal in place of the field discrimination signal in a reverse phase state.

The present invention also provides an exclusive OR circuit in which the field discrimination monitoring circuit collates the field discrimination signal with the field inversion signal and outputs a field discrimination abnormality signal in a mutually opposite phase state, If the output of the exclusive OR circuit latches the abnormal field discrimination signal for a predetermined time, and the field discrimination signal and the field inversion signal are switched by the latch output of the latch circuit, and if the field discrimination abnormality does not occur, A selector switch for selectively outputting the field discrimination signal and selectively outputting the field inversion signal as an alternative field discrimination signal when a field discrimination abnormality occurs, or the latch circuit is configured to detect the field discrimination abnormality signal. The duration is timed and the duration is preset When beyond the field period, it is characterized in such that a timer to clear the field discrimination abnormal signal.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
2 will be described. FIG. 1 is a schematic circuit configuration diagram showing an embodiment of the field discriminating apparatus of the present invention, and FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG.

The field discriminating apparatus 21 shown in FIG.
The present invention is applied to a liquid crystal display device 31 for displaying an image by receiving GB data and a composite sync signal. A liquid crystal display panel 32 has an image processing circuit 33 for processing RGB signals and a liquid crystal display panel 32 according to the composite sync signal. A drive circuit 34 for two-dimensional scanning is connected. Further, a scanning line thinning circuit 35 for thinning the number of scanning lines according to the number of pixels of the liquid crystal display panel 32 is connected to the drive circuit 34, and a field discrimination signal necessary for thinning the scanning lines is supplied to the field discrimination device. It is configured to be supplied from 21.

The field discriminating device 21 performs a toggle operation by a field discriminating circuit 22 which performs even-odd field discrimination and outputs a binary-level field discriminating signal, and a vertical synchronizing pulse included in the composite synchronizing signal, thereby leveling each field. The field inversion circuit 23 that outputs a field inversion signal that inverts the field inversion signal is collated with the field inversion signal and the field inversion signal, and the field inversion signal is selected and output in the in-phase state, and the field inversion signal in the in-phase state. Is used as a substitute field discriminating signal instead of the field discriminating signal and is selectively output. The field inversion circuit 23
It is composed of a T flip-flop circuit in which the vertical synchronizing pulse is supplied to the trigger input terminal, and performs a toggle operation in which the polarity of the output is inverted each time the vertical synchronizing pulse is supplied to the trigger input terminal.

The field discriminating / monitoring circuit 24 collates the field discriminating signal with the field inversion signal, and outputs a field discriminating abnormal signal in a phase opposite to each other, and an output of the exclusive OR circuit 25. The latch circuit 26 that latches the field discrimination abnormality signal for a predetermined time, and the field discrimination signal and the field inversion signal are switched by the latch output of the latch circuit 26. When the field discrimination abnormality does not occur, the field discrimination signal is selectively output, When a field discrimination abnormality occurs, the selector switch 27 is configured to selectively output the field inversion signal as an alternative field discrimination signal. The latch circuit 26 has a built-in timer 26a that counts the duration of the field discrimination abnormality signal and clears the field discrimination abnormality signal when the duration exceeds a preset number of field periods (timer set time).

When the received video signal is a regular interlaced signal and the composite sync signal is not disturbed, the field discriminating circuit 22 operates normally, and the field discriminating signal output from the field discriminating circuit 22 and the field inversion signal. The field inversion signal output by the circuit 23 is shown in FIG.
As shown in the first half of the time axis of (B) and (C), they are in phase with each other, and the output of the exclusive OR circuit 25 is as shown in FIG.
It is at a low level as shown in (D). Therefore, as a matter of course, the output of the latch circuit 26 is also at the low level, the changeover switch 27 selects the field discrimination signal, and sends this to the scanning line thinning circuit 35.

On the other hand, when the received video signal is not a regular interlaced signal but a composite sync signal having irregularity or lack of equalization pulses, an abnormality occurs in the even / odd field discrimination in the field discrimination circuit 22. In this case, the field discriminating signal and the field inversion signal output from the field discriminating circuit 22 are in a state in which the opposite phase state and the in-phase state are repeatedly mixed with each other as shown in the second half of the time axis of FIGS. It will be. As a result, the output of the exclusive OR circuit 25, as shown in FIG. 2D, occasionally takes a low level but frequently exposes a high level indicating a field discrimination abnormality. As a result, as a matter of course, the output of the latch circuit 26 continues to be at the high level during the timer period, and the changeover switch 27 selectively outputs the field inversion signal instead of the field determination signal during that period. Therefore, the output of the changeover switch 27 becomes a normal field discriminating signal whose level is inverted in accordance with the even and odd fields not only in the normal state but also in the similar abnormal state.

As described above, the field discrimination device 21
Output of field discrimination circuit 22 and field inversion circuit 2
The output of FIG. 3 is collated to monitor whether there is a field discrimination abnormality, and if there is a field discrimination abnormality, the field inversion circuit 2
Since the field inversion signal which is the output of No. 3 is output instead of the field discrimination signal, when a weak signal is received in an area where the electric field strength is weak, or when non-interlaced signals such as non-interlaced signals disturbed by external noise are received. Even when the field discriminating circuit 22 causes a malfunction when a standard signal is received, the field inversion signal can be output instead of the erroneous field discriminating signal, thereby preventing an abnormal field discrimination. . Therefore, since the field discrimination is not accurate and stable as in the conventional case, the interlace operation and the non-interlace operation are not normally performed, and the liquid crystal display panel in which the number of display dots is less than the number of scanning lines is not required. When the display by 32 is performed, it is possible to accurately make the odd-numbered field and the even-numbered field different from each other in the positions where the scanning lines of the original video signal are thinned out. For this reason, for example, an odd field or an even field may be erroneously discriminated over several fields, and the same scanning line portion may be repeatedly thinned or the Roman letter "E" may be displayed as "F". As described above, it is possible to prevent the inconvenience that the original image information is unnecessarily lost and the quality of the displayed image is deteriorated, and it is possible to always display a stable image.

Further, the field discrimination monitoring circuit 24 can accurately execute the phase comparison of the field discrimination signal and the field inversion signal with the coincidence or non-coincidence of the levels of both signals, that is, the exclusive OR, and the field discrimination abnormality signal. Is latched for a predetermined time by the latch circuit 26 and used for switching the changeover switch 27. Therefore, even if the exclusive OR circuit 25 malfunctions due to external noise, the effect of the malfunction is within the latch period of the latch circuit 26. Therefore, it is possible to perform the field discrimination using the field discrimination signal as the first priority and the field inversion signal as the backup signal.

Further, since the latch circuit 26 includes the timer 26a, the latch time of the latch circuit 26 is accurately set to an integral multiple of the field period, and even if the exclusive OR circuit 25 malfunctions due to external noise, The effect of the malfunction can be suppressed within the period of several fields specified by the timer.

In the above embodiment, the NTSC signal has been described as an example, but the PAL signal or the S signal is used instead of the NTSC signal.
It goes without saying that the present invention can be applied to the case of handling ECAM signals. While NTSC signals consist of 525 scanning lines per frame, PAL signals and SECA
The M signal is composed of 625 scanning lines in one frame, but the process of forming the field discrimination signal is substantially the same except for the thinning control mode of the thinning circuit.

[0020]

As described above, according to the present invention,
The field discrimination circuit that performs even-odd field discrimination and outputs a binary level field discrimination signal is monitored by the field discrimination monitoring circuit, and toggles by the vertical synchronization pulse included in the composite synchronization signal, and the field inversion circuit outputs it. A field inversion signal that level-inverts for each field is collated with the field discrimination signal, and if the in-phase state is selected, the field discrimination signal is selectively output, and if in the in-phase state, the field inversion signal is used as the alternative field discrimination signal. The field discriminating circuit is configured to selectively output instead of the above, when a weak signal is received in an area where the electric field strength is weak, or when a non-standard signal such as a non-interlaced signal disturbed by external noise is received. The wrong field identification signal, even if The field inversion signal can be output as an alternative by this, and the field discrimination error can be prevented. Therefore, since the field discrimination is not accurate and stable as in the past, the interlace operation and non-interlace operation are normal. There is nothing that is not done in
In particular, when displaying with a liquid crystal display panel in which the number of display dots is less than the number of scanning lines, it is possible to accurately make the difference between the odd field and the even field in thinning out the scanning lines of the original video signal. By mistakenly distinguishing between odd field and even field over the field, the same scan line part is repeatedly thinned,
It is possible to prevent inconvenience such as displaying the letter “E” in the Roman alphabet as “F” and losing the original image information and impairing the quality of the displayed image. It has excellent effects such as video display.

According to the present invention, the field discriminating and monitoring circuit compares the field discriminating signal with the field inversion signal and outputs a field discriminating abnormal signal in a phase opposite to each other, and an exclusive OR circuit. Output of the sum circuit Latch circuit that latches the field discrimination abnormality signal for a predetermined time, and the field discrimination signal and the field inversion signal are switched by the latch output of the latch circuit, and if the field discrimination abnormality does not occur, the field discrimination signal is selected and output However, when a field discrimination abnormality occurs, the field inversion signal is selectively output as a substitute field discrimination signal, and a changeover switch is provided. Therefore, the phase comparison between the field discrimination signal and the field inversion signal is performed by comparing the levels of the two signals. Exactly with a disagreement or exclusive OR It can be, also because the field determination abnormality signal so as to provide the switching of the changeover switch by latching a predetermined time by the latch circuit,
Even if the exclusive OR circuit malfunctions due to external noise,
The effect of the malfunction can be suppressed within the latch period of the latch circuit, and it is possible to perform the field discrimination using the field discrimination signal as the first priority and the field inversion signal as the backup signal. .

Further, since the latch circuit measures the duration of the field discrimination abnormality signal and has a built-in timer for clearing the field discrimination abnormality signal when the duration exceeds a predetermined number of field periods, the latch circuit is latched. Even if the exclusive OR circuit malfunctions due to external noise, the latch time of the circuit can be accurately set to an integral multiple of the field period, and the effect of the malfunction can be suppressed within a few field periods specified by the timer. Produce an effect.

[Brief description of drawings]

FIG. 1 is a schematic circuit configuration diagram showing an embodiment of a liquid crystal display device to which a field discrimination device of the present invention is applied.

FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG.

FIG. 3 is a circuit diagram showing an example of a conventional field discrimination circuit.

FIG. 4 is a signal waveform diagram of each part of the circuit shown in FIG.

FIG. 5 is a circuit configuration diagram showing an example of a conventional field discrimination device.

6 is a signal waveform diagram of each part of the circuit shown in FIG.

[Explanation of symbols]

 21 field determination device 22 field determination circuit 23 field inversion circuit 24 field determination monitoring device 25 exclusive OR circuit 26 latch circuit 26a timer 27 changeover switch 31 liquid crystal display device 32 liquid crystal display panel 33 image processing circuit 34 drive circuit 35 scanning line thinning circuit

Claims (3)

[Claims] 1. An even-odd field discrimination is performed on a video signal in which an even field and an odd field form one frame based on the characteristics of an equalization pulse included in a vertical blanking period of a composite sync signal. A field discriminating circuit that outputs a field discriminating signal, a field inverting circuit that toggles by a vertical synchronizing pulse included in the composite synchronizing signal, and outputs a field inverting signal whose level is inverted for each field, the field discriminating signal, and the The field discrimination signal is collated with the field inversion signal, and the field discrimination signal is selectively output in the in-phase state, and in the reverse phase state, the field inversion signal is selectively output as the alternative field discrimination signal instead of the field discrimination signal. A field discriminating device comprising a monitoring circuit . 2. The exclusive-OR circuit, wherein the field-discrimination monitoring circuit collates the field-discrimination signal with the field inversion signal, and outputs a field-discrimination abnormal signal in a phase opposite to each other, and the exclusive-OR circuit. A latch circuit for latching an output field discrimination abnormality signal of the circuit for a predetermined time, and switching between the field discrimination signal and the field inversion signal by the latch output of the latch circuit, and when the field discrimination abnormality does not occur, the field discrimination signal 2. The field discriminating apparatus according to claim 1, further comprising a changeover switch for selectively outputting the field inversion signal and for selectively outputting the field inversion signal as an alternative field discrimination signal when a field discrimination abnormality occurs. 3. The latch circuit has a built-in timer for measuring the duration of the field discrimination abnormality signal and clearing the field discrimination abnormality signal when the duration exceeds a preset number of field periods. The field discriminating device according to claim 2, wherein