JPH0997908A - Amorphous silicon thin film transistor and method for manufacturing thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amorphous silicon thin film transistor which can realize a sufficiently low off-current level which suppresses an optical leakage current, and which can obtain switching characteristics excellent even when it is irradiat ed with light, as well as a method for manufacturing a thin film transistor. SOLUTION: A stacked film of an amorphous silicon thin film 14 and an inorganic protection film 15 formed on an insulation substrate 11 is located inside a gate electrode 12. Together with it, an edge part in a direction parallel to a channel in a channel area of a source and drain area of the inorganic protection film 15 is located inside a direction parallel to the channel in the channel area of an amorphous silicon thin film 14, and the width in a direction vertical to a channel in a channel area in a source and drain area of the amorphous silicon thin film 14 is smaller than that in a direction vertical to the channel in the channel region of a source electrode 20 and a drain electrode 21 and located further inside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amorphous silicon thin film transistor used as an active element of, for example, an active matrix type liquid crystal display device, and a method of manufacturing the thin film transistor.

[0002]

2. Description of the Related Art Conventionally, as a display device using a liquid crystal, a large-capacity and high-density active matrix type liquid crystal display device for a graphic display has been developed and put into practical use.

In such a display device, a semiconductor switch is used as a means for driving and controlling each pixel for enabling high-contrast display without crosstalk.

As such a semiconductor switch, a thin film transistor formed on a transparent insulating substrate, for example, a glass substrate is usually used for the reason that a transmissive display is possible and the area can be easily increased. Among them, a thin film transistor using amorphous silicon is the most common because it can be formed on a large area substrate and can be processed at a low temperature.

The structure of such a thin film transistor is roughly classified into a coplanar type and a staggered type depending on the relative positional relationship between the gate electrode, the semiconductor layer, and the source and drain electrodes. Particularly, it is formed on an insulating substrate. In the case of the amorphous silicon thin film transistor that is used, a staggered type, which has many significant points in terms of the manufacturing process, is often used, and in particular, the cross-sectional views shown in FIGS. , Which corresponds to the JJ ′ surface of the top view shown in FIG.
As shown in FIG. 3, an inverted staggered structure is generally used in which a gate electrode 2, a gate insulating film 3, an amorphous silicon thin film 4, a low resistance semiconductor thin film 5, a source electrode 6 and a drain electrode 7 are formed in this order on an insulating substrate 1. Target. Further, in such an inverted staggered type, an inorganic protective film 8 made of, for example, silicon nitride is formed between the amorphous silicon thin film 4 and the low resistance semiconductor thin film 5, and the inorganic protective film 8 is formed in a predetermined manner. A structure having a structure in which the workability of the low-resistance semiconductor thin film 5 is improved by processing the shape is also used.

Generally, in an active matrix type liquid crystal display device, two substrates subjected to an alignment treatment by rubbing are arranged parallel to each other so that their alignment directions are 90 degrees. A twisted nematic (TN) type in which a nematic type liquid crystal composition is sandwiched between these is widely used.

[0007]

By the way, the pattern of this type of amorphous silicon thin film transistor is generally shown in FIG.
The shapes and positional relationships shown in (a) and (b) are
The inorganic protective film 8 and the amorphous silicon thin film 4 are both island-shaped, and the source and drain electrodes 6 and 7 and the low-resistance semiconductor thin film 5 are shaped parallel to the channel direction so that the channel is sandwiched. positioned. At this time, since the amorphous silicon thin film 4 and the inorganic protective film 8 are formed by patterning after respectively forming, for example, amorphous silicon and silicon nitride continuously, the outer shape of the island-shaped inorganic protective film 8 is non-island-shaped. Generally, the crystalline silicon thin film 4 does not protrude from the outer shape. Regarding the positional relationship between the source and drain electrodes 6 and 7 and the inorganic protective film 8, the outer shape (width) of the source and drain electrodes 6 and 7 in the direction perpendicular to the channel direction in the channel region 9 is the inorganic protective film 8 as well. Is smaller than the outer shape (width) in the direction perpendicular to the channel direction, and is also inside in terms of position. That is, regarding the outer dimensions and relative positions of the respective layers, with respect to the direction parallel to the channel of the amorphous silicon thin film 4 in the channel region 9, the width of the gate electrode 2 is α9, the width of the amorphous silicon thin film 4 is β9, and the inorganic protection is performed. When the width of the film is γ9, γ9 <
The relationship is α9 <β9.

However, an amorphous silicon thin film transistor having such a pattern is generally known to have poor light resistance. For example, when the thin film transistor is irradiated with light, the amorphous silicon thin film in a region irradiated with light is known. A so-called off, in which photocarriers are generated in the thin film 4 and this becomes a photoleakage current and flows when the thin film transistor is not selected.
There was a problem of current failure.

Therefore, as a means for solving this problem,
As shown in FIGS. 14A and 14B (the cross-sectional view shown in FIG. 14A corresponds to the KK 'plane of the top view shown in FIG. 14B), light is emitted from the outside. A thin film transistor in which the inorganic protective film 8 and the low-resistance semiconductor layer 5 are configured to separate the amorphous silicon thin film 4 and the source and drain electrodes 6 and 7 electrically connected to the amorphous silicon thin film 4 Proposed.

However, in order to form an amorphous silicon thin film transistor having such a structure, the amorphous silicon thin film 4 and the inorganic protective film 8 cannot be continuously formed in a process manner. When the thickness is as thin as 1000 angstroms or less, deterioration of transistor characteristics due to contamination at the interface between the amorphous silicon thin film 4 on the back surface of the channel and the inorganic protective film 8 has been a problem.

The present invention has been made in view of the above circumstances, and it is possible to realize a sufficiently low off current level by suppressing a light leak current, and to obtain an excellent switching characteristic even when light is irradiated with an amorphous silicon thin film transistor. Another object of the present invention is to provide a method for manufacturing the thin film transistor.

[0012]

According to the first aspect of the present invention,
In an amorphous silicon thin film transistor formed by forming a gate electrode, a gate insulating film, an amorphous silicon thin film, an inorganic protective film, a low resistance semiconductor thin film, a source electrode and a drain electrode on an insulating substrate, with respect to the outer periphery of the gate electrode. The amorphous silicon thin film and the inorganic protective film are located inside, and at least the edges of the source and drain regions of the inorganic protective film in the direction parallel to the channel are the amorphous silicon thin film. The width in the direction perpendicular to the channel in the channel region of the source and drain regions of the amorphous silicon thin film located inside the edge portion in the direction parallel to the channel in the channel region and the source electrode and The width of the drain electrode is smaller than the width of the drain electrode in the direction perpendicular to the channel region and is located inside.

According to a second aspect of the present invention, a gate electrode, a gate insulating film, an amorphous silicon thin film, an inorganic protective film, and
In the method for manufacturing an amorphous silicon thin film transistor in which a low resistance semiconductor thin film, a source electrode and a drain electrode are sequentially formed, an inorganic protective film formed on the amorphous silicon thin film is
The shape is processed by backside exposure using the gate electrode as a mask.

According to a third aspect of the present invention, a gate electrode, a gate insulating film, an amorphous silicon thin film, an inorganic protective film, and
In the method for manufacturing an amorphous silicon thin film transistor in which a low resistance semiconductor thin film, a source electrode and a drain electrode are sequentially formed, the amorphous silicon thin film formed on the gate insulating film is formed by backside exposure using the gate electrode as a mask. I am trying to process it.

According to a fourth aspect of the present invention, a gate electrode, a gate insulating film, an amorphous silicon thin film, an inorganic protective film, and
In an amorphous silicon thin film transistor formed by forming a low resistance semiconductor thin film, a source electrode and a drain electrode, the outer shape of the source electrode and the drain electrode is the gate insulating film forming a laminated film, the amorphous silicon thin film, and the inorganic protective film. Smaller than any outer shape of the membrane and located inside,
The source electrode and the drain electrode to the amorphous silicon thin film through the via hole formed in the inorganic protective film,
The wiring electrodes are connected through the via holes formed in the laminated film.

According to a fifth aspect of the present invention, in the fourth aspect, at least a part of the wiring electrode is formed in the same layer as the gate electrode. According to a sixth aspect of the present invention, in the fourth aspect, the outer shapes of at least the amorphous silicon thin film and the inorganic protective film formed on the gate insulating film are the same.

According to a seventh aspect of the present invention, in the fourth aspect, at least the low-resistance semiconductor layer is a modified layer in which ionic species including impurity ions are injected into the amorphous silicon semiconductor layer.

As a result, according to the invention of claim 1,
Since the light is not irradiated to the region where the source and drain electrodes and the amorphous silicon thin film are electrically connected, the light leakage current can be suppressed and a sufficiently low off current level can be realized. Good switching characteristics can be obtained even at times.

According to the second and third aspects of the present invention, the shape of the inorganic protective film and the amorphous silicon thin film can be processed by backside exposure using the gate electrode as a mask.
The manufacturing process of such a thin film transistor can be simplified.

According to the present invention, the amorphous silicon thin film region electrically irradiated with light from the outside and the amorphous silicon thin film electrically connected to the source electrode and the drain electrode. Since it is possible to prevent the light from being irradiated to the region where the region is separated and the source and drain electrodes and the amorphous silicon thin film are electrically connected, it is possible to suppress the light leak current and keep the sufficiently low off current level. This can be realized, and good switching characteristics can be obtained even during light irradiation.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1A and 1B are a cross-sectional view and a top view of an amorphous silicon thin film transistor to which the present invention is applied (the cross-sectional view shown in FIG. 2 (a) to (a ')-corresponding to the plane AA' in the top view shown in FIG.
(D) and (d ') are cross-sectional views and a top view (FIG. 2 (a)) for explaining the method for manufacturing the same amorphous silicon thin film transistor.
The cross-sectional views shown in (d) to (a ')-
In the top view shown in (d '), BB' plane, CC 'plane, D-
(Corresponding to D ′ surface and EE ′ surface), FIGS. 3 (a) and 3 (b)
FIG. 4A is a top view for explaining a method for forming an amorphous silicon thin film.

First, as shown in FIGS. 2 (a) and 2 (a '),
The gate electrode 12 is formed on the insulating substrate 11. In this case, the width of the source and drain regions in the direction parallel to the channel is α1, and the width of the regions other than the source and drain regions in the direction parallel to the channel is α′1.

Next, as shown in FIGS. 2 (b) and 2 (b '),
A gate insulating film 13 is formed so as to cover the gate electrode 12. As the gate insulating film 13, a silicon nitride film using monosilane as a raw material is formed with a film thickness of 4000 angstroms by a CVD method such as plasma, constant pressure or reduced pressure.

Then, an amorphous silicon thin film 14 is formed on the gate insulating film 13. In this case, the amorphous silicon thin film 1
3A, as shown in FIG. 3A, first, the amorphous silicon thin film 14 having a film thickness of 500 angstrom is exposed from the back surface of the insulating substrate 11, so that the outer peripheral portion of the gate electrode 12 is exposed. The outer periphery of the crystalline silicon thin film 14 is formed inward by a width η, and the gate electrode 12 is formed so that the width of the amorphous silicon thin film 14 in the direction parallel to the channel regions of the source and drain regions becomes β1. In contrast, it forms in a self-aligned manner.
Further, by using a mask as shown in FIG. 3B, the width of the region other than the source and drain regions of the amorphous silicon thin film 14 in the direction parallel to the channel direction is β′1.
The amorphous silicon thin film 14 shown in (b) is completed.

Next, as shown in FIGS. 2 (c) and 2 (c '),
An inorganic protective film 15 having a film thickness of 2000 angstrom is exposed from the back surface of the insulating substrate 11 on the amorphous silicon thin film 14 to form the inorganic protective film 15 in a self-aligned manner with respect to the gate electrode 12. At this time, in the inorganic protective film 15, the width γ1 in the direction parallel to the channel region in the source and drain regions is smaller than the width β1 in the direction parallel to the channel region in the source and drain regions of the amorphous silicon thin film 14, and , The width γ′1 in the direction other than the source and drain regions in the direction parallel to the channel region is the width β ′ in the direction other than the source and drain regions of the amorphous silicon thin film 14 in the direction parallel to the channel direction.
Process so that it becomes larger than 1.

Thus, the relationship between α1, β1 and γ1 is
α1>β1> γ1 and α′1, β′1, γ ′
The relationship of 1 is α′1>γ′1> β′1. After this,
As shown in FIGS. 2 (d) and 2 (d '), a low resistance semiconductor thin film 16 having a film thickness of 500 angstroms is formed, for example.
As shown in FIG. 3, a channel region 17, a source region 18 and a drain region 19 are formed, and a source electrode 20 and a drain electrode 21 are further formed. At this time, the width δ1 of the source and drain electrodes 20 and 21 in the direction perpendicular to the channel direction is formed to be larger than the width ε1 of the channel region 17 in the direction perpendicular to the channel.

As a result, an amorphous silicon thin film transistor as shown in FIGS. 1A and 1B is completed. Then
In the amorphous silicon thin film transistor configured as described above, first, it will be described that no light leak current occurs due to light irradiation from above.

In this case, in order to simplify the explanation, FIG. 4A shows a case where a light leak current is generated by light irradiation from above the amorphous silicon thin film transistor shown in FIG. 13 as a conventional example. Then, with reference to FIG. 2B, it will be explained that no light leak current occurs due to light irradiation from above the amorphous silicon thin film transistor according to the first embodiment. In FIG. 4, the shaded area A is the amorphous silicon thin film 14 when light is irradiated from above the thin film transistor.
Region (4) irradiated with light, region B, is a region where the amorphous silicon thin film and the source / drain electrodes 20, 21 (6, 7) are electrically connected.

The amorphous silicon thin film 14 (4) is sensitive to light and has high photoconductivity. Therefore, when the source-drain electrodes 20 and 21 (6, 7) are connected by the light-irradiated amorphous silicon thin film 14 (4), the thin film transistor is turned off.
Even in the state, a light leak current flows between the source and drain electrodes 20, 21 (6, 7) regardless of the gate voltage.

Therefore, when light is irradiated from above the thin film transistor, in the conventional example shown in FIG. 4A, the shaded areas A and B are the end portions XY, X of the source / drain electrodes 6, 7. Since they are connected by'-Y ', the amorphous silicon thin film 4 is short-circuited by the light irradiation between the source and drain electrodes 6 and 7, which causes a light leak current. On the other hand, in the first embodiment shown in FIG. 4B, the shaded regions A and B are not directly connected to each other, and the amorphous silicon thin film region C where light is not present exists between them. Therefore, the distance between the source and drain electrodes 20 and 21 is of
Since they are separated by the amorphous silicon thin film 14 in the f state, the light resistance against light irradiation from above the thin film transistor is significantly improved.

Next, it will be explained that no light leak current is generated due to light irradiation from below the thin film transistor. Also in this case, in order to simplify the explanation, FIG.
FIG. 5A shows a case where a light leak current is generated by light irradiation from below the amorphous silicon thin film transistor shown in FIG.
As shown in FIG. 2B, it will be described that no light leakage current is generated due to light irradiation from below the amorphous silicon thin film transistor according to the first embodiment. Note that FIG.
In (a), area ABCH and area A'B'C '
H '(hatched region I) is a region where the amorphous silicon thin film 4 is irradiated with light from below the thin film transistor, a region ABEF and a region A'B'E'F' (region J).
Is a region where the amorphous silicon thin film 4 is electrically connected to the source / drain electrodes 6 and 7.

Therefore, when light is irradiated from below the thin film transistor, in the conventional example shown in FIG. 5A, the shaded regions I and J are the end portions A-G, A of the source / drain electrodes 6, 7. Since they are connected by'-G ', BD, and B'-D', the amorphous silicon thin film 4 is short-circuited by the light irradiation between the source and drain electrodes 6 and 7, and a light leak current is generated. Become. On the other hand, in the first embodiment shown in FIG. 5B, the shaded region I does not exist because the light from below is blocked by the gate electrode 12. That is, since the source and drain electrodes 20 and 21 are separated by the amorphous silicon thin film 14 in the off state, the light resistance against light irradiation from below the thin film transistor is significantly improved.

Incidentally, FIGS. 6 and 7 show the above-mentioned FIG. 4 (a).
In the conventional example shown in FIG. 5 (a), the amorphous silicon thin film 4 irradiated with light from above or below causes the source,
It shows an experimental example for demonstrating that the drain electrodes 6 and 7 are short-circuited and a light leak current is generated.

In the amorphous silicon thin film transistor in this case, the width of the island-shaped inorganic protective film on the amorphous silicon parallel to the channel direction is α = 14 μm, and the width in the direction perpendicular to the channel direction is β = 50 μm. The width of the source and drain electrodes in the direction perpendicular to the channel direction is γ = 40 μm, and the distance between both electrodes is δ = 10 μm.

In this experiment, slit light was radiated from above (FIG. 6) and below (FIG. 7) the thin film transistor so as to be parallel to the tip portions of the source and drain electrodes 6 and 7 at positions equidistant from each electrode. The figure shows the change in leak current when the slit light is irradiated and is translated in this state from the central portion of the thin film transistor to the side end portions of both electrodes. Here, the leak current is the source when the drain voltage VD = 15V, the gate voltage VG = 0V, and the source voltage VS = 0V.
It is a current (IDS) flowing between the drain electrodes.

From the results shown in FIGS. 6 and 7,
The current level when the slit light is applied to the central part (position A) of the thin film transistor is almost the same as the current level when the thin film transistor is not irradiated with light, whereas the slit light is applied to the side end parts of the source and drain electrodes ( Position B)
This means that the thin film transistor has a leakage current when it is irradiated. This is shown in FIGS.
As described in (a), it is shown that a light leakage current is generated when the source and drain electrodes 6 and 7 are short-circuited by the amorphous silicon thin film 4 which is irradiated with light.

The experimental results when the position A is irradiated with the slit light are simulated when the light is irradiated from above and below the amorphous silicon thin film transistor described in FIGS. 4B and 5B. It is also shown that the photo-leakage current does not occur in these amorphous silicon thin film transistors.

Then, the light resistance of the amorphous silicon thin film transistor thus constructed was tested by comparison with a conventional thin film transistor, and the results shown in FIG. 8 were obtained. Note that the thin film transistors used in this experiment have the same effective channel dimensions, and the amorphous silicon thin film,
The widths of the inorganic protective film, the source and drain electrodes, the structure other than those caused by the positional relationship, and the various conditions such as manufacturing conditions are all the same.

The light resistance measurement here is performed by the source,
Measure the current (IDS) flowing between the source and drain when the gate voltage (VG) is changed from -15V to + 25V with the voltage (VDS) between the drains set to 15V (IDS-VG) characteristic measurement Went by. In addition, white light was used for light irradiation, and the amount of light was 800 lux from above and below the amorphous silicon thin film transistor.
The experimental atmosphere is air and the temperature is 25 ° C.

In this case, (a) in the figure is the sample 1 according to the first embodiment, and (b) is the sample 2 according to the conventional example.
The characteristic curves of the sample No. 1 at the time of light irradiation are shown, and (c) and (d) show the characteristic curves of Sample No. 1 and Sample No. 2 when no light is irradiated.

As is apparent from the figure, however, the sample 1 has a much smaller current value in the leak current (I _off ) region during light irradiation than the sample 2, and therefore, the light resistance is very high. Proved to be excellent.

Therefore, in this way, the insulating substrate 11
A gate electrode 12, a gate insulating film 13, an amorphous silicon thin film 14, an inorganic protective film 15, a low resistance semiconductor thin film 16, a source electrode 20 and a drain electrode 21 are formed on the gate electrode 12, and an electric field generated by a voltage applied to the gate electrode 12 is formed. Due to the effect, it is an amorphous silicon thin film transistor that exhibits a switching action between the source and drain electrodes 20 and 21, and a laminated film including the amorphous silicon thin film 14 and the inorganic protective film 15 is located inside the gate electrode 12. This prevents the light from below the substrate 11 from irradiating the amorphous silicon thin film 14, and also, in the channel regions of the source and drain regions of the inorganic protective film 15, the edges in the direction parallel to the channel. Is located inside the edge of the amorphous silicon thin film 14 in the channel region in the direction parallel to the channel, and the amorphous silicon thin film 14 has the source and the source. Since the width of the drain region in the channel region in the direction perpendicular to the channel is smaller than the width of the source electrode 20 and the drain electrode 21 in the channel region in the direction perpendicular to the channel, and is located inward. The region where the source and drain electrodes 20 and 21 and the amorphous silicon thin film 14 are electrically connected is prevented from being irradiated with light from above, thereby suppressing the light leak current and sufficiently low off current level 0. This can be realized, and good switching characteristics can be obtained even during light irradiation.

Further, since the shape processing of the inorganic protective film 15 and the amorphous silicon thin film 14 can be realized by the back surface exposure using the gate electrode 12 as a mask, the manufacturing process of such a thin film transistor can be simplified.

The shape processing of the amorphous silicon thin film 14 in the first embodiment is carried out by the usual photolithography method so that the stacking range is limited to the inside of the gate electrode 12. May be. Further, in the first embodiment, the source and drain regions 18 and 19 are formed by forming the low resistance semiconductor thin film 16, but at least the inorganic protective film 15 is masked from above the substrate by a method such as ion implantation. Alternatively, it may be formed by implanting an ion species containing an element that can serve as a donor into silicon such as phosphorus ions. (Second Embodiment) FIGS. 9 (a) and 9 (b) are a cross-sectional view and a top view of the second embodiment (the cross-sectional view shown in FIG. 9 (a) is the top view shown in FIG. 9 (b)). (Corresponding to the FF ′ plane), and the same portions as those in FIGS. 1A and 1B are denoted by the same reference numerals.

In this case, the gate electrode 12 has a width in the direction parallel to the channel region of the source and drain regions and a width in the direction parallel to the channel of regions other than the source and drain regions as α3, and the inorganic protective film 15 also serves as the source. The width of the drain region in the direction parallel to the channel region and the width of the region other than the source and drain regions in the direction parallel to the channel are γ3, and the amorphous silicon thin film 14 is parallel to the channel regions of the source and drain regions. The width dimension in the direction is widened to β3, and the relationship between α3, β3, and γ3 is α3>β3> γ
3 is set.

The preparation procedure in this case is also the same as that described with reference to FIGS. 1 and 2, and the same effect as that of the first embodiment can be expected. (Third Embodiment) FIGS. 10A and 10B are a sectional view and a top view of an amorphous silicon thin film transistor according to a third embodiment (the sectional view shown in FIG. It is equivalent to the GG 'surface of the top view shown in (b)).

In this case, the gate electrode 3 is formed on the insulating substrate 31.
2 and the wiring electrodes 33 and 34 are formed. The gate electrode 32 and the wiring electrodes 33 and 34 here are formed in the same layer as a single layer or a laminated layer of a metal material such as Ta, Mo, W, Ti, Cr, or Al, or an alloy thereof. At this time, a taper etching technique may be used in which the etching cross section is inclined.

Next, these gate electrode 32 and wiring electrode 3
A gate insulating film 35 made of, for example, silicon nitride, an amorphous silicon thin film 36, and an inorganic protective film 37 made of, for example, silicon nitride are continuously formed to cover the layers 3 and 34 to form a laminated film 38. At this time, a CVD method such as plasma, atmospheric pressure or reduced pressure is used for forming the laminated film 38. Also,
Gate insulating film 35, amorphous silicon thin film 36, inorganic protective film 3
Each film thickness of 7 is 4000 angstroms, 5
It is set to 00 angstrom and 2000 angstrom. Further, here, the gate insulating film 3 of the laminated film 38 is used.
5, each layer of the amorphous silicon thin film 36 and the inorganic protective film 37 is formed of a single material or a single layer film, but may be formed of a laminated film made of different materials.

Next, first via holes 39 for forming source and drain regions are formed in the inorganic protective film 37 at the same time when the outer pattern is processed, and then the amorphous silicon thin film 36 is formed.
Shape processing. The outer shape of the amorphous silicon thin film 36 here is larger than the outer shape of the inorganic protective film 37.

Next, an amorphous silicon thin film doped with, for example, phosphorus is formed as the low resistance semiconductor layer 40, and then the second via hole for connecting the wiring electrode is formed through the laminated film 38 and the low resistance semiconductor layer 40. 41 is formed.

Further, source and drain electrodes 42 and 43
For example, a metal material such as Ta, Mo, W, Ti, Cr, or Al, or an alloy thereof is formed as a single layer or a stacked layer, and the shape is processed. At that time, the outer shapes of the source and drain electrodes 42 and 43 are positioned inside and at least smaller than the outer shapes of any of the films forming the laminated film 38. Also,
In this processing, the low resistance semiconductor layer 40 is processed at the same time by using the source and drain electrodes 42 and 43 as a mask to separate the source and drain electrodes 42 and 43.

Therefore, in the amorphous silicon thin film transistor having such a structure, no light leakage current due to light irradiation is generated, as shown in FIGS. 11 (a) and 11 (b). This corresponds to the HH 'plane of the top view shown in FIG.

In this case, the shaded area A is the amorphous silicon thin film 3 when light is irradiated from above the amorphous silicon thin film transistor.
6 is a region irradiated with light, region B is an amorphous silicon thin film 36.
Is a region where the source and drain electrodes 42 and 43 are electrically connected.

Amorphous silicon 36 is very sensitive to light and has high photoconductivity. Therefore, the source and drain electrodes 4
When the amorphous silicon thin film 36 irradiated with light is connected between 2 and 43, the source and drain electrodes 42 and 43 are independent of the gate voltage even if the amorphous silicon thin film transistor is off. Light leak current flows between them.

However, in such a structure, the hatched region A and the region B are not directly connected to each other, light is not irradiated between them, and the amorphous silicon thin film is not connected to the source and drain electrodes 42 and 43. Since the region C of 36 exists, that is, between the source and drain electrodes 42 and 43 is o.
Since it is separated in the region C of the amorphous silicon thin film 36 in the ff state, the light leakage current does not flow, and the light resistance can be remarkably improved.

Therefore, in this way, the insulating substrate 31
The gate electrode 32, the wiring electrodes 33 and 34, the gate insulating film 35, the amorphous silicon thin film 36, the inorganic protective film 37, the low resistance semiconductor thin film 40, the source electrode 42, and the drain electrode 43 are formed on the top.
Is formed, and is an amorphous silicon thin film transistor that exhibits a switching action between the source and drain electrodes 42 and 43 due to a field effect due to the voltage applied to the gate electrode 32. The gate insulating film 32 and the amorphous silicon thin film 36 Since the inorganic protective film 37 is continuously formed, the interface between the insulating film and the amorphous silicon thin film, which are stacked above and below the amorphous silicon thin film 36, can be well maintained, and thus good channel characteristics can be obtained. In addition, the source and drain electrodes 42 and 43 have the outer shapes of the gate insulating film 35 and the amorphous silicon thin film 3 which form a laminated film.
6, which is smaller than any of the outer shapes of the inorganic protective film 37 and is located inside, and the source electrode 42 and the drain electrode 43 are stacked on the amorphous silicon thin film 36 through the via holes formed in the inorganic protective film 37. Since the wiring electrodes 33, 34 are connected to the wiring electrodes 33, 34 through the via holes formed in the non-conductive region, the amorphous silicon thin film region irradiated with light from the outside is electrically connected to the source and drain electrodes. The crystalline silicon thin film region can be separated, and the region where the source and drain electrodes and the amorphous silicon thin film are electrically connected can be prevented from being irradiated with light. As a result, the light leakage current can be suppressed to realize a sufficiently low off current level, and good switching characteristics can be obtained even during light irradiation. (Fourth Embodiment) FIGS. 12A and 12B (FIG. 12)
The cross-sectional view shown in (a) is taken along the line I- of the top view shown in (b).
(Corresponding to plane I ') shows a schematic configuration of the fourth embodiment, and the same parts as those in FIGS. 10A and 10B are designated by the same reference numerals.

In this case, the gate electrode 3 is formed on the insulating substrate 31.
2 is formed, the first gate insulating film 44 is formed so as to cover the gate electrode 32, and then the wiring electrodes 33 and 34 are formed.

After that, the second gate insulating film 45, the amorphous silicon thin film 36 and the inorganic protective film 37 are continuously formed to form a laminated film 38. The materials, structures, film forming methods, etc. of the films formed so far are the same as those described in the first embodiment. In addition, the wiring electrode 3 shown in the present embodiment
For example, ITO (Indiu) is used as a transparent conductive film on the layers 4 and 35.
m-Tin-Oxide) may be used partially or entirely, and this ITO may be used as a pixel electrode of an active matrix type liquid crystal display device, for example.

After that, first via holes 39 for forming source and drain regions are formed in the inorganic protective film 37. Then, the low resistance semiconductor layer 46 is formed by injecting, for example, an ion species containing phosphorus ions into the amorphous silicon thin film 36 exposed in the first via hole 39 using the inorganic protective film 37 as a mask. The ion implantation conditions here are an acceleration voltage of 30 kV and an implantation amount of 5 × 10 ¹⁵ / cm ² . Under this condition, the average projected range (R _p ) of phosphorus ions
Is about 500 Å, which is sufficiently shallow, and the inorganic protective film 3
7 can serve as an ion implantation stopper. Then, the laminated film 38 is shaped. At that time, the second via hole 41 for connecting to the wiring electrode is also formed at the same time.

After that, the source and drain electrodes 42 and 43
For example, a metal material such as Mo, Al, or Ti, or an alloy thereof is formed in a single layer or stacked, and is shaped. Here, the source and drain electrodes 42,
The outer shape of 43 is at least smaller than the pattern shape of the laminated film 38.

Even in this case, the same effect as that of the third embodiment can be expected. The amorphous silicon thin film transistor described in the above embodiment can be applied not only to the active matrix type liquid crystal display device but also to the manufacture of various sensors.

[0062]

As described above, according to the present invention, the region where the source and drain electrodes are electrically connected to the amorphous silicon thin film is prevented from being irradiated with light, so that the light leakage is prevented. It is possible to realize a high-performance amorphous silicon thin film transistor by suppressing the current and realizing a sufficiently low off current level and obtaining good switching characteristics even during light irradiation. Further, since the inorganic protective film and the amorphous silicon thin film can be processed by the back surface exposure using the gate electrode as a mask, the manufacturing process can be simplified.

[Brief description of drawings]

FIG. 1 is a sectional view and a top view of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view and a top view for explaining the manufacturing method according to the first embodiment.

FIG. 3 is a top view for explaining the method for forming the amorphous silicon thin film according to the first embodiment.

FIG. 4 is a diagram for explaining a cause of a light leak current generated by light irradiation from above in the first embodiment.

FIG. 5 is a diagram for explaining the cause of the generation of a light leak current due to light irradiation from below in the first embodiment.

FIG. 6 is a diagram showing an experimental result of investigating which portion of the thin film transistor is the cause of generation of a light leak current by irradiation with light from above using slit light.

FIG. 7 is a diagram showing an experimental result of investigating which part of the thin film transistor is the cause of generation of a light leak current by irradiating light from below with slit light.

FIG. 8 is a diagram showing a result of an experiment relating to light resistance in the first embodiment.

FIG. 9 is a sectional view and a top view of the second embodiment of the present invention.

FIG. 10 is a sectional view and a top view of the third embodiment of the present invention.

11A and 11B are a cross-sectional view and a top view for explaining the cause of the generation of the light leakage current according to the third embodiment.

FIG. 12 is a cross-sectional view and a top view of a fourth embodiment of the present invention.

13A and 13B are a cross-sectional view and a top view illustrating an example of a conventional thin film transistor.

14A and 14B are a cross-sectional view and a top view showing another example of a conventional thin film transistor.

[Explanation of symbols]

 11 ... Insulating substrate, 12 ... Gate electrode, 13 ... Gate insulating film, 14 ... Amorphous silicon thin film, 15 ... Inorganic protective film, 16 ... Low resistance semiconductor thin film, 17 ... Channel region, 18 ... Source region, 19 ... Drain Regions: 20 ... Source electrode, 21 ... Drain electrode, 31 ... Insulating substrate, 32 ... Gate electrode, 33, 34 ... Wiring electrode, 35 ... Gate insulating film, 36 ... Amorphous silicon thin film, 37 ... Inorganic protective film, 38 ... Laminated film, 39 ... First via hole, 40, 46 ... Low resistance semiconductor layer, 41 ... Second via hole, 42 ... Source electrode, 43 ... Drain electrode, 44 ... First gate insulating film, 45 ... Second gate insulating film.

Claims (7)

[Claims] 1. A gate electrode, a gate insulating film, an amorphous silicon thin film, an inorganic protective film, a low resistance semiconductor thin film, on an insulating substrate.
In an amorphous silicon thin film transistor formed by forming a source electrode and a drain electrode, the amorphous silicon thin film and the inorganic protective film are located inside the outer periphery of the gate electrode, and at least the source of the inorganic protective film and The edge of the drain region in the channel region parallel to the channel is located inside the edge of the amorphous silicon thin film in the channel region in the direction parallel to the channel, and the amorphous silicon thin film. The width of the source and drain regions in the channel region in the direction perpendicular to the channel is smaller than the width of the source and drain electrodes in the channel region in the direction perpendicular to the channel, and is located inward. And an amorphous silicon thin film transistor. 2. A gate electrode, a gate insulating film, an amorphous silicon thin film, an inorganic protective film, a low resistance semiconductor thin film, on an insulating substrate.
In a method for manufacturing an amorphous silicon thin film transistor in which a source electrode and a drain electrode are sequentially formed, an inorganic protective film formed on the amorphous silicon thin film may be shaped by backside exposure using the gate electrode as a mask. A method for manufacturing an amorphous silicon thin film transistor, which is characterized. 3. A gate electrode, a gate insulating film, an amorphous silicon thin film, an inorganic protective film, a low resistance semiconductor thin film, on an insulating substrate.
In the method for manufacturing an amorphous silicon thin film transistor in which a source electrode and a drain electrode are sequentially formed, the amorphous silicon thin film formed on the gate insulating film is shaped by backside exposure using the gate electrode as a mask. A method for manufacturing an amorphous silicon thin film transistor, which is characterized. 4. A gate electrode, a gate insulating film, an amorphous silicon thin film, an inorganic protective film, a low resistance semiconductor thin film, on an insulating substrate.
In an amorphous silicon thin film transistor formed by forming a source electrode and a drain electrode, the outer shape of the source electrode and the drain electrode is any one of the gate insulating film, the amorphous silicon thin film, and the inorganic protective film that form a laminated film. Smaller than and located inside, the source electrode and the drain electrode serve as the amorphous silicon thin film through the via hole formed in the inorganic protective film, and serve as the wiring electrode through the via hole formed in the laminated film. An amorphous silicon thin film transistor characterized by being connected. 5. The amorphous silicon thin film transistor according to claim 4, wherein at least a part of the wiring electrode is formed in the same layer as the gate electrode. 6. The amorphous silicon thin film transistor according to claim 4, wherein the amorphous silicon thin film and the inorganic protective film laminated at least on the gate insulating film have the same outer shape. 7. The amorphous silicon thin film transistor according to claim 4, wherein at least the low resistance semiconductor layer comprises a modified layer in which ionic species containing impurity ions are injected into the amorphous silicon semiconductor layer.