JPH0996645A - Tape speed detecting equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a tape speed detecting equipment which detects running speed of a tape at the time of direct drive of reels without using a sensor for exclusive use. SOLUTION: At the time of direct drive of reels, a period square sum computing circuit 5 outputs value of the sum of squares of periods of frequency generators 23 and 24 fitted to the reels 101 and 102 respectively, while a reference period square sum preparing circuit 6 outputs value of the sum of squares of a period corresponding to a reference tape speed. In a division circuit 7, the output value of the reference period square sum preparing circuit 6 is divided by the output value of the period square sum computing circuit 5. In a square root computing circuit 8, square root of output value of the division circuit 7 is calculated, and double speed value to the reference tape speed is calculated therefrom.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tape speed detecting device for detecting a running speed when a reel around which a tape-shaped medium (for example, a magnetic tape such as an audio tape or a video tape) is wound is directly driven. Regarding

[0002]

2. Description of the Related Art As a conventional tape speed detecting device, a device for detecting the rotational speed of a roller in contact with the tape, a device for detecting the reproduction frequency of a signal recorded at equal intervals on the tape, a tape winding diameter, One that derives the tape speed from the rotation speed of the reel, one that simply calculates the tape speed from the rotation cycle of the two reels (for example, JP-A-5-307801).
Japanese Patent Laid-Open No. 63-15), which obtains a voltage inversely proportional to the tape speed from the rotation cycle of two reels (for example, Japanese Patent Laid-Open No. 63-15).
3469).

[0003]

However, the conventional tape speed detecting device described above has the following problems. A roller for detecting the rotation speed of the roller requires a dedicated roller, and a roller for detecting the reproduction frequency of the signal cannot be detected in a portion where the signal is not recorded. In the case of obtaining the tape speed from the winding diameter and the rotation speed of the reel, it is necessary to detect the absolute winding diameter and a dedicated winding diameter detector is required.
When the speed is simply calculated from the rotation cycle of the reel, an error occurs depending on the winding position of the tape. In order to obtain a voltage inversely proportional to the tape speed from the rotation cycle of two reels, the tape speed itself cannot be directly obtained, and a dedicated electronic circuit for converting the cycle into a voltage and then synthesizing the voltage is required.

[0004] The present invention solves the above problems,
Software processing by a microcomputer is easy without providing special parts for tape speed detection.
An object of the present invention is to provide a tape speed detecting device that detects the tape speed without depending on the winding position of the tape.

[0005]

In order to achieve the above object, a tape speed detecting device of the present invention comprises a take-up reel and a delivery reel having both ends of the tape wound, and a tape on the take-up reel. The tape winding means for winding up, the first and second frequency generators for outputting frequency signals proportional to the respective rotation speeds of the winding side reel and the sending side reel, and the first and second frequency generators A cycle sum of squares calculating means for calculating the sum of squares of respective cycles of the output signal, a reference cycle sum of squares creating means for creating a sum of cycle squares corresponding to the reference tape speed, and an output value of the reference cycle sum of squares creating means It is provided with a dividing means for dividing the output value of the sum of squares calculating means and a square root calculating means for calculating the square root of the output value of the dividing means and outputting a value corresponding to the tape speed.

Further, the square root calculating means in the tape speed detecting device of the present invention comprises a first area judging means for deciding a solution area roughly divided into several according to an output value of the dividing means, and a dividing means. Based on a value obtained by dividing the output value by a value corresponding to the first area, a second area determination means for determining a further narrowed down solution area and an area determined by the second area determination means Using the extreme value output means for outputting the minimum solution or the maximum solution and the output of the extreme value output means as the initial predicted solution, the predicted solution creation means for adding or subtracting unit values to update the predicted solution, and the predicted solution And a solution determining means for outputting an expected solution when the verification error of the verification means is minimum.

As a result, it is possible to obtain a tape speed detecting device which can easily perform software processing by the microcomputer without providing a special part for detecting the tape speed, and which detects the tape speed without depending on the winding position of the tape.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 is a winding-side reel and a sending-side reel in which both ends of the tape are wound respectively, and a tape winding means for winding the tape around the winding-side reel. And a first and a second that respectively output a frequency signal proportional to the rotation speed of the take-up reel and the delivery reel.
Frequency generator, a cycle sum of squares calculating means for calculating the sum of squares of respective cycles of output signals of the first and second frequency generators, and a reference cycle for creating a cycle sum of squares corresponding to the reference tape speed. A square sum generating means, a dividing means for dividing the output value of the reference period square sum generating means by the output value of the period square sum calculating means, and a square root of the output value of the dividing means are calculated to correspond to the tape speed. A tape speed detecting device having a square root calculating means for outputting a value and detecting a double speed value with respect to the reference tape speed, and has the following operation.

When the tape winding means is winding the tape from the sending side reel to the winding side reel, the cycle sum of squares calculating means squares the signal cycles of the first and second frequency generators. Is added and output. This value is inversely proportional to the square of the tape speed regardless of the winding position of the tape. The reference period sum of squares creating means presets a value corresponding to the output of the period square sum calculating means when the tape is wound at the reference tape speed. The dividing means divides the output value of the reference period sum of squares creating means by the output value of the period sum of squares calculating means. The square root calculating means outputs the square root of the division result and obtains a value proportional to the tape speed. The value of the sum of period squares is inversely proportional to the square of the tape speed.Therefore, by deriving the square root of the result of dividing the sum of period squares when winding at a known and slow tape speed, which is the reference, by the sum of period squares, The tape speed is obtained as a double speed value with respect to the tape speed.

According to a second aspect of the present invention, there is provided a first method for determining a solution region which is roughly divided into several according to an output value of the dividing means.
Area determining means and the output value of the dividing means to the first
Second area determining means for determining a further narrowed down solution area based on a value divided by a value corresponding to the area
The extreme value output means for outputting the minimum solution or the maximum solution of the area determined by the second area determination means, and the output of the extreme value output means as an initial predicted solution, and the unit value is added or subtracted for prediction. An expected solution creating means for updating a solution, a checking means for determining whether the checking error is the minimum using the expected solution, and a solution determining means for outputting the expected solution when the checking error of the checking means is the minimum The tape speed detecting device according to claim 1, further comprising a square root calculating means for obtaining a square root output by updating the predicted solution until the verification error is minimized. .

The first area judging means divides the range of the square root solution into several stages according to the input value of the square root calculating means, and the second area judging means divides the input value by a predetermined value for each first area. At the stage, the range of the further narrowed square root solution is determined. The extreme value output means outputs the minimum solution or the maximum solution in the range of the square root solution. The predicted solution creating means sets the output of the extreme value output means as an initial predicted solution. The verification means uses the expected solution to determine whether the verification error is the minimum. When the verification error is not the minimum, the predicted solution creating means adds or subtracts the unit value to update the predicted solution. The checking means uses the updated expected solution to determine again whether the checking error is the minimum. This operation is repeated until the verification error becomes minimum. The solution decision means outputs the expected solution as a square root solution when the verification error is minimized. At this time, the square root can be obtained accurately and in a short time by appropriately setting the first and second areas and a predetermined value for division.

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a configuration of a tape speed detecting device according to Embodiment 1 of the present invention.
In FIG. 1, 100 is a tape, 101 and 102 are reels for winding the tape 100, 103 and 104 are posts that form a traveling path of the tape 100, and 22 is a reel 10.
A motor for rotating 1 or 102, 23 and 24 for a frequency generator that outputs a signal of a frequency proportional to the rotation speed of the reels 101 and 102, 26 for a drive circuit for generating a winding torque for the motor 22, and 28 for a motor. 22
And a drive circuit 26, tape winding means 51, 5
2 is a cycle detection circuit for detecting the cycle of the output signals of the frequency generators 23 and 24, Tt and Ts are the values of the output signals of the cycle detection circuits 51 and 52, and 53 and 54 are the squares of Tt and Ts squared, respectively. An arithmetic circuit, 55 is an adder circuit for adding the outputs of the square arithmetic circuits 53 and 54, and 5 is a cycle sum of squares arithmetic means composed of the period detection circuits 51, 52, the square arithmetic circuits 53, 54, and the adder circuit 55, Reference numeral 6 is a reference period square sum generation circuit that outputs the value of the period square sum corresponding to the reference tape speed, Ref is an output value of the reference period square sum generation circuit 6, and 7 is an output value Ref added circuit 55 (or period squared). A division circuit for dividing by the output value of the sum calculation means 5), D
v is an output value of the division circuit, 8 is a square root calculation circuit for calculating the square root of the output value Dv of the division circuit 7, and n is an output value of the square root calculation circuit.

The operation of the tape speed detecting device according to the first embodiment having the above-described structure will be described below.
When the drive circuit 26 drives the motor 22 and the tape 100 is wound from the reel 102 to the reel 101 (when the reel 101 is the take-up reel and the reel 102 is the delivery reel), the frequency generators 23 and 24. Outputs a signal having a frequency proportional to the rotation speed of the reels 101 and 102, respectively. The cycle detection circuits 51 and 52 detect the cycle values Tt and Ts of the output signals of the frequency generators 23 and 24, respectively. The square calculation circuits 53 and 54 calculate the square of Tt and Ts, respectively. The adder circuit 55 includes two square operation circuits 5
The output values of 3, 54 are added and output. That is, the period square sum calculating means 5 adds up the values obtained by squaring the signal periods of the frequency generators 101 and 102 and outputs the sum. This value is inversely proportional to the square of the tape speed regardless of the winding position of the tape.

This is because the winding diameters (radius) of the tape 100 including the reels 101 and 102 are Rt and Rs, respectively, and the rotation cycles of the reels 101 and 102 are Tt and Rt, respectively.
Assuming that Ts and the running speed of the tape 101 are V, (V × T
t) and Rt, (V × Ts) and Rs are in a proportional relationship, and the area (2 × π × Rt × Rt + 2 × π × Rs × Rs) in the winding diameter direction of the reels 101 and 102 and the tape 101 is equal to the winding amount. Since there is a fixed relationship regardless of position, Rt, Rs
It is possible to obtain a relational expression in which the sum of squares of Tt and Ts is inversely proportional to the square of the tape speed V without including.

The reference period sum of squares generation circuit 6 outputs the value of the period sum of squares Ref corresponding to the reference tape speed. The division circuit 7 outputs the output value Ref of the reference period sum of squares creation circuit 6.
Is divided by the output value of the adder circuit 55 (periodic sum of squares calculation circuit 5) to output a value Dv. The square root calculation circuit 8 outputs the square root of the divided value Dv and outputs the value n proportional to the tape speed.
Get.

As described above, in the first embodiment, the value of the sum of period squares, which is the output of the period square sum calculation circuit 5, is inversely proportional to the square of the tape speed V. Therefore, the period square sum Ref at the reference tape speed is given. By deriving the square root of the result obtained by dividing by the sum of the detected period squared, the tape speed is obtained as the double speed value n with respect to the reference tape speed. (Second Embodiment) FIG. 2 is a block diagram showing a configuration of a tape speed detecting device according to a second embodiment of the present invention.

In FIG. 2, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Reference numeral 27 is a drive circuit for changing the torque generated in the motor 22 based on an operation switching command from the outside, 29 is a tape winding means constituted by the motor 22 and the drive circuit 27, and 31 is a cap for transferring the tape 100. Stan motor, 32 is capstan motor 3
1 is a pinch roller that presses the tape 100 against the rotating shaft 1, 33 is a speed control circuit that rotates the capstan motor 31 at a constant speed based on a predetermined target speed, and 34 is based on an operation switching command from the outside. Capstan motor 3
1. A crimping mechanism for crimping or releasing the rotary shaft 1 and the pinch roller 32, 35 is a double speed conversion circuit that outputs a double speed value from a predetermined target speed to the reference tape speed, and 36 is an output value of the addition circuit 55 and a double speed conversion circuit 35. A multiplying circuit for multiplying the output, 37 is a memory circuit for storing and outputting the output of the multiplying circuit 36 based on an operation switching signal from the outside, and the reference period square sum creating means is the capstan motor 31 and the pinch roller 3
2, speed control circuit 33, crimping mechanism 34, and double speed conversion circuit 3
5, a multiplication circuit 36, and a storage circuit 37.

The operation of the tape speed detecting device according to the second embodiment having the above-described structure will be described below.
First, the creation of the reference period sum of squares will be described. When the tape transfer by the capstan motor 31 is commanded from the outside, the pressure bonding mechanism 34 sandwiches the tape 100 between the rotation shaft of the capstan motor 31 and the pinch roller 32. Since the speed control circuit 33 rotates the capstan motor 31 at a constant speed (target speed), the tape 100 is pulled out from the reel 102 at a constant speed. At this time, drive circuit 2
A motor 7 drives the reel 101 by the motor 22 and winds the drawn tape 100 without slack. Tape 1
When 00 is wound around the reel 101 from the reel 102 at a constant speed, the sum of squared period calculating means 5 adds and squares the signal periods of the frequency generators 101 and 102 and outputs the sum (see Embodiment 1). reference). Further, the double speed conversion circuit 35 outputs a double speed value from the target speed of the capstan motor 31 with respect to the reference tape speed. The multiplication circuit 36 multiplies the output value of the period square sum calculation means 5 and the output value of the double speed conversion circuit 35. The memory circuit 37 is the capstan motor 31.
The output value of the multiplying circuit 36 at the time of tape transfer by is stored and output. The output value of the storage circuit 37 becomes the output of the target period square sum creating means, and the target period square sum value at the reference tape speed (1 × speed) is obtained.

Next, when a command to wind the tape 100 by directly driving the reel 101 from the outside is given, the pressure bonding mechanism 34
Is the rotation shaft of the capstan motor 31 and the pinch roller 32.
Release the crimp of. The tape 100 runs only by the rotation of the reel 101. Therefore, the drive circuit 27
Drives the motor 22 to rotate the reel 101 and wind the tape 100. As the tape 100 is sequentially wound from the reel 102 to the reel 101, the frequency generators 23 and 24 output signals having frequencies proportional to the rotation speeds of the reels 101 and 102, respectively. The cycle detection circuits 51 and 52 detect the cycle values Tt and Ts of the output signals of the frequency generators 23 and 24, respectively. Squaring circuit 53,
54 calculates the square of Tt and Ts, respectively. The adder circuit 55 adds the output values of the two square calculation circuits 53 and 54 and outputs the result. The division circuit 7 outputs the output value Ref of the storage circuit 37.
Is divided by the output value of the adder circuit 55 (periodic sum of squares calculation circuit 5) to output a value Dv. The square root calculation circuit 8 outputs the square root of the divided value Dv and outputs the value n proportional to the tape speed.
Get.

As described above, in the second embodiment, the value of the sum of period squares, which is the output of the period sum of squares arithmetic circuit 5, is inversely proportional to the square of the tape speed V. Therefore, the reference value obtained by the tape transfer by the capstan is used. By deriving the square root of the result obtained by dividing the sum of period squared Ref at the tape speed by the detected period square sum, the double speed value n with respect to the reference tape speed is obtained.
The tape speed is calculated as

Here, the case where the square root operation circuit 8 is realized by the processing of a microcomputer having only addition, subtraction, multiplication and division operations will be described. FIG. 3 is a flow chart when a microcomputer is used as an example of the square root calculation circuit 8 in the first and second embodiments of the present invention. In FIG. 3, the input value 81 (the output value Dv of the division circuit 7) is 256.
A branching process for determining whether it is less than 0, a setting process for setting A1 (arbitrary value) as the value of address 1,
83 is a setting process for setting A2 (arbitrary value) as the value of address 1, and 84 is the value of address 2 (input value / 25
6) division processing for setting the integer part, 85 division processing for setting the integer part of (input value / 1024) as the value of address 2, 86 addition processing for adding address 1 and address 2 to obtain address 3 , 87 are addresses A1 and A2
Data table that stores lower limit expected values in order from 8
8 is a read process for setting the value of the data table 87 stored at the position of address 3 as an expected value, 89 is a division process for obtaining a value K by dividing the input value by the expected value, and 90 is a divided value K for the expected value. Branch processing to determine if it is greater than 9
Reference numeral 1 is an adding process for adding 1 as a unit value to the value of the predicted value, and 92 is a setting process for setting the predicted value as a square root solution.

The branching processing 81 divides the solution area into first area determining means, setting processing 82 and 83, and division processing 84 and 8.
5 and the addition table 86, the second area determining means for determining the solution area narrowed down by the processing, and the data table 8
7 is the extremum output unit, the process composed of the division process 89 and the branching process 90 is the verification unit, the addition process 91 is an expected solution creating unit for updating the expected solution, and the setting process 92. Corresponds to the solution decision means.

The square root operation circuit 8 configured as described above
The operation of one example will be described below. First, in the branching process 81, it is determined whether or not the input value for which the square root is to be calculated is smaller than 2560. If it is smaller, the setting process 82 is executed, and if it is equal or larger, the setting process 83 is executed. Setting process 8
After 2 is executed, the division processing 84 is executed. After the setting process 83 is executed, the division process 85 is executed. After the division processing 84 or 85 is executed, the addition processing 86 is executed. After the addition process 86 is executed, the read process 88 is executed to obtain the expected lower limit of the square root to be obtained.

Here, the values of the data table 87 referred to by the read processing 88 will be described. Table 1 shows the relationship between address 1, address 2 and the lower limit expected value.

[0025]

[Table 1]

The read process 88 outputs an expected value from the data table 87 based on the relationship (Table 1). (Table 1)
Is derived from the relationship between the solution, the square of the solution, and the address 2 shown in (Table 2).

[0027]

[Table 2]

The solution enclosed in parentheses in (Table 2) shows the expected lower limit of (Table 1). The solution enclosed in parenthesis is (square of solution / square of solution) when the square of the solution corresponding to the input value is less than 2560.
256), when it is 2560 or more, (square of solution / 10)
The solution of before and after the integer part of the value of 24) changes. In Table 2, if the result of division when the value of address 2 changes is divisible, the solution in the corresponding column is enclosed, and if the result of division is not divisible, the solution one less than the solution in the corresponding column is enclosed in parentheses. . In this way, the lower limit expected value can be obtained.

Next, the division processing 89 divides the input value by the expected value, and the branch processing 90 judges whether or not the division result is larger than the expected value. If it is larger, the addition processing 91 increases the expected value by 1 and performs division. Return to processing 89. When the division result of the division processing 89 becomes less than or equal to the expected value, the setting processing 92
Determines the expected value as the square root solution. As described above, in the example of the square root calculation circuit 8 shown in FIG. 3, as a result of preparing an expected value of the solution according to the input value and performing verification while changing the expected value, the expected value is the true solution or more. When it is determined that the answer is, the expected solution is the square root solution. In other words, the division processing 89, the branch processing 90, and the addition processing 91 are repeated several times to obtain 1
It is possible to obtain an integer solution from 1 to 150. In addition, since the (input value / expected value) is compared with the expected value as a verification method, it is possible to reduce the bit length of the microcomputer processing as compared with the case of comparing the (estimated value x expected value) with the input value. it can. Further, the comparison value of the judgment processing 81 is set to 2
By setting 560 (hexadecimal number A00), it is possible to simplify the comparison process because the lower 8 bits can be ignored in the microcomputer process for comparison. Further, by setting the denominator of the division processings 84 and 85 to be a multiple of 2, the division processing for calculating the address 2 in the microcomputer processing can be realized by bit shift, and the calculation load can be reduced.

The comparison value of the branch process 81 and the denominator of the division process may be values other than those shown in FIG. 3, and the square root can be obtained in the same manner although the number of times the process is repeated changes. Further, the branch destination of the branch processing 81 does not have to be two, and the range of solutions that can be calculated can be expanded by increasing the number of branches and the number of data in the data table 87. Further, the calculation of the addition processing 91 is configured to add 1 to the expected value, but it is obvious that subtraction may be performed if the data of the data table 87 is set to the expected value of the upper limit value.

In the second embodiment, the capstan motor 31 and the motor 22 are used for driving, but the capstan motor 31 drives the reel 101.
It is obvious that the same effect can be obtained even if the drive is driven. Further, in each of the embodiments, an example in which the transfer is performed in a single direction has been shown, but it is clear that the same effect can be obtained even when the winding side and the sending side are switched.

In each embodiment, the drive circuit 2
6, 27, period detection circuits 51, 52, square calculation circuit 5
3, 54, an adding circuit 55, a reference period sum of squares creating circuit 6,
The division circuit 7, the square root calculation circuit 8, the speed control circuit 33, the double speed conversion circuit 35, the multiplication circuit 36, and the storage circuit 37 can be configured by a microcomputer capable of measuring time, and the same effect can be obtained.

[0033]

As described above, the present invention calculates the square root of the value obtained by dividing the reference value corresponding to the reference tape speed by the sum of squares of each reel rotation cycle, without using a sensor dedicated to speed detection. Moreover, the double speed value with respect to the reference tape speed can be detected without depending on the winding position of the tape. Further, the tape speed can be obtained in a short time while being easily realized by software processing by the microcomputer. Furthermore, since the tape speed can be detected even when the reel is directly driven, it is possible to obtain the winding diameter and the remaining tape length from the reel rotation cycle, the tape speed is made constant, and the helical track is used. When it is used in the magnetic recording apparatus of the present invention, there is a possibility that special reproduction can be performed by setting the rotation speed of the drum corresponding to the tape speed, so that the effect of the present invention is very large.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a tape speed detection device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a tape speed detection device according to a second embodiment of the present invention.

FIG. 3 is a flow chart showing a configuration of a square root calculating means using a microcomputer in the first and second embodiments of the present invention.

[Explanation of symbols]

 23, 24 Frequency generator 28, 29 Tape winding means 5 Periodic sum of squares calculating means 6 Reference period sum of squares creating circuit 7 Dividing circuit 8 Square root calculating circuit 100 Tape 101, 102 Reel

Claims (2)

[Claims] 1. A take-up side reel and a delivery side reel in which both ends of the tape are respectively wound, a tape take-up means for taking up the tape on the take-up side reel, and a take-up side reel and a delivery side reel. First and second frequency generators that respectively output frequency signals proportional to the rotation speed, and cycle sum of squares computing means for calculating the sum of the squares of the cycles of the output signals of the first and second frequency generators. And a reference period square sum creating means for creating a period square sum corresponding to the reference tape speed, and a dividing means for dividing the output value of the reference period square sum creating means by the output value of the period square sum calculating means, And a square root calculating means for calculating a square root of an output value of the dividing means and outputting a value corresponding to the tape speed, and detecting a double speed value with respect to the reference tape speed. 2. A first area determination means for determining a solution region roughly divided into several areas according to an output value of the division means, and an output value of the division means corresponding to the first area. Second area determining means for determining the area of the solution further narrowed down based on the value divided by, and an extreme value output for outputting the minimum solution or the maximum solution of the area determined by the second area determining means. Means, an expected solution creating means for updating the expected solution by adding or subtracting a unit value with the output of the extreme value output means as an initial expected solution, and whether the verification error is minimum using the expected solution. A verification means for judging, and a solution determining means for outputting the predicted solution when the verification error of the verification means is minimum, and a square root output by updating the predicted solution until the verification error becomes minimum. Claims comprising means for obtaining a square root Tape speed detecting apparatus according.