JPH0993577A - Moving image decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process plural MPEG data streams with a single MPEG(moving picture image coding expert group) hardware decoder. SOLUTION: A system decoder 10 processing an MPEG data stream is provided with plural packet buffers 11-0, 11-1,... and a function of controlling an output of data stored in the packet buffers synchronously with a system time clock supplied from an STC(system time clock) module 18. Then a video decoder 13 is provided with plural record information registers 14-0, 14-1,... storing plural sets of decode information corresponding to plural data streams respectively and plural data buffers (FIFO) storing data of decode object to process plural moving image data streams with a single hardware decoder.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a plurality of types of moving image data streams (eg MPEG system stream).
The present invention relates to a moving picture decoding device capable of realizing the playback function of a single hardware resource.

[0002]

2. Description of the Related Art As a typical MPEG hardware decoder for reproducing moving picture data compressed by MPEG, there is Real Magic manufactured by SIGMA DESIGNS.
The performance of this hardware decoder is 30 fps (frame per seco) for color moving images of 352 x 240 dots size.
nd) can be decoded at the speed of.

However, in the above-mentioned conventional hardware decoder, the number of MPEG data streams that can be reproduced is limited to one (one), and a plurality of MPEG data streams cannot be reproduced. Therefore multiple M
When trying to reproduce a PEG data stream, an independent MPEG hardware decoder is required for each of a plurality of MPEG data streams handled simultaneously,
This causes various inconveniences such as a complicated structure, a large device, and a large increase in cost.

[0004]

As described above, since the conventional hardware decoder can reproduce only a single MPEG data stream and cannot reproduce a plurality of MPEG streams, a plurality of MPEG data streams cannot be reproduced. , An independent MPEG hardware decoder is required for each of a plurality of MPEG data streams handled at the same time, which causes various inconveniences such as a complicated structure, an increase in size of the apparatus, and a significant increase in cost. There was a problem.

The present invention has been made in view of the above circumstances,
A moving picture decoding in which a plurality of sets of buffers for reproducing a plurality of MPEG data streams are prepared inside the hardware decoder so that a plurality of moving picture data streams can be handled by a single hardware resource. The purpose is to provide a device.

[0006]

According to the present invention, a packet buffer for storing a plurality of video packets is provided inside a system decoder provided in an MPEG hardware decoder, and a plurality of video streams are provided inside the video decoder. It is characterized in that a plurality of registers for storing decoding information for decoding are provided so that a plurality of MPEG system streams including audio can be reproduced by one hardware resource.

That is, according to the present invention, a system decoder that handles a moving image data stream is supplied with a plurality of packet buffers for individually storing a plurality of video packets and the data stored in the plurality of packet buffers from the outside. So that a single system decoder can handle a plurality of moving image data streams by providing a means for controlling the output in synchronization with the signal that is transmitted and a means for notifying the states of the plurality of packet buffers to the outside. It is characterized by having done.

Further, according to the present invention, a video decoder for handling a moving image data stream is provided with a plurality of registers for individually storing a plurality of sets of decoding information corresponding to each data stream for decoding a plurality of moving image data streams. Is built in so that the reproduction of a plurality of moving image data streams can be executed by a single video decoder.

Further, according to the present invention, a plurality of sets of decoding information for individually storing a plurality of sets of decoding information corresponding to respective data streams for decoding a plurality of moving image data streams are provided in a video decoder which handles the moving image data streams. A register and a plurality of FIFOs provided corresponding to the register and each storing data to be decoded
A buffer and one of the above registers are selected, and the corresponding FIFO is based on the decode information stored in the register.
A decoder main body for decoding the data stored in the buffer is provided, and a plurality of moving image data streams can be reproduced by a single video decoder.

Further, according to the present invention, in a moving picture decoding device for reproducing a moving picture data stream, a system decoder having a plurality of storage means for individually storing a plurality of moving picture data streams, and storage of this system decoder. A video decoder having a plurality of storage means for individually storing a plurality of sets of decoding information for reproducing a plurality of moving image data streams stored in the means, and a plurality of moving images with a single hardware resource. The feature is that the image data stream can be reproduced in real time.

The present invention also provides a system decoder having a plurality of storage means for individually storing a plurality of moving picture data streams containing sound data, and a plurality of moving picture data streams stored in the storage means of the system decoder. A video decoder having a plurality of storage means for individually storing a plurality of sets of decoding information for reproducing, a working buffer provided for decoding processing including frame data processing of this video decoder, and It is characterized by an MPEG decoder provided with a sound buffer and a sound decoder for reproducing and outputting sound data in synchronization with a moving image.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 illustrates an M according to an exemplary embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a PEG hardware decoder, and FIG. 2 is a block diagram showing a configuration of an MPEG decoding system using the MPEG hardware decoder shown in FIG.

An MPEG hardware decoder according to an embodiment of the present invention shown in FIG. 1 is a system decoder 10 that handles a plurality of (here, four (4)) MPEG data streams, and this system decoder 10.
Video decoder 13 for individually decoding the four (4) MPEG data streams received from
And this video decoder 13 has I in the decoding process.
A decoding buffer 15 used for temporary storage of frame data such as pictures and P-pictures, an audio buffer 16 for temporarily storing audio data accompanying a moving image in an MPEG data stream, and an audio buffer 16 stored in the audio buffer 16. An audio decoder 17 for reproducing and outputting data, and an S for synchronizing reproduction.
A TC (system time clock) module 18 is used as a main element.

A system decoder 10 and a video decoder 1 which are components of the MPEG hardware decoder.
3 and the audio buffer 16 are connected to each other via a dedicated bus 102 inside the system.

System decoder 10 and video decoder 1
3, the audio decoder 17 is supplied with a clock (system time clock) output from the STC 18 via the line 106.

The system decoder 10 is supplied with each MPEG data of a maximum of four (4) MPEG data streams read from the CD drive 24 shown in FIG.

The system decoder 10 outputs an interrupt signal to the interrupt controller 21 shown in FIG. 2 via the signal line 101. The stream selection signals (0 to 3) are output to the video decoder 13 via the signal line 108.

The video decoder 13 is an internal dedicated bus 1
Display controller (VGA) 2 shown in FIG.
8 transmits the frame data to the signal line 109
Similarly, a frame identification signal (0 to 3) is sent to the display controller (VGA) 28 via.

The video decoder 13 also writes and reads frame data such as I picture and P picture in the decoding process into the decoding buffer 15 via the internal dedicated bus 103. Decoding buffer 1
5 can store a maximum of 8 frame data here.

The audio decoder 17 sends an analog audio signal synchronized with the moving image to the audio amplifier (AMP) 26 shown in FIG. 2 through the signal line 107. Inside the system decoder 10, the MPEG data of a maximum of four types (4) of MPEG data streams read from the CD drive 24 shown in FIG. 2 via the system bus 100 are streamed in video packet units. Packet buffers 11-0, 11-1, 11-2, 11-3 having four FIFO structures for individually storing each are provided, and the respective packet buffers 11-0, 11
-1, 11-2, 11-3 with 4 STC counters 1
2-0, 12-1, 12-2, 12-3 and the packet buffer status register 10A shown in FIG. 3 are provided.

Further, inside the system decoder 10, as shown in FIGS. 4A to 4E, status register information, decode register information, registered ID acquisition register information, ID registration register information, ID deletion register information. Control register 10 for generating various control information such as
B is provided.

Further, inside the above-mentioned video decoder 13, 4 (4) corresponding to each data stream for decoding each of 4 (4) MPEG data streams are provided.
Store four (4) pieces of decoding information individually 4
Record information registers 14-0, 14-1, 14-2, 1
4-3 and a data buffer (FIFO) having a FIFO structure for storing data to be decoded for each data stream.

FIG. 2 is a block diagram showing the configuration of an MPEG decoding system including the MPEG hardware decoder shown in FIG. 1 described above. Here, reference numeral 25 in the figure is the MPEG hardware decoder shown in FIG. .

In FIG. 2, reference numeral 20 denotes a CPU which controls the whole MPEG decoding system. Here, various control information as shown in FIG. Driver control processing,
Also, it controls each control of the stream multiplexer processing of the driver as shown in FIGS.

Reference numeral 21 denotes an interrupt controller for generating an interrupt to the CPU 20 in accordance with the interrupt request signal received via the interrupt request signal line 101. Here, it is received from the system decoder 10 of the MPEG hardware decoder 25 shown in FIG. An interrupt is issued to the CPU 20 in accordance with the interrupt request signal received from the SCSI interface 23, the display controller (VGA) 28, etc. described later.

Reference numeral 22 denotes a RAM in which a storage area for various programs executed by the CPU 20, a work area, and the like are formed. Here, a stream multiplexer driver (DRV) for performing processing as shown in FIGS. 6 and 8,
And the stream multiplexer driver (DRV)
A stream registration array data area (DA) used by the above is provided as shown in FIG.

23 is a SCSI interface,
Here, under the control of the CPU 20, the MPEG data read from the CD drive 24 is sent to the MPEG hardware decoder 25 via the system bus 100.

Numeral 24 indicates S via the SCSI cable 110.
CD drives connected to the CSI interface 23, each of which has a different video stream I
It is assumed that a plurality of MPEG data streams having D are stored.

Reference numeral 25 is an MPEG having the structure shown in FIG.
It is a hardware decoder, and as described above, MPE
A system decoder 10 having four packet buffers 11-0, 11-1, 11-2, 11-3 for individually storing G data streams, and four record information registers 14-0, 14-1, 14 similarly -2 and 14-3 are included in the video decoder 13, and a plurality of MPEG data streams can be reproduced in real time with a single hardware resource.

26 is an MPEG hardware decoder 25
It is an audio amplifier (AMP) for inputting an analog audio signal output from the audio decoder 17 provided in the above through a signal line 107 and amplifying the audio.
Reference numeral 27 is a speaker that outputs a sound (sound) in an audible frequency band according to the analog audio signal output from the audio amplifier (AMP) 26.

Reference numeral 28 is a display controller (VGA) for performing display control under the control of the CPU 20, and here, M
The display output of the display screen according to the frame data generated by the PEG hardware decoder 25 or the software decoder is controlled.

Reference numeral 29 is a monitor for displaying and outputting various display screen information as a visible image under the display control of the display controller (VGA) 28. Here, frame data generated by the MPEG hardware decoder 25 or software decoder is used. The display screen according to is displayed and output.

The above-mentioned CPU 20, interrupt controller 21, RAM 22, SCSI interface 23, M
The system components such as the PEG hardware decoder 25 and the display controller (VGA) 28 are connected to each other via a system bus 100 having address and data lines.

The interrupt controller 21 is connected to the SCSI interface 23 via the interrupt request signal line 101,
The interrupt signal is received from the MPEG hardware decoder 25, the display controller (VGA) 28, etc., and the interrupt signal is sent to the CPU 20 via the interrupt request signal line 113.

In addition, the MPEG hardware decoder 25
Sends frame data and frame identification signals (0 to 3) to the display controller (VGA) 28 via the dedicated bus 105 and the signal line 115 inside the system.

The SCSI interface 23 converts the MPEG data read-accessed by the CD drive 24 into S
It is input via the CSI cable 110 and sent out on the system bus 100 under the control of the CPU 20. The MPEG data transmitted on this system bus 100 is MPE.
Is sent to the G hardware decoder 25 and decoded, or decoded by a software decoder,
It is sent to the display controller (VGA) 28.

FIG. 3 is a diagram showing the internal register arrangement of the packet buffer status register 10A provided in the system decoder 10 of the MPEG hardware decoder 25. By referring to the contents of the packet buffer status register 10A, various control information shown in FIG. 4 is generated on the control register 10B.

The register array of this packet buffer status register 10A has four elements.
Stream ID, operation mode, PTS offset, PT
There is an area for writing the S initial value.

FIG. 4 is a diagram showing a data structure of each control information generated on the control register 10B in the system decoder 10. Here, each control information generated on the control register 10B is referred to as register information. And CP
The types of register information that the U20 can access include status register information, decode control register information, registration ID acquisition register information, ID registration register information, and I.
There is D deletion register information and the like.

FIG. 5 is a flow chart showing the control procedure of the stream multiplexer process in the decoder application for controlling the stream multiplexer driver (DRV) placed on the RAM 22.

FIG. 6 is a flow chart showing the procedure of the stream multiplexer process executed by the stream multiplexer driver (DRV) placed on the RAM 22.

FIG. 7 is a diagram showing the structure of the stream registration array data area (DA) of the stream multiplexer driver (DRV) placed on the RAM 22. Here, the array number is assigned to each of the four streams. (0 to 3), file name, stream ID, and operation mode are registered.

FIG. 8 is a flow chart showing the flow of the interrupt processing routine in the stream multiplexer processing, which is the packet buffer (FIFO buffer) 11-i (i = 0 to 3) generated from the system decoder 10.
) Is executed each time an interrupt request for notifying the empty state is received by the CPU 20.

FIG. 9 shows the structure of the system stream (a).
FIG. 10 is a diagram showing the structure (b) of the pack data, FIG. 10 is a diagram showing the structure of the system header, and FIG. 11 is a diagram showing the structure of the packet data.

The operation of the embodiment of the present invention will be described with reference to the drawings. In this embodiment,
MPE that can be played back by the MPEG hardware decoder 25
As a condition of the G system stream, it is assumed that the video stream IDs included in each are different. The playback speed is set to 25 fps in this embodiment because the PTS offset of each of the four (4) streams that can be handled by the MPEG hardware decoder 25 is set to 10 msec.

The CPU 20 accesses various control register information shown in FIG. 4 from the system decoder 10.
The type of control register information accessed by the system decoder 10 from the CPU 20 includes status register information having a structure shown in FIG. 4A, decode control register information having a structure shown in FIG. Registered ID acquisition register information having the structure shown in FIG. 7C, ID registration register information having the structure shown in FIG. 7D, and ID having the structure shown in FIG.
There is deletion register information and the like. The control register information is generated and accessed on the control register 10B by the CPU 20 designating the internal address of the system decoder 10.

Of the above control register information, the status register information can be accessed by accessing the internal addresses of the system decoder "0x00", "0x01", "0x0".
It is performed by accessing 2 "and" 0x03 ".
When "0x00" is accessed, the status for the video stream set in the packet buffer 0 (11-0) is returned, and when "0x01" is accessed, the packet buffer 1 (11-1) is returned. Returns the status for the set video stream and returns "0x
02 "is accessed, the packet buffer 2 (1
When the status for the video stream set to 1-2) is returned and "0x03" is accessed,
The status for the video stream set in the packet buffer 3 (11-3) is returned.

The status register information item is shown in FIG.
As shown in (a), operation status [A], FIFO
empty (packet buffer 11-i is empty) [B], F
IFO full (packet buffer 11-i is full)
[C] and stream ID [D].

The operation status [A] is the stream ID
The status is “0x0” when playing.
1 "," 0x00 "for Stop," 0x02 "for Pause," 0 "for Step (frame advance)
x03 "is set.

FIFO empty [B], FIFO full
In the item [C], the corresponding packet buffer (0 to
3) 11-0, 11-1, 11-2, 11-3 are empty
), FIFO empty [B] is set to “1”, and when full (full), FIFO full [C] is set to “1”.

To access the decode control register information,
This is performed by accessing "0x04" with the internal address of the system decoder 10. As shown in FIG. 4B, the items of the decode control register information include the decode control information [A] and the stream ID [B], and the status register for the stream specified by the stream ID [B]. Specify the same decoding control information as the operation status of the information.

Acquisition of registration ID The register information can be accessed by accessing the internal address “0x0” of the system decoder 10.
5 ". The registered ID acquisition register information item has four registered stream IDs as shown in FIG. 4C (stream ID).
0 [A], stream ID 1 [B], stream ID 2
[C], stream ID 3 [D]). "0x00" is set to the unregistered stream ID.

The ID registration register information is accessed by accessing "0x06" with the internal address of the system decoder 10. As shown in FIG. 4D, the item of the ID registration register information includes the array element number [B].
And the registration ID value [A], and the registration ID is assigned to the packet buffer 11-i indicated by the array element number [B].

The access to the ID deletion register information is performed by accessing "0x07" with the internal address of the system decoder 10. As shown in FIG. 4E, the item of the ID deletion register information includes the array element number [A].
And the stream I specified by this array number [A]
D is deleted.

When the CPU 20 registers the ID in accordance with the ID registration register information from the CPU 20, the packet decoder status register 10A shown in FIG.
The registration ID according to the array element number designated by the ID registration register is written in.

At this time, a code indicating Stop is written as an initial value in the item of operation mode. Then, in the packet buffer 11-i having the same array number,
The packet data having the designated stream ID is stored.

Further, at this time, the system decoder 10 stores the PTS value first appearing in the packet information in the system stream to be decoded in the PTS initial value item in the packet buffer status register 10A of FIG.

The added value of the stored PTS value and PTS offset is compared with the PTS value of the system stream to be registered at the time of next ID registration, and if they are not the same value, they are registered as they are, and if they are the same value. For example, if the PTS offset indicated by the array element number specified in the ID registration register is "1.
0 ”(count value for 10 msec) is added. This added value is compared with other stored PTS values, and if they are not the same value, the added value is stored as an offset in the PTS offset storage position shown by the array element number in FIG. If the values are the same, the same operation as above is repeated.

When the CPU 20 accesses the decode control register information, the system decoder 10 writes the specified decode control information in the operation mode item of the packet buffer status register 10A specified by the stream ID.

The decoding control information that can be specified here includes:
Play: “0x01”, Stop: “0x00”, Pause:
There are four types, "0x02" and Step: "0x03". For example, when Stop: “0x00” is set to Play: “0x01”, the system decoder 10 starts the decoding process of the stream in which the operation mode is designated.

When system stream data is input from the CPU 20 to the system decoder 10 via the system bus 100, the system decoder 10 divides the data into video packets and audio packets, and the packet data divided into video packets is divided into video packets. Stream ID
The packet buffer status register 10 shown in FIG.
The video packet data is stored in the packet buffer 11-i designated by the corresponding array element number as compared with the stream ID item of A.

STC counter 1 of system decoder 10
2 counts the system time clock input from the STC module 18. For example, the value obtained by subtracting the value of PTS offset 0 from the value of STC counter 0 (12-0) and the PT included in packet buffer 0 (11-0).
When the S / DTS becomes the same value, the system decoder 10
The stream selection signal (0) is sent to the video decoder 13 via the signal line 108, and the packet data stored in the packet buffer 0 (11-0) is transferred.

This operation is performed from packet buffer 0 to packet buffer 3 (11-0 to 11-3). The packet buffers 0 to 3 (11-0, 11-1, 11
When either -2, 11-3) becomes empty,
The system decoder 10 sends an interrupt request signal to the interrupt controller 21 via the signal line 101 to notify the interrupt controller 21 of the occurrence of an interrupt.

Upon receiving the notification of the interrupt request signal from the MPEG hardware decoder 25, the interrupt controller 21 notifies the CPU 20 via the signal line 113 that an interrupt has occurred.

Upon receipt of the interrupt notification, the CPU 20 activates and executes an interrupt processing routine as shown in FIG. The interrupt processing routine will be described later.

The video decoder 13 is designated by the system decoder 10 (transmitted via the signal line 108).
Decoding information used for decoding processing is selected in accordance with the stream selection signal (0 to 3).

The decode information selected is 4 as shown in FIG.
One record information register 14-0, 14-1, 14-2, 1
This is one of the pieces of decoding information stored in 4-3. This record information register 14-0, 14-1, 14-2, 14
The decode information stored in -3 includes the content of the sequence header included in the video stream, and when the sequence header appears in the video stream, the content is updated by overwriting.

The video decoder 13 uses this information to decode the video stream information sent from the system decoder 10. At this time, the video decoder 13
Uses the decoding buffer 15 as a storage destination of frame data such as I picture and P picture in the decoding process. The decoding buffer 15 has a size capable of storing a maximum of 8 frame data.

The frame data decoded by the video decoder 13 is sent to the display controller (VGA) 28 via the dedicated bus 105 inside the system. At the same time, a frame identification signal (0 to
3) is also sent to the display controller (VGA) 28.

Now, consider the case of decoding one system stream. The stream ID 0 of the video packet registered in the array element number 0 is registered in the system decoder 10 by the ID registration register.

Now, with the decode control register for the system decoder 10, the stream ID 0, Play:
It is assumed that “0x01” is set. At this time, the STC counter 12-0 is reset.

Since the packet buffer 11-0 is empty, the system decoder 10 sends an interrupt request signal to the interrupt controller 21 via the signal line 101 to notify the occurrence of an interrupt.

When the interrupt controller 21 receives the interrupt request signal, it notifies the CPU 20 that an interrupt has occurred. Upon receiving the notification of the interrupt, the CPU 20 activates the interrupt processing routine in the stream multiplexer processing of the driver as shown in FIG.

In this interrupt processing routine, the packet buffer status register 10A is referred to and the FIFO
Packet buffer 11 with the empty flag set
For -i, the pack data of the file designated by the stream ID is transferred to the system decoder 10 via the system bus 100 (steps 400 to 403 in FIG. 8).

The system decoder 10 divides the input pack into packets, refers to the stream ID (streamID) included in the packet data, and stores them in the designated packet buffers 11-i.

The PTS data that first appeared at this time is shown in FIG.
P of the packet buffer status register 10A shown in
Store in the TS initial value item. Then, the offset obtained by comparison by the means described above is stored in the PTS offset 0 of the packet buffer status register 10A shown in FIG.

When the packet data of stream ID 0 is stored in the packet buffer (0) 11-0, the STC counter (0) 12-0 starts counting the system time clock from the STC module 18.

When the value obtained by subtracting the PTS offset 0 from the value of the STC counter (0) 12-0 and the PTS and DTS of the video packet data stored in the packet buffer (0) 11-0 become the same value, the system Decoder 1
0 notifies the video decoder 13 of the stream selection signal (0) of the stream 0 via the signal line 108, extracts the video stream from the packet data stored in the packet buffer (0) 11-0, and outputs the stream inside the system. The video data is transferred to the video decoder 13 via the dedicated bus 102.

If the packet is an audio packet, the audio stream included in the packet is transferred to the audio buffer 16 via the dedicated bus 102 inside the system. The audio decoder 17 includes the audio buffer 1
The audio data stream transferred to No. 6 is decoded, and the decoded analog audio signal is output to the analog signal line 107.

In the video decoder 13, according to the input stream selection signal, the record information register 14-0,
Select one register from 14-1, 14-2, 14-3,
The decode information used for the decode processing is selected, and the decode processing is performed according to the decode information.

The decoded frame data is output to the dedicated bus 105 inside the system, and at the same time, the frame identification signal is output to the signal line 109. The number designated by this frame identification signal and the number used when selecting the decode information are the same. For example, the frame data decoded by using the decode information 2 of the record information register 14-2 is "2" as the frame identification signal.
Is specified.

Although the above-described operation has considered the case of decoding one system stream, the case of registering the second system stream will be considered here. The stream ID 1 of the video packet registered in the array element number 1 is registered in the system decoder 10 by the ID registration register information.

The flow of registration is the same as that described above, but the work of calculating the PTS offset is added. In the system decoder 10, when the stream indicated by the stream ID 1 is stored in the packet buffer 1 (11-1), the PTS value that appears first and the PTS value already registered, P
The TS initial value and the added value of the PTS offset are compared, and if they are the same value, “10” is added to the PTS offset 1. PTS offset 1 when all comparisons are completed
The content of is decided.

The timing of transferring the video stream included in the packet data to the video decoder 13 is as follows.
PTS value and S contained in packet buffer 1 (11-1)
When the value obtained by subtracting the PTS offset 1 from the TC counter 1 (12-1) becomes the same value, it is transferred to the video decoder 13.

Here, a plurality of stream data are MPEG
A process for controlling the supply to the hardware decoder 25 will be described. FIG. 5 shows a processing flow of the decoder application for the stream multiplexer driver (DRV) for supplying and controlling the system stream to the MPEG hardware decoder 25.

Here, if the operation mode is set, for the stream multiplexer driver (DRV),
Operation mode for the file to be set (Play / Stop
/ Pause / Step) notification (step 20 in FIG. 5)
0,201).

For stream file open processing, the stream multiplexer driver (DRV)
The stream file name to be decoded is registered in the stream registration array data area (DA) shown in FIG. 7 (steps 202 and 203 in FIG. 5).

At this time, the MPEG hardware decoder 2
When the stream file names of all four streams are registered in 5, the registration failure occurs, and instead of the hardware decoder 25, the software decoder corresponding to the stream instructed to be reproduced is activated and reproduced (see FIG. 5 steps 204, 205).

FIG. 6 shows a processing flow of the above stream multiplexer driver (DRV). Here, when the operation mode setting notification is received from the decoder application shown in FIG. 5, the decode control register information is accessed to the system decoder 10 to write the decode control information (step 30 in FIG. 6).
0,306).

When the operation mode is not set, the file name of the stream notified from the decoder application is registered in the stream registration array data area (DA) shown in FIG. 7 (step 301 in FIG. 6).

At this time, if the file name of the stream cannot be registered, an error is notified to the decoder application and the process ends (steps 302 and 303 in FIG. 6). When the stream file name is registered, the stream ID is registered by extracting the stream ID from the notified stream file and accessing the ID registration register information to the system decoder 10 (step 304 in FIG. 6). , 305).

FIG. 8 shows the flow of the interrupt processing routine in the above stream multiplexer. The interrupt request from the system decoder 10 is the CPU
When accepted by 20, the interrupt processing routine shown in FIG. 8 is executed, the status register information shown in FIG. 4A is accessed to obtain the status of the stream registered in the system decoder 10, and the status for counting is obtained. The variable I is set to "0" (step 400 in FIG. 8).

Next, the FIFO empty flag of the array number I is checked. If the flag is set (if it is "1"), the pack data is extracted from the file specified by the array number I and the system decoder 10 (steps 401, 402, 403 in FIG. 8).

Next, the variable I for counting is incremented, I> 3 is checked, and when the result becomes true, the interrupt processing routine ends (steps 404 and 405 in FIG. 8).

FIG. 9 shows the structure of the system stream (FIG. 9A) and the structure of the pack data (FIG. 9B). The system header in the pack (system header ())
And packet data (packet ()).

FIG. 10 shows the structure of the system header. Stream id in the system header indicates the stream ID of video or audio. FIG. 11 shows the structure of packet data. In the packet data, PTS (presentation time stamps), DTS (de
coding time stamp) and the packet data size (pa
cketdata byte) is defined.

As described above, according to the embodiment of the present invention, a plurality of packet buffers 11-0, 11-1, 11 for individually storing a plurality of video packets are stored in the system decoder 10 which handles an MPEG data stream. -2, 1
1-3 and this packet buffer 11-0, 11-1, 11-
The STC module 18 uses the data stored in 2, 11-3.
A function of controlling output in synchronization with a system time clock supplied from the video decoder 13, and the video decoder 13 individually stores a plurality of sets of decoding information corresponding to each data stream for decoding the plurality of data streams. Multiple record information registers 14-0, 14-
1, 14-2, 14-3 and this register 14-0, 14-1,
Corresponding to 14-2 and 14-3, a plurality of data buffers (FIFOs) for storing the data to be decoded and one of the above registers are selected, and the decode information stored in the register 14-i is selected. Original data buffer (FIFO)
A decoder main body for decoding the data stored in the above is provided, and a plurality of moving image data streams can be handled by a single hardware decoder, so that a plurality of MPEG data streams are handled in parallel. When realizing a possible MPEG hardware decoder, it is possible to realize inexpensive and compact with a simple configuration without providing an independent MPEG hardware decoder for each of a plurality of MPEG data streams handled at the same time.

[0098]

As described above in detail, according to the present invention, the hardware decoder is provided with a plurality of sets of buffers for reproducing a plurality of MPEG data streams and a plurality of stream control functions. Thus, it is possible to provide a moving picture decoding device capable of reproducing a plurality of moving picture data streams in real time with a single hardware resource.

That is, according to the present invention, a system decoder that handles a moving image data stream includes a plurality of packet buffers for individually storing a plurality of video packets,
Means for controlling the output of the data stored in the plurality of packet buffers in synchronization with a signal supplied from the outside,
With the configuration including means for notifying the states of the plurality of packet buffers to the outside, a plurality of moving image data streams can be reproduced in real time by a single system decoder.

Further, according to the present invention, a plurality of sets of decoding information respectively corresponding to each data stream for decoding a plurality of moving image data streams are individually stored in a video decoder which handles the moving image data stream. With the configuration in which the register is built in, a plurality of moving image data streams can be reproduced by a single video decoder.

Further, according to the present invention, a plurality of sets of decoding information for individually storing a plurality of sets of decoding information corresponding to each data stream for decoding a plurality of moving image data streams are stored in a video decoder which handles the moving image data streams. It is provided corresponding to this register and this register,
Multiple Fs that store the data to be decoded
Select the IFO buffer and one of the above registers, and use the corresponding F based on the decode information stored in the register.
With the configuration including the decoder main body for decoding the data stored in the IFO buffer,
Playback of multiple video data streams can be performed by a single video decoder.

Further, according to the present invention, in a moving picture decoding apparatus for reproducing a moving picture data stream, a system decoder having a plurality of storage means for individually storing a plurality of moving picture data streams, and this system decoder And a video decoder having a plurality of storage means for individually storing a plurality of sets of decoding information for reproducing a plurality of moving image data streams stored in the storage means of With multiple hardware resources, multiple moving image data streams can be played in real time.

Further, according to the present invention, a system decoder having a plurality of storage means for individually storing a plurality of moving image data streams including sound data, and a plurality of moving images stored in the storage means of the system decoder. A video decoder having a plurality of storage means for individually storing a plurality of sets of decoding information for reproducing a data stream, a working buffer used for decoding processing including frame data processing of the video decoder, and the data stream. By configuring the MPEG decoder with a sound buffer and a sound decoder for reproducing and outputting the sound data therein in synchronization with a moving image, a plurality of moving image data streams can be reproduced in real time with a single hardware resource.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an MPEG hardware decoder according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of an MPEG decoding system including the MPEG hardware decoder shown in FIG.

FIG. 3 is a diagram showing an internal register arrangement configuration of a packet buffer status register 10A provided in the system decoder 10 of the MPEG hardware decoder 25 in the above embodiment.

FIG. 4 is a system decoder 10 in the above embodiment.
6 is a diagram showing a data structure of each control information generated on the control register 10B in FIG.

FIG. 5 is a flowchart showing a control procedure of stream multiplexer processing in a decoder application for controlling a stream multiplexer driver (DRV) placed on the RAM 22 in the above embodiment.

FIG. 6 is a flowchart showing a procedure of stream multiplexer processing executed by a stream multiplexer driver (DRV) placed on the RAM 22 in the above embodiment.

FIG. 7 is a diagram showing a configuration of a stream registration array data area (DA) of a stream multiplexer driver (DRV) placed on a RAM 22 in the above embodiment.

FIG. 8 is a flowchart showing a flow of an interrupt processing routine in stream multiplexer processing in the above embodiment.

FIG. 9 is a diagram showing a structure (a) of a system stream and a structure (b) of pack data.

FIG. 10 is a diagram showing the structure of a system header.

FIG. 11 is a diagram showing a structure of packet data.

[Explanation of symbols]

10 ... System decoder, 10A ... Packet buffer status register, 10B ... Control register, 11-0, 1
1-1, 11-2, 11-3 ... Packet buffer, 12-0, 1
2-1, 12-2, 12-3 ... STC counter, 13 ... Video decoder, 14-0, 14-1, 14-2, 14-3 ... Record information register, 15 ... Decoding buffer, 16 ... Audio buffer , 17 ... Audio decoder, 18 ... S
TC (system time clock) module, 20 ... C
PU, 21 ... Interrupt controller, 22 ... RAM, 2
3 ... SCSI interface, 24 ... CD drive,
25 ... MPEG hardware decoder, 26 ... Audio amplifier (AMP), 27 ... Speaker, 28 ... Display controller (VGA), 29 ... Monitor, DRV ... Stream multiplexer driver, DA ... Stream registered array data area.

Claims (8)

[Claims] 1. A plurality of packet buffers for individually storing a plurality of video packets, a means for controlling output of the data stored in the plurality of packet buffers in synchronization with a signal supplied from the outside, and Means for notifying the states of the plurality of packet buffers to the outside,
A system decoder characterized by being able to handle multiple moving image data streams with a single hardware resource. 2. A system decoder according to claim 1, further comprising means for identifying a storage destination packet buffer by identifying a stream ID included in the system stream. 3. The system decoder according to claim 1, further comprising means for updating and controlling the synchronous data contained in the data stream corresponding to each of the plurality of packet buffers. 4. A plurality of FIFO buffers constituting a plurality of packet buffers, and an STC counter for synchronization control provided corresponding to the FIFO buffers.
2. The system decoder according to claim 1, further comprising a control register for managing data in the FIFO buffer. 5. A plurality of registers for individually storing a plurality of sets of decoding information corresponding to each data stream for decoding a plurality of moving image data streams are built-in to reproduce a plurality of moving image data streams. A video decoder characterized by being able to execute with a single hardware resource. 6. A plurality of registers for individually storing a plurality of sets of decoding information corresponding to each data stream for decoding a plurality of moving image data streams, and a register provided corresponding to each of the registers, respectively. A FIFO buffer for storing target data and a decoder main body for selecting one of the above registers and decoding the data stored in the corresponding FIFO buffer based on the decode information stored in the register are provided. The video decoder is characterized in that a plurality of moving image data streams can be played back by a single hardware resource. 7. A system decoder having a plurality of storage means for individually storing a plurality of moving image data streams, and a plurality of sets for reproducing the plurality of moving image data streams stored in the storage means of the system decoder. A moving picture decoding apparatus comprising: a video decoder having a plurality of storage means for individually storing decoding information, and capable of reproducing a plurality of moving picture data streams in real time with a single hardware resource. 8. A system decoder having a plurality of storage means for individually storing a plurality of moving picture data streams containing sound data, and for reproducing the plurality of moving picture data streams stored in the storage means of the system decoder. A video decoder having a plurality of storage means for individually storing a plurality of sets of decoding information, a working buffer used for decoding processing including frame data processing of the video decoder, and sound data in the data stream as a moving image. An MPEG decoder comprising a sound buffer and a sound decoder for reproducing and outputting in synchronization with an image.