JPH0993292A - Quaternary fsk detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a quaternary FSK detection circuit in which miniaturization, power saving and necessitating no adjustment are attainable. SOLUTION: A quaternary FSK signal is converted into an I-phase signal and a Q-phase signal, and a D-flip-flop circuit receiving the I-phase signal at its data terminal and the Q-phase signal at its clock terminal is used to produce binary judgment output. Then the correlation among the I-phase signal, a 1st reference frequency shift signal and a 2nd reference frequency shift signal is taken and the correlation among the Q-phase signal, the 1st reference frequency shift signal and the 2nd reference frequency shift signal is taken, and a comparator judges the polarity of the sum of correlation outputs and outputs them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting a 4-level FSK signal.

[0002]

2. Description of the Related Art FIG. 6 shows an example of a conventional four-value FSK detection circuit using a frequency discriminator. An intermediate frequency (IF) four-value FSK signal is input to a frequency discriminator 11. To be done. As shown in FIG. 7, the four-level FSK signal input to the frequency discriminator (DISC) 11 has a frequency shift amount (Δf) when input.
According to the output voltage (V). At this time, the comparator circuits 12-1, 12-2, 12-3 that apply the reference threshold voltage (V _{th1 to} V _th3 ) to the comparator circuits 12-1, 12-2, 12-3 are the DISC1.
The output from 1 and the threshold voltage (V _{th1 to} V _th3 ) determine the output at each position shown by the dotted line with respect to the eye pattern of FIG. Comparator circuits 12-1, 12-
The outputs of 2 and 12-3 enter the encoder 13 and the code is reproduced.

[0003]

A heterodyne reception system is a configuration of a receiver conventionally used as an FSK detection circuit. In this configuration, since the intermediate frequency (IF) is used, the image frequency signal exists, and it is necessary to take a measure to remove it. Therefore, the circuit scale becomes large. That is, a filter circuit is required to remove the image frequency. Therefore, the physical size is restricted, which is not suitable for miniaturization of the circuit. Further, since the frequency discriminator that detects the FSK frequency deviation is configured by using the analog circuit of the resonance circuit, it is necessary to make adjustments and compensations to cope with changes in environmental conditions such as temperature and aging. There are drawbacks such as There is a direct conversion reception system as one technique to overcome this. With this configuration, the baseband signal is directly extracted without using the intermediate frequency, so that there is an advantage that the circuit scale can be significantly reduced. However, most of the application examples of the direct conversion reception system to the FSK detection circuit are binary FSK, and the application technology to the four-level FSK is under study.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a four-valued FSK detection circuit which eliminates the above-mentioned drawbacks of the prior art, and which can be downsized, consume less power and need no adjustment.

[0005]

In order to achieve this object, a 4-valued FSK detection circuit according to the present invention converts a 4-valued FSK signal into two baseband signals I and Q which are orthogonal to each other. And a binary determination F for performing binary FSK detection by phase comparison between the I-phase signal and the Q-phase signal.
An SK detection circuit, a first frequency deviation reference circuit that outputs a signal of a first reference frequency deviation, a second frequency deviation reference circuit that outputs a signal of a second reference frequency deviation, and I
A first correlation circuit that correlates a phase signal with the signal having the first reference frequency shift, and a second correlation circuit that correlates the I-phase signal with the signal having the second reference frequency shift And a third correlation circuit for correlating the Q-phase signal with the signal of the first reference frequency deviation, and a third correlation circuit for correlating the Q-phase signal with the signal of the second reference frequency deviation. 4 correlation circuit, an addition circuit for adding the respective outputs of the first, second, third and fourth correlation circuits, and a comparator for judging the polarity of the output of the addition circuit. ing.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION According to the present invention, a 4-value FSK signal is converted into an I-phase signal and a Q-phase signal, and the I-phase signal is input to a data terminal and the Q-phase signal is input to a clock terminal. A value judgment output is performed to correlate the I-phase signal with the signal of the first reference frequency deviation and the signal of the second reference frequency deviation, respectively, and the Q signal and the signal with the first reference frequency deviation It has a configuration in which the correlation with the signal of the second reference frequency deviation is respectively obtained, and the polarity of the addition output obtained by adding the correlation outputs is judged by a comparator, and the output is made compact, power saving, and no adjustment is required. 4-level FSK that can be achieved
Realizes a detection circuit.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an embodiment of the present invention. The received four-level FSK signal is converted into the I-phase signal and the Q-phase signal which are baseband signals orthogonal to each other by the direct conversion method, and then input to the circuit of this embodiment. Here, 1 is a comparator circuit for I-phase signals, 2
Is a Q-phase signal comparator circuit, 3 is a 2FSK detection circuit, 4-1 and 4-2 are frequency shift reference circuits that generate signals with reference frequency shifts ΔF1 and ΔF2, 5-1 and 5-2.
5-3 and 5-4 are I-phase signals and ΔF1, I-phase signals and ΔF
2. Correlation circuit for correlating each of the Q-phase signal and ΔF1 and the Q-phase signal and ΔF2, 6 is an adder, 7 is a comparator, 8 is an output terminal of Δf, and 9 is an output terminal of 0, 1 judgment output. is there. In this embodiment, the binary FSK detection circuit 3 includes, for example, a data terminal D and a clock terminal C of a D flip-flop circuit.
It can be realized by a phase comparison circuit configuration in which two signals of I phase and Q phase are input to L. At this time, the output is I
A binary value of "0" or "1" is determined and output depending on whether the phase relationship between the two signals of the phase and Q phases is ahead of or behind the other. Therefore, the output 9 outputs the rotation direction of the vector when the input signal is represented by the vector I + jQ, that is, the polarity of the instantaneous frequency deviation Δf (= binary FSK detection output value) with respect to the center frequency of the carrier of the received input wave IN. ing. The correlation circuits 5-1, 5-2, 5-3, 5-4 are
At the sample time, it is equivalent to reception by the matched filter. The frequency of the input signal is the reference frequency deviation ΔF ₁ , Δ
When it becomes the same as F ₂ , the correlation circuits 5-1, 5-2, 5-
The correlation outputs of 3 and 5-4 are maximum. That is, the correlation circuit 5
Received input wave I by -1,5-2,5-3,5-4
The degree of approximation between the carrier instantaneous frequency shift number Δf of N and ΔF ₁ and ΔF ₂ is output. These outputs are added by the adder 6, and the signal output to the output terminal 8 through the comparator 7 is the instantaneous frequency deviation Δ of the carrier of the received input wave.
It shows which f is closer to ΔF ₁ or ΔF ₂ .

FIG. 2 shows a direct conversion circuit 10
In the balanced modulation circuit 10-, the signal waves L ₁ and L ₂ from the local oscillator 10-1 having the same oscillation frequency as the frequency of the received input wave IN and orthogonal to each other and the received input wave IN are shown. Multiply by 2, 10-3, and low-pass filter (LP
F) Quadrature baseband signals I and Q at 10-4 and 10-5
Is extracted.

FIG. 3 shows the correlation circuits 5-1, 5-2, 5-.
It is a block diagram showing an example of composition of processing of 3 and 5-4.
1 is an input terminal for inputting signals of reference frequency shifts ΔF1 and ΔF2, 22 is an input terminal for I-phase signal and Q-phase signal, 23 is a 90 ° phase shifter, 24 is a signal of ΔF1 or ΔF2 and I-phase signal or A multiplier for multiplying with a Q-phase signal, 25 is a multiplier for multiplying a signal obtained by phase-shifting a signal of ΔF1 or ΔF2 by 90 ° and an I-phase signal or a Q-phase signal, and 26 and 27 are low-pass filters. Reference numeral 28 is a square sum calculator having X and Y as inputs. With the above configuration, the correlation calculation output X ² between the input signal I (or Q) and the frequency ΔF ₁ (or ΔF ₂ )
+ Y ² is obtained, and the degree of approximation between the fluctuation frequency of the signal I (or Q) and the reference frequency ΔF ₁ (or ΔF ₂ ) is calculated at this output. When both the I-phase and Q-phase input signals and the reference frequency signal are binary-shaped waveforms, the multipliers 24 and 25 are an exclusive OR, and the LPF is a moving average circuit using a shift register or a counter. Can be replaced respectively. Here, an example of the configuration of the moving average circuit is shown in FIG. In the figure, CLK is a clock signal for calculating the moving average value, and XOR is the exclusive OR output. Further, 81 is an m-bit shift register, and 82 is an up / down counter. By connecting as shown,
The output X (Y) of the up / down counter 82 shows a value obtained by counting the number of polarities "1" in m samples of continuous XOR, so that it is understood that a moving average value of m samples of XOR can be obtained. Further, the sum-of-squares calculator may be replaced with a sum of absolute values, which can be easily realized by using a recording element such as a ROM table. From the above, it can be seen that the correlation circuit can be realized by a digital circuit.

FIG. 4 is a diagram summarizing the operating principle of the embodiment of FIG. The vertical axis of the figure corresponds to the instantaneous frequency deviation Δf of the received input wave IN, and the areas with ± ΔF ₁ and ± ΔF ₂ are determined as four values of −ΔF ₂ , −ΔF ₁ , + ΔF ₁ , and + ΔF _2. It shows the area. The alternate long and short dash line indicates the boundary of each area, that is, the threshold. 4A shows the operation of obtaining the judgment result by the binary judgment circuit 3 at the output terminal 9, and FIG. 4B shows the correlation circuit 5-1, 5-2, 5-3, 5
-4, adder 6 and comparator 7 output the judgment result output terminal 8
Shows the operation to get to. As shown, output terminal 9
The bit of the instantaneous frequency deviation Δf (whether + ΔF ₁ , + ΔF ₂ hatched with diagonal lines or −ΔF ₁ , −ΔF ₂ hatched with dots) is used to determine the 1-bit value of the output terminal 8. Then, it is determined whether the absolute value of the frequency deviation is ΔF ₁ for dot hatching or ΔF _{2 for} diagonal hatching. In this way, the total of 2 bits obtained at the output terminals 8 and 9 provides an output for determining each value (four values) of the four-valued FSK.

[0011]

As described in detail above, according to the present invention, it is possible to reduce the size of a receiving circuit using a 4-level FSK detection circuit. Further, since digital processing is possible, power saving and no adjustment can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a direct conversion circuit used in the present invention.

FIG. 3 is a block diagram showing an example of a correlation circuit used in the present invention.

FIG. 4 is a schematic diagram showing a determination operation in the present invention.

FIG. 5 is a block diagram showing a configuration example of a moving average circuit used in the present invention.

FIG. 6 is a block diagram showing an example of a conventional 4-level FSK detection circuit.

FIG. 7 is a characteristic diagram for explaining the operation of the circuit of FIG.

FIG. 8 is a characteristic diagram for explaining the operation of the circuit of FIG.

[Explanation of Codes] 1, 2 Comparator circuit 3 2 value FSK detection circuit 4-1, 4-2 Frequency deviation reference circuit 5-1, 5-2, 5-3, 5-4 Correlation circuit 6 Adder 7 Comparison Device 8, 9 Output terminal 10 Direct conversion circuit 10-1 Local oscillator 10-2, 10-3 Balanced modulation circuit 10-4, 10-5 Low-pass filter 11 Frequency discriminator 12-1, 12-2, 12-3 Comparator circuit 13 Encoder 23 90 ° phase shifter 24, 25 Multiplier 26, 27 Low pass filter 28 Square sum calculator 81 m-bit shift register 82 Up-down counter

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenzo Urabe 3-14-20 Higashi-Nakano, Nakano-ku, Tokyo Kokusai Electric Co., Ltd.

Claims (4)

[Claims] 1. Binary FSK detection by means for converting a 4-valued FSK signal into two baseband signals I-phase signal and Q-phase signal which are orthogonal to each other, and phase comparison between the I-phase signal and the Q-phase signal. A binary FSK detection circuit, a first frequency shift reference circuit that outputs a signal with a first reference frequency shift, and a second frequency shift reference that outputs a signal with a second reference frequency shift A circuit, a first correlation circuit for correlating the I-phase signal with the signal having the first reference frequency shift, and a circuit for correlating the I-phase signal with the signal having the second reference frequency shift A second correlation circuit; a third correlation circuit that correlates the Q-phase signal with the signal with the first reference frequency shift; and the Q-phase signal with the signal with the second reference frequency shift And a fourth correlation circuit for taking the correlation of each of the first, second, third and fourth correlation circuits An adder circuit for adding the force, quaternary FSK detection circuit and a comparator determining the polarity of the output of said adder circuit. 2. A 90 ° phase shifter for shifting one of the two signals by 90 °, and the correlation circuit for multiplying the two signals and the 90 ° phase shifted signal by the other signal. First and second multipliers, and first and second low-pass filters for low-pass filtering the respective outputs of the first and second multipliers,
4. The four-valued FSK detection circuit according to claim 1, wherein the four-valued FSK detection circuit comprises a sum of squares calculator for summing the respective outputs of the first and second low-pass filters. 3. The four-valued F according to claim 2, wherein the sum of squares calculator is replaced with a calculator for summing absolute values.
SK detection circuit. 4. The first and second multipliers are respectively connected to first and second exclusive OR circuits, and the first and second multipliers are respectively provided.
4. The four-valued F according to claim 2, wherein the low-pass filter is replaced by first and second moving average circuits, and the square sum calculator is replaced by a ROM table.
SK detection circuit.