JPH0991968A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory in which the operating time is shortened at the time of list award activation while suppressing the increase of device area retaining the X address information of sense word activation at a self boost node until the moment of list award activation. SOLUTION: High potential at the self boost nodes 101, 102 of an X decoder circuit selected at the time of sense word activation is retained until the moment of list award activation. A retaining circuit is provided at the self boost nodes 101, 102 of X decoder circuit in order to retain the X address of sense word at each bank until the moment of list award activation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using a pulse word method.

[0002]

2. Description of the Related Art This type of conventional pulsed word (pulsed w
In the ord-line) type semiconductor memory device, the word line selected by the X address indicates the RAS main signal RASB (row address strobe signal, Low active signal) as shown in the timing chart of FIG. A word line (referred to as "sense word") that is added to add "B" and is activated to sense memory cell data at the falling edge of "RAS bar", and an RSTR (restore) signal that is a RAS main signal. It has two functions of a word line (called a "restore word") that is activated to write the data stored in the sense amplifier to the memory cell at the time of rising.

The pulse word method is usually used for devices having multiple banks. The 2-bank configuration will be described below. FIG. 6 shows two banks (L) depending on the RAS signal, the X address when operating the RSTR signal, and the bank signal.
The operation waveforms of the word line and the bit line of the bank and U bank are shown.

Referring to FIG. 6, at the time of 6B, RST
Since the bank signal is the U bank when the R signal rises, word 3 of the U bank is activated as a restore word.

At time 6C, word 4 is activated as a sense word by the designation of the X address at the fall of the RASB signal.

Next, at the time of 6D, since the bank signal is the L bank when the RSTR signal rises, word 1 of the L bank is activated as a restore word. Here, the activated word 1 is the same word line as the activated word line in the sense word at the time of 6A.

The bit line of the L bank (sense amplifier activation timing) is sensed at the time of 6A, and the 6B and 6B are sensed.
Even if the RAS operation of the U bank is executed at the time of C, 6
It is in the activated state until the time point D.

From the time point 6A to the time point 6D, the write operation is also performed on the sense amplifier in the L bank.
The data of the sense amplifier must be written into the memory cell before the sense amplifier is inactivated at the rising edge of the RASB signal between the time point of 6) and the time point of 6E. Therefore, the same word line as the word line activated at the time of 6A is activated again.

Similarly, in the U bank, at the time of 6F, the word 4 activated at the time of 6C is activated as a restore word. Although the U bank is selected at the time of 6B and the L bank is selected at the time of 6D, the bank selection at the rising edge of the RSTR signal is arbitrary in the pulse word system.

The conventional X-address supply method in the pulse-word type device receives the X-address at both the sense word activation time and the restore word activation time.

FIG. 5 shows a configuration example of a conventional memory device of the pulse word system.

Referring to FIG. 5, memory cells of U bank and L bank are arranged above and below the X decoder section as a boundary, and a peripheral circuit section is provided at the center.

In the peripheral circuit section, a circuit which receives an X address and a bank signal input from the outside, performs predecoding, and outputs a predecode signal to the X decoder section (that is, an X address input first stage circuit, a bank signal input first stage Circuit, and an X address predecode circuit), and an RAV circuit for outputting the RAV signal, which is a word line active potential generation signal, to the left and right X decoder sections are provided as main circuits of the X address system. . These circuits are commonly used in both banks in order to reduce the device area.

FIG. 4 is a diagram showing a schematic configuration of a conventional X-address main circuit, focusing on circuit connections.

Referring to FIG. 4, when an 8-bit X address signal is input to X address input initial stage circuit 31, X
The output (node (node) 301) pre-decoded by the address pre-decoding circuit 34 is X in 16 lines.
The signal reaches the decoder circuit 36 and is input to the X decoder circuit 36.

The bank signal is input to the bank signal first stage circuit 32, and the output internal bank signal (node 302) is input to the X decoder circuit 36 and the RAV circuit 35.

The RAV circuit 35 is connected to an X decoder circuit 36, which serves as a reference signal for the potential of the word line.
A circuit for generating a V signal (node 303),
It operates at the timing of the output signal of the RSTR first stage circuit 33 and activates the RAV signal of the selected bank in accordance with the bank signal.

The RAS / RSTR first stage circuit 33 is
An X address precharge signal (node 304) is generated.

X address precharge signal (node 30
4) is a signal for resetting the X address in the X decoder circuit 36, and becomes a low level (active) when the sense word and the restore word line are deactivated, as shown in the timing chart of FIG. , X address is reset.

FIG. 3 shows an example of a circuit configuration of a conventional X decoder section.

Referring to FIG. 3, node 203 is selected for another X decoder circuit by the X address predecode signal (node 301 in FIG. 4) (node 203 is at low level), and node 201 and node 202 are selected. High potential.

Next, when the RAV signal of either the U bank or the L bank is activated, the node 201 or the node 202 is affected by the parasitic capacitance with the RAV signal line (for example, the input terminal (drain terminal of the N-channel MOSFET MN3). ) And the node 201), and is bootstrapped through the power supply voltage V _DD or more (that is, V _DD + V).
Above _T , but V _T rises to the potential of the threshold voltage of MN5), and the potential of the RAV signal is transmitted to the word line as it is.

This technique is generally called self-boot (or bootstrap technique), and the nodes 201 and 202 are both called "self-boot nodes".

The outline of the conventional pulse word type memory device described above is summarized below.

(1) Conventionally, all the X-address related circuits are shared by both banks for reasons such as device area reduction.

(2) The specifications of the pulse word system are RST
Bank selection at the rising edge of the R signal is arbitrary.

(3) Although the restore word after the sense word is the same word in each bank,
In the conventional example, because of the reasons (1) and (2) above, all the X addresses are reset after the sense word is activated. Therefore, when the restore word is activated, the X address is input again and predecoding of the X address and the self-boot node are performed. A high potential charge time is required.

(4) The selection means for activating the word line is X
It is performed through the self-boot node selected by the address and bank signals.

[0029]

In the conventional pulse word type memory device described above, all the X address circuits are shared by both banks, and the bank selection at the rising of the RSTR is arbitrary. Since the X address is received again when the restore word is activated and the word line selection operation is performed, the write time to the memory cell cannot be shortened even though the restore word immediately after the sense word is the same word in each bank. .

Therefore, it is an object of the present invention to provide a semiconductor memory device in which the operation time at the time of activating the restore word is shortened and the increase in the device area due to this is suppressed as much as possible.

[0031]

In order to achieve the above object, the present invention has a plurality of banks and ends a sense operation of a word line activated to sense data of a memory cell (referred to as "sense word"). After that, it is deactivated once, and when the sense amplifier is deactivated, the word line (called “restore word”, but the word line at the same address as the immediately preceding sense word in each bank) is activated and the sense amplifier data is stored in memory. In a semiconductor memory device that performs an operation of writing to a cell, a holding circuit is provided at an internal self-boot node, and holds an X address for each bank from the activation of the sense word to the activation of the restore word. A semiconductor memory device is provided.

The principle of the present invention will be described below.

That is, in order to solve the above-mentioned problems of the prior art, X of the active word line at the time of activation of the sense word is X.
It is necessary to hold the address in bank units, but depending on where it is held in the circuit, the write time when activating the restore word can hardly be shortened or the device area increases. .

In order to reduce the write time when the restore word is activated most effectively, the self-boot node High of the X decoder circuit selected when the sense word is activated is High.
This is to hold the potential (high potential) until the restore word is activated. This is because the operation of charging the selected self-boot node, which is one of the operations that greatly affects the word line activation operation time, is unnecessary.

By the way, as a method of holding the High potential of the self-boot node, when the holding circuit is provided in the peripheral circuit unit to hold the High potential of the self-boot node, the X decoder circuit unit has the above-mentioned conventional example. 5 has the same configuration as that of the X address predecode signal output from the peripheral circuit section to the X decoder section (wiring 402 in FIG. 5, FIG.
16 signals are required for each bank, and this leads to an increase in device area especially in a device having a multi-bank configuration.

On the other hand, when the holding circuit is provided at the self-boot node to hold the High potential, the area of the X decoder circuit is slightly increased as compared with the conventional example, but the holding circuit is provided in the peripheral circuit section. The effect of increasing the area is extremely small as compared with the case of including.

The present invention was made based on the above findings, and a holding circuit is provided at the self-boot node of the X decoder to hold the X address of the sense word in each bank until the restore word is activated. .

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an X decoder circuit according to an embodiment of the present invention. In addition, the schematic configuration of the device of the pulse word type memory device and the connection outline of the main X address system circuit according to the present embodiment are basically as follows.
It is assumed that the configurations shown in FIGS. 5 and 4 referred to in the description of the conventional example are respectively followed.

Referring to FIG. 1, in the X decoder circuit according to the present embodiment, the source is connected to the power supply, and the X precharge address signal which is a signal for precharge control (active at Low level) is input to the gate. P-channel type MOS transistor MP1 and a plurality of N-channels connected in series between the drain of the transistor MP1 and the ground, and each of which inputs an X address predecode signal output from an X address predecode circuit (not shown) into its gate. Type MOS transistor, a drain terminal of the transistor MP1, and inverters INV1 and INV2
N-channel MOS transistor MN1 (pass transistor) which is inserted between the flip-flop and the U-bank signal (internal signal) at the gate, the output terminal of the inverter INV1 and the N-channel MOS transistor M.
An N-channel type MOS transistor MN1 which is inserted between the gate of N5 and whose gate is connected to a power source,
The output terminal of the transistor MN1 (the connection point with the input / output terminal of the first flip-flop) is connected to the gate of the N-channel MOS transistor MN6, and the drain terminal thereof is RAV.
A transistor MN5 to which a signal (U bank) is applied,
The word line of the U bank is output from the connection point with the transistor MN6 whose source is grounded. In addition, the drain terminal of the MOS transistor MP1 and the inverter INV
3, an N-channel type MOS transistor MN2 (pass transistor) which is inserted between the second flip-flop composed of INV4 and whose gate receives an L bank signal (internal signal), an output terminal of the inverter INV3 and an N channel. Type MOS transistor MN7 and an N-channel type MOS transistor MN4 (pass transistor) whose gate is connected to a power source, the output end of the transistor MN2 (input / output end of the second flip-flop). Connection point) is an N-channel MOS transistor MN
RAV signal (L
The word line of the L bank is output from the connection point of the transistor MN7 to which the bank is applied and the transistor MN8 whose source is grounded.

In this embodiment, as in the conventional X decoder section shown in FIG. 3, the X address signal is shared by both banks, and as shown in FIG. When all the decoded signals are at the high potential, the node 103 is selected (the node 103 is at the low level), and the internal bank signal (U bank signal, L bank signal)
As a result, one of the node 104 and the node 105 having the holding circuit becomes High potential, and the self-boot node 10
1 or one of the self-boot nodes 102 is High
It becomes an electric potential.

As for the internal bank signal, as shown in the timing chart of FIG. 2, when the RSTR signal becomes high, one of the internal bank signals becomes high due to the external bank signal, and the RSTR signal becomes high. Becomes Low (when the sense word becomes inactive), the internal bank signal also becomes Low.

In the conventional example, as shown in FIG. 6, the X address precharge signal is low when the sense word is inactive and the restore word is inactive.
However, in the present embodiment, as shown in the timing chart of FIG. 2, when the restore word is inactivated (for example, when the L bank signal is at the high level, the restore word of the word 1 is not activated). Reset the self-boot node only when activated (see between 5D and 5E). The X address after activation of the sense word is held at the self-boot node, and the X address is reset only when switching from the restore word to the sense word.

In the non-selected bank when the RSTR signal becomes High, the internal sense signal remains at the Low level, so that the self boot node is not reset and the X address of the sense word is held. to continue.

In the above embodiment shown in FIG. 1, the X address predecode signal from the X address predecode circuit 34 shown in FIG. 4 is input to the X decoder for simplicity. Based on a predetermined bit of the X address signal input from the outside, for example, the least significant bit and the next bits X0 and X1 (the X address predecode circuit 34 receives the external X address signal X2 and later), the RAV circuit 35 A configuration including an RAi circuit that outputs an input RAV signal that is a word line active potential generation signal to an output stage transistor (for example, MN5 in FIG. 1) of an X decoder via any one of four selected lines Can be similarly applied to. in this case,
The RAi circuit can have the same configuration as the X decoder having the holding circuit described in the above embodiment.

[0046]

As described above, according to the present invention,
By holding the X address information for sense word activation at the self-boot node until the restore word is activated, the operation time until activation of the word line is greatly affected.
The charge time of the self-boot node is unnecessary, and therefore the restore word activation time can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an X decoder circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 3 is a diagram showing a configuration example of a conventional X decoder circuit diagram.

FIG. 4 is a diagram showing a connection outline of a main X address system circuit of a pulse word system.

FIG. 5 is a diagram showing a schematic configuration of a pulse word type device.

FIG. 6 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 31 X address signal input first stage circuit 32 Bank signal input first stage circuit 33 RAS / RSTR first stage circuit 34 X address predecode circuit 35 RAV circuit 36 X decoder circuit 101 to 105 nodes

Claims (4)

[Claims] 1. A word line having a plurality of banks and activated for sensing data in a memory cell (referred to as "sense word") is once inactivated after the end of sensing,
When the sense amplifier is deactivated, the word line (called "restore word", but the word line at the same address as the immediately preceding sense word in each bank) is activated again to write the data of the sense amplifier to the memory cell. In a semiconductor memory device, a holding circuit is provided at an internal self-boot node, and holds an X address for each bank from the activation of the sense word to the activation of the restore word. . 2. The semiconductor memory device according to claim 1, wherein an X address other than the bank signal is shared by each of the plurality of banks. 3. An X decoder which inputs and decodes an X address predecode signal and activates a selected word line of a corresponding bank based on an internal bank signal, has a predetermined high level when the word line is in its activated state. A semiconductor memory device comprising a flip-flop for storing the potential of a self-boot node of an output stage circuit set to a potential. 4. A semiconductor memory device according to claim 3, wherein said self-boot node potential of a corresponding bank is reset by said internal bank signal only when a restore word is inactivated.