JPH0989995A - Integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the increase in number of testing terminals and perform three kinds or more of tests by controlling three kinds or more of testing circuits by three kinds or more of control signals according to input voltage. SOLUTION: When a prescribed voltage is added to a testing input terminal 4 to make a signal (b) of output control signals (a)-(d) of a control circuit 2 HIGH, a selector SL1 pulse-inputs the clock signal from an input terminal 5 and transmits it to a counter CN2, and the counter CN2 is stopped when the count value becomes 15. With respect to the signals (c)-(d), the same procedure is successively performed. The signal (a) is then made HIGH, the lock signal 16 pulse is inputted from the terminal 5 to a counter CN1 through a gate GT1 to reverse its output from HIGH to LOW by the 16th clock signal. The LOW output is inputted to the counter CN2 to reverse its output to LOW. The outputs of counters CN3-CN4 are similarly reversed to LOW. The above description shows the case where a circuit 1 to be tested is entirely normal, and the quality of the circuit 1 can be judged by monitoring an output terminal 6.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD This application relates to integrated circuit devices.

[0002]

2. Description of the Related Art When performing, for example, two types of tests on a circuit integrated in an integrated circuit device, binary control is performed from outside the integrated circuit device to a test terminal provided in the integrated circuit device. A signal is input and different tests are executed according to the high or low level of the control signal.

[0003]

However, when performing three or more types of tests, a plurality of test terminals must be provided, and the number of terminals of the integrated circuit device increases accordingly. there were.

An object of the present invention is to provide an integrated circuit device capable of suppressing an increase in the number of test terminals even when performing three or more types of tests.

[0005]

An integrated circuit device according to the present application includes a circuit under test, a control circuit for generating three or more kinds of control signals in accordance with an input voltage, and a circuit under test in response to the control signal. And a test circuit for performing three or more types of tests.

[0006]

1 is a block diagram showing an embodiment of an integrated circuit device according to the present invention.

In order to simplify the description, a case where a 16-bit binary counter is assumed as an integrated circuit and a test of this 16-bit binary counter is performed will be described.

The circuit under test 1 constitutes a 16-bit binary counter, and is a 4-bit binary counter CN1.
~ CN4. In actual operation, a 16-bit binary counter can be obtained by serially connecting these 4-bit binary counters CN1 to CN4.
The clock input from the input terminal 5 is divided into 2 ¹⁶ and output to the output terminal 6.

The control circuit 2 generates four types of control signals a to d according to the input voltage value input to the test terminal 4. FIG. 2 is a diagram showing a detailed configuration of the control circuit 2. The resistors R1 to R4 have the same resistance value, and are connected in series between the positive power supply VDD and the negative power supply VSS (usually ground) to divide the power supply voltage. The comparators CP1 to CP3 include resistors R1 to R4.
Each voltage value divided by is compared with the input voltage value input to the test terminal 4. Gate G1
G4 generates the control signals a to d according to the output states of the comparators CP1 to CP3. That is, in the control circuit 2, the input voltage value input to the test terminal 4 is compared with each voltage value divided by the resistors R1 to R4, and only one of the control signals a to d is in the high state. Becomes

The test circuit 3 performs four types of tests on the circuit under test 1 in response to the control signals a to d, and is composed of a gate GT1 and selectors SL1 to SL3. In the selector SL1, the control signal b
Is high, the clock signal from the input terminal 5 is selected, and when the control signal b is low, the output signal from the counter CN1 is selected. In the selector SL2, the control signal c
Is high, the clock signal from the input terminal 5 is selected, and when the control signal c is low, the output signal from the counter CN2 is selected. In the selector SL3, the control signal d
When is high, the clock signal from the input terminal 5 is selected, and when the control signal d is low, the output signal from the counter CN3 is selected.

Next, a test operation in the integrated circuit device shown in FIGS. 1 and 2 will be described.

First, all the binary counters CN1 to CN4 are reset (count value 0). After releasing the reset state, a predetermined voltage is applied to the test input terminal 4 to set the control signal b to the high state, and the selector SL1 is selected. Then, input the clock signal from the input terminal 5 to 15
Input pulse. This clock signal is input to the counter CN2 through the selector SL1 and the counter CN2 stops when the count value of the counter CN2 becomes “15”. Next, the voltage of the test terminal 4 is changed to bring the control signal c into the high state, and the selector SL2 is selected.
Then, 15 pulses of the clock signal are input from the input terminal 5, and the count value of the counter CN2 is set to "15".
Next, the voltage of the test terminal 4 is further changed to bring the control signal d into the high state, and the selector SL3 is selected. Then, 15 pulses of the clock signal are input from the input terminal 5, and the count value of the counter CN4 is set to "15". Next, the voltage of the test terminal 4 is further changed to bring the control signal a into the high state. Then, 16 pulses of the clock signal are input from the input terminal 5. This clock signal is input to the counter CN1 through the gate GT1 and the output of the counter CN1 is inverted from high to low by the 16th clock signal. The output of the counter CN1 is input to the counter CN2 through the selector SL1 and the counter C2
The output of N2 is inverted from high to low. Similarly, the output of the counter CN3 is inverted from high to low, and the output of the counter CN4 is inverted from high to low.

If all the counters CN1 to CN4 are normal, the sequence is performed as described above, and the counter C
The output of the counter CN4 is first inverted from high to low by the 16th clock signal to N1. On the contrary, if there is an abnormality in the counters CN1 to CN4, the sequence as described above is not performed, and the inversion operation of the counter CN4 based on the 16th clock signal to the counter CN1 is not performed. Since the output of the counter CN4 is connected to the output terminal 6, if the output of the counter CN4 is monitored using this output terminal 6, it is possible to determine the quality of the counters CN1 to CN4, that is, the circuit under test.

Here, the total number of clock pulses input from the input terminal 5 in the test sequence is "15 + 15 + 15 + 16", that is, 61 pulses. If the counters CN1 to CN4 are directly connected in serial to form a 2 ¹⁶ or 65536-ary counter and a test is performed, the total number of clocks required for the test is 65536 pulses. Therefore, by performing the test as described above, the total number of clocks required for the test can be significantly reduced, and the test time can be significantly reduced.

In the actual operation, if the test terminal 4 is fixed to VSS and the control signal a is kept high, the 4-bit binary counters CN1 to CN4 are serially connected through the selectors SL1 to SL3. And a 16-bit binary counter is constructed. As a result, the clock signal input to the input terminal 5 is divided into 2 ¹⁶ and output terminal 6
Output from

[0016]

According to the invention of the present application, a control circuit for generating three or more types of control signals according to an input voltage and a test circuit for performing three or more types of tests on a circuit under test according to the control signals are provided. Since it is provided, it is possible to suppress an increase in the number of test terminals even when performing three or more types of tests.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an integrated circuit device according to the present application.

FIG. 2 is a diagram showing in detail a part of the integrated circuit device shown in FIG.

[Explanation of symbols]

 1 ... Tested circuit 2 ... Control circuit 3 ... Test circuit a to d ... Control signal

Claims (1)

[Claims] 1. A circuit under test, a control circuit for generating three or more types of control signals according to an input voltage, and a test for performing three or more types of tests on the circuit under test according to the control signals. An integrated circuit device having a circuit.