JPH08274614A - Semiconductor integrated circuit and its test method - Google Patents

Abstract

PURPOSE: To reduce the measurement errors of output currents of output buffers that are caused by the contact resistance of a metallic probe brought into contact to the electrode of a semiconductor integrated circuit in every measurement state. CONSTITUTION: The output buffers B1 to Bn have the input and output terminals connected between an input terminal 2 and an output terminal 3 and also have the test control terminals T1 to Tn respectively. The outputs of buffers B1 to Bn have high impedances due to the test signals which are supplied to the terminals T1 to Tn. When the electrical characteristic is measured by an 1C tester, a normal drive operation is given only one of buffers Bl to Bn with other buffers set at high impedances respectively. Then the output current of a single output buffer is first measured and then other buffers also undergo the measurement of their output currents in the same way. The sum total of these measured current value is defined as the output current of a high-drive output buffer 1, so that the output current can be reduced in every measurement. Then the voltage drop error due to the contact resistance of a metallic probe caused in a measurement state can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method for testing the same, and more particularly to a semiconductor integrated circuit and a method for testing the semiconductor integrated circuit in which a current error when measuring an output current of an output buffer having a high driving capability is improved.

[0002]

2. Description of the Related Art In recent years, the number of input / output terminals has increased along with the high integration and multifunction of semiconductor integrated circuits, and the input / output buffers connected to these terminals also have various functions. Has been requested. Therefore, for example, when testing a semiconductor integrated circuit, it is necessary to confirm the internal circuit function in a state where the inside of the semiconductor integrated circuit is shifted to the test mode, and also to confirm the electrical characteristics of the input / output buffer that interfaces with the external circuit of the semiconductor integrated circuit. Therefore, the method for measuring the electrical characteristics of these input / output buffers is devised in accordance with their respective functions.

FIG. 4 is a block diagram showing an example of a conventional low-driving output buffer of this type of input / output buffer.
Referring to (a), the output buffer B10 has an input end 21 and an output end 22, and outputs the signal supplied to the input end 21 from the output end 22 with the same polarity. The drive capability of the output buffer B10 is generally designed so that an output current capable of driving the input buffer of the semiconductor device connected to the outside can be taken out.

Therefore, as a demand when the input circuit of the semiconductor device connected to the outside is configured to require a particularly large current, a transistor forming an output so that a large output current can be drawn from this output buffer. Design a large size.

On the other hand, in a semiconductor integrated circuit having a gate array structure, basic gates (for example, NAND, NOR, etc.) are arranged in a row on a chip in advance, and all logics are limited to a certain limited type. The design is advanced by expressing it with a basic gate, but at this time, the input and output buffers are also arranged in advance in the peripheral portion of the chip.

However, arranging a large number of output buffers having a large output current in the limited peripheral region requires a wasteful area from the viewpoint of layout efficiency, and therefore, except for a special case. An output buffer with a relatively small output current is arranged in advance.

Generally, these output buffers are diverted to output buffers requiring a large current output as needed. Referring to FIG. 4B, which is a block diagram showing an example of a high drive output buffer using a conventional low drive output buffer in that case, the output buffers B11 to B1n having a relatively small output current are desired. Multiple units are connected in parallel according to the output current.

That is, the output buffer B is connected to the input terminal 23.
Input terminals 11 to B1n are commonly connected, and respective output terminals are commonly connected to the output terminal 24.

Here, when a signal is supplied to the input terminal 23, it is input to the output buffers B11 to B1n, respectively, and the total output of the respective outputs is output to the output terminal 24. Therefore, even if a large output current is taken out, Since only the divided currents flow into the output buffers B11 to B1n, the output buffers having a relatively small drive capacity need to be arranged.

[0010]

The output buffer mounted on the semiconductor integrated circuit in the conventional gate array system described above is used as a test device, for example, an IC tester, when an electrical characteristic test of the semiconductor integrated circuit is carried out. He is electrically connected to the test semiconductor integrated circuit.

The first step of this electrical characteristic test is carried out in the state where the semiconductor integrated circuit has the chips before division formed on the semiconductor wafer. Since the connection between the IC tester and the semiconductor integrated circuit is a temporary connection only during the test because it is still in the form of a wafer, the metal probe of the prober attached to the test head of the IC tester is
This is a state in which the output terminal of the output buffer arranged in the peripheral portion of the chip is in contact with the external terminal electrode to be connected.

The connection for contacting the metal probe is 1 to 5
Contact resistance of about Ω occurs. When a large current flows through the output buffer due to this contact resistance, this large current flows from the output buffer through the metal probe to the common ground potential of the IC tester and the chip.

Therefore, there is a drawback that a large voltage drop occurs due to the contact resistance of the metal probe, and this voltage drop amount causes a measurement error.

The object of the present invention has been made in view of the above-mentioned drawbacks, and is high due to the contact resistance of a metal probe contacting an electrode of a semiconductor integrated circuit at the time of measuring an electrical characteristic by an IC tester. An object of the present invention is to provide a semiconductor integrated circuit in which the measurement error of the capacity output buffer is reduced and a test method thereof.

[0015]

The semiconductor integrated circuit of the present invention is characterized in that it has an output buffer group for supplying a signal output from an internal circuit to the outside through an output terminal, and these buffer groups have drivability. In a semiconductor integrated circuit consisting of a low drive buffer group having a small number and a high drive buffer group in which a plurality of the low drive buffers are combined to increase the drive capability,
At least a part of the low drive output buffer group is provided with a test control terminal, and comprises a ternary output buffer which is in a high impedance output state in response to an active state of a predetermined test signal supplied to the terminal. A plurality of input terminals of the output buffer are commonly connected to each other and their output terminals are commonly connected to each other to form the high drive output buffer.

The semiconductor integrated circuit testing method of the present invention is characterized in that the output buffer group for supplying the signal output from the internal circuit to the outside through the output terminal has a low drive capacity and a low drive buffer group. A method for testing a semiconductor integrated circuit, which comprises a high-driving buffer group having a combination of a plurality of high-driving buffers, and the output current of the high-driving output buffer is measured by a test device inserted between the output terminal and the ground potential. In at least a part of the low drive output buffer group, a test control terminal is provided, which comprises a ternary output buffer that is in a high impedance output state in response to an active state of a test signal supplied to the terminal. The output buffer is a ternary output buffer having a plurality of input terminals commonly connected to each other and each output terminal commonly connected to each other. Made of a high drive output buffer Mounting control functions, output current measurement of the high drive output buffer,
The test signal is made active and supplied to one of the three-value output buffer groups forming the high drive output buffer, and the test signal is made inactive in the remaining three-value output buffer groups. Measuring the output current of the one ternary output buffer that is supplied and flows out of the output terminal;
This measurement operation is sequentially performed on each of the remaining three-value output buffers to measure each output current.

[0017]

First, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1A is a block diagram showing the main part of an output buffer and its measuring circuit according to one embodiment.
(B) is a circuit diagram showing an example of a configuration circuit of an output buffer.

Referring to FIG. 1, the high drive output buffer of the semiconductor integrated circuit according to the present embodiment comprises a plurality of low drive output buffers B1 to Bn, and these low drive output buffers B1 to Bn are test control terminals. A low drivability buffer which has T1 to Tn and becomes a high impedance output state or one of a logic level high level and low level in response to an active state or a non-active state of a predetermined test signal supplied to this terminal ( Hereinafter, referred to as tri-state output buffers) B1 to Bn, and a plurality of tri-state output buffers have their input terminals commonly connected to each other and their output terminals commonly connected to each other to form a high drive output buffer 1. Has been done.

The three-state output buffers B1 to Bn have a known circuit configuration. For example, a P-channel type MOS transistor Q1 and an N-channel type MOS transistor Q2 are connected in series between a power supply potential and a ground potential to form a P-channel type MOS transistor. The gate electrode of the transistor Q1 has a 2-input NA
The ND gate element 11 has a 2-input NAND gate element 12 at the gate electrode of the N-channel MOS transistor Q1.
Are connected to each other, and these two gate elements 11 and 1 are connected.
Each one input terminal of 2 is commonly connected to the input terminal 2, and NA
A test signal line is connected to the other input terminal of the ND gate element 11 via an inverter 13, and the NOR gate element 12
The other input end of is connected to the test signal line directly.

High drive output buffer 1 having the above configuration
In the normal high drive operation state of the test control terminals T1 to T
n is set to the low level, and three-valued state output buffers B1 to Bn
Simultaneously output the input signals to the output terminal 3. As the output current at this time, the total value of the output currents of the respective buffers is taken out.

Since each of the test control terminals T1 to Tn is independently controlled, a plurality of three-state output buffers B1 to Bn forming one high drive output buffer 1 are provided.
Among them, when the test control terminal of any three-state output buffer is set to the high level, only the three-state output buffer can be set to the high impedance state, and the output signal can be output only from the remaining three-state output buffer.

On the contrary, only the test control terminal of one 3-state output buffer is set to the low level, only the 3-state output buffer is set to the input signal output state, and the remaining 3-state output buffers are set to the high impedance state. You can

Referring to FIG. 3, which is a circuit connection diagram for measuring electrical characteristics, which will be described later, these test control terminals T are shown.
1 to Tn are selected by connecting a plurality of output terminals of the decoder 4 in which a test signal has a plurality of bits to the test control terminals T1 to Tn of the plurality of three-state output huffers B1 to Bn, respectively. Depending on the combination of the high-level and low-level states of the test signal, any one of 3
The status output buffer can be selectively activated.

Although the decoder 4 is prepared inside this semiconductor integrated circuit, if the external terminal has a margin, the decoder 4 is not necessary and the test control terminals T1 to Tn may be directly connected to the external terminal.

Referring to FIG. 2 which shows the timing chart for explaining the selection operation described above, in order to facilitate understanding in this figure, the states output to the output terminals of the three-state output buffers B1 to Bn are different from each other. Although shown, in reality, these terminals are commonly connected to each other, so that they become one output.

Since the potential of the test control terminal T1 is low level and the test control terminals T2 to Tn are high level in the period t1, the corresponding three-state output buffer B1 outputs the input signal with low driving and the three-state output buffers B2 to B2. Bn is in a high impedance state.

Next, during the period t2, the potential of the test control terminal T2 is low level, and the test control terminals T1, T3 to Tn are high level, so that the corresponding tri-state output buffer B2.
Outputs the input signal at low drive, and the 3-state output buffer B
1, B3 to Bn are in a high impedance state.

Next, during the period tn, the test control terminal T2 is at low level and the test control terminals T1 to T (n-1) are at high level.
B (n-1) outputs the input signal with low driving, and only the 3-state output buffer n is in the high impedance state.

After the subsequent period tn + 1, the test state ends because the potentials of the test control terminals T1 to Tn are all at the low level, and the three-state output buffers B1 to Bn serve as high drive output buffers and output the input signals with low drive. To do.

The method of testing the output current of the semiconductor integrated circuit having the high drive output buffer 1 is shown in FIGS.
Referring to FIG. 3 in addition to (b) and FIG. 2, a decoder 4 for selecting a test signal is connected to the test control terminals T1 to Tn of the high drive output buffer 1, and an output terminal 3 for measuring an output current. The IC tester 5 is connected.

In the above-mentioned connected state, the contact resistance 7 caused by the metal probe 6 of the IC tester 5 contacting the output terminal 3 (external terminal electrode) is generated between the output terminal 3 and the IC tester 5.

The test signals supplied to the decoder 4 are set to a predetermined combination, the test control terminal T1 of the high drive output buffer 1 is set to low level, and the other test control terminal T2 is set.
The high level is selected and supplied to Tn.

In this state, as described above, the ternary state output buffer B1 becomes active and outputs the input signal with low driving. The other ternary state output buffers B2 to Bn are in a high impedance state, and only the output current of the ternary state output buffer B1 flows to the IC tester 5 via the contact resistance 7 of the metal probe 6, so that the current value is measured. To be done.

Next, the test signals are changed to a predetermined combination, and a low level is selected and supplied to the test control terminal T2 of the high drive output buffer 1 and high levels are supplied to the other test control terminals T1 and T3 to Tn. . The ternary state output buffer B1 becomes active and outputs the input signal with low driving,
Only the output current is I through the contact resistance 7 of the metal probe 6.
It flows into the C tester 5 and its current value is measured.

The same operation is repeatedly executed until the output current output from the ternary state output buffer Bn is measured.

The sum of the output current values of the three-state output buffers B1 to Bn measured as described above is obtained as the output current value of the high drive output buffer 1 in the normal operation state.

As described above, by measuring the output current by dividing it into n times, the current value for each time is 1 /
n, and the voltage drop due to the contact resistance 7 is also 1 / n.
Therefore, the measurement error due to the voltage drop caused by the metal probe 6 in the electrical characteristic test is reduced.

[0039]

As described above, the semiconductor integrated circuit and the test method thereof according to the present invention include a plurality of low drive capacity buffers, each of which has a test control terminal. A three-state output buffer having a low driving capability that becomes a high-impedance output state or one of a logic level high level and a low level in response to an active state or a non-active state of a predetermined test signal supplied to the three-state output buffer. Output buffer Using a high drive output buffer composed of a plurality of input terminals commonly connected to each other and each output terminal commonly connected to each other,
One of the three-value output buffer groups is supplied with the test signal in the active state, and the remaining three-value output buffer groups are supplied with the test signal in the inactive state and flowing out from the output terminal. Since the output current of the output buffer is measured and this measurement operation is sequentially executed for each of the remaining three-value output buffers, the output current of each is measured.
The sum of these individual output current values becomes the output current as a whole. Therefore, in the measurement of the output current per time,
Since the current value can be made sufficiently small, there is an effect that the measurement error due to the voltage drop caused by the metal probe between the output buffer and the test apparatus can be made small.

[Brief description of drawings]

FIG. 1A is a block diagram showing a main part of an output buffer and its measurement circuit according to an embodiment of the present invention. (B) It is a circuit diagram which shows an example of the structural circuit of an output buffer.

FIG. 2 is a timing chart for explaining a test control terminal selection operation.

FIG. 3 is a circuit connection diagram when measuring the electrical characteristics of the embodiment.

FIG. 4A is a block diagram of a conventional low drive output buffer. (B) A block diagram of a high drive output buffer using a conventional low drive output buffer.

[Explanation of symbols]

 1 High drive output buffer 2,21,23 Input terminal 3,22,24 Output terminal 4 Decoder 5 IC tester 6 Metal probe 7 Contact resistance 11 NAND gate element 12 NOR gate element 13 Inverter B1-Bn, B10-B1n Low drive Output buffer T1 to Tn test control terminal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H03K 19/0175

Claims (2)

[Claims] 1. An output buffer group for supplying a signal output from an internal circuit to the outside through an output terminal, and these buffer groups have a low drive capacity and a plurality of low drive buffers. In a semiconductor integrated circuit including a high drive buffer group having a combination of increased drive capability, at least a part of the low drive output buffer group is provided with a test control terminal, and a predetermined test signal supplied to this terminal is activated. In response, the ternary output buffer is brought into a high impedance output state. The ternary output buffer has a plurality of input terminals commonly connected to each other and each output terminal commonly connected to each other to form the high drive output buffer. A semiconductor integrated circuit characterized by being configured. 2. A low drive buffer group in which an output buffer group for supplying a signal output from an internal circuit to the outside through an output terminal has a small drive capacity, and a plurality of low drive buffers are combined to enhance a high drive capacity. In a method of testing a semiconductor integrated circuit, the output current of the high drive output buffer is measured by a test device inserted between the output terminal and a ground potential, and at least one of the low drive output buffer group is provided. The unit is provided with a test control terminal, and comprises a ternary output buffer that is in a high impedance output state in response to an active state of a test signal supplied to the terminal. The high drive output buffer is a plurality of ternary output buffers. It consists of a high drive output buffer with test control function whose input terminals are commonly connected to each other and each output terminal is commonly connected to each other. The measurement of the output current of the high drive output buffer is performed by supplying the test signal to one of the ternary output buffers constituting the high drive output buffer in an active state, and the remaining ternary output buffers. The test signal is supplied to the group in an inactive state, and the output current of the one ternary output buffer flowing from the output terminal is measured, and this measurement operation is sequentially performed on each of the remaining ternary output buffers. A method for testing a semiconductor integrated circuit, which is executed to measure each of the output currents.