JPH098633A - Power supply circuit for mixed mounting of high-speed logic circuit and analog circuit - Google Patents

Abstract

PURPOSE: To prevent noise from being generated by providing a VCC layer A with a sufficiently smaller form dimension in comparison with the wavelength of a power supply current change in a CMOS IC and providing an LPF at a path between VCC layers A and B and a GND layer. CONSTITUTION: A VCC layer A1 is provided between a printed circuit board 7 of a VCC layer B2 on the side, where a CMOS IC3 is mounted, and a GND layer 4. The form dimension of the layer A1 is made sufficiently smaller in comparison with the wavelength of the power supply current change in the CMOS IC3. Since the structure of a power supply circuit equipped with the VCC layer A1 is provided, no potential difference is generated inside the layer A1. Besides, since an LPF5 is provided, there is a voltage change only in the layer A1 and the GND layer 4 is not affected. Further, no voltage change is propagated to the VCC layer B2 by the operation of the LPF5 as well. Thus, since the structure of the power supply circuit for high-speed logic circuit is provided, power supply with a little noise is enabled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit formed on a printed wiring board which can reduce noise by preventing the occurrence of standing waves due to changes in power supply current.

[0002]

2. Description of the Related Art In the prior art, an ECL IC with high power consumption was used for a high speed logic circuit.
Recently, CMOS ICs, which consume less power, have become faster, so that CMOS ICs have been used in many high-speed logic circuits and have replaced ECL ICs.

However, in the ECL IC, the power supply current is constant, whereas in the CMOS IC, the power supply current fluctuates greatly and noise is generated in the power supply.

Therefore, in the printed wiring board on which the analog circuit portion and the digital circuit portion are mixedly mounted, noise from the power supply circuit spills into the analog circuit portion, which causes a problem of adverse effect. .

Next, the mechanism of power supply noise that causes the problem and the situation in which the noise propagates will be described with reference to FIG. FIG. 2- (A) is a conceptual diagram showing the configuration of the high-speed logic circuit and the power supply circuit on the printed wiring board 7. The equivalent circuit is shown in FIG. Further, FIG. 2- (D) shows a change state of the power supply current of the CMOS IC3. That is, as shown in (D), CM
The OSIC3 is a VCC layer 13 which is a power supply layer at the time of level inversion.
Through current flows from the ground layer to the GND layer 4. Therefore, if the number of circuits that are inverted at the same time increases, a power supply current i14 having an excessive characteristic as shown in FIG.

Assuming that the VCC layer 13 and the GND layer 4, which are power supply layers, are made of copper foil layers of the printed wiring board 7, as shown in FIG. Such a voltage drop occurs, and this voltage propagates in the copper foil layer and is reflected 15 at the end of the printed wiring board 7 to generate a standing wave 1.
6 will occur. When the GND layer 4 of the analog circuit and the digital circuit are made common, the standing wave 1 generated in the GND layer 4
6 becomes a noise source of the analog circuit and causes a problem. Further, as shown in FIG. 2- (B), although the bypass capacitor 6 is used, the high frequency noise cannot be completely removed by the action of the L component 9 inside the capacitor.

Therefore, in the prior art, in order to prevent the adverse effect of noise on the circuit on the printed wiring board 7 on which the analog circuit and the digital circuit parts are mounted together,
Separate the power supply of the analog circuit part and the digital circuit part,
Moreover, in the mutual signal connection, a method of separating by using an optical coupling element such as a photocoupler, a pulse transformer or a differential driver / receiver has been adopted.

Therefore, in the prior art, when the number of signal connections to each other is extremely large, it is necessary to form a circuit by the above-mentioned coupling elements or the like corresponding to the number of signal connections, and therefore costs such as parts cost and assembly cost. In addition, there is a problem that a space for disposing the coupling element and the like is required.

[0009]

The problem to be solved by the present invention is necessary because a CMOS IC is used in a high-speed logic circuit on a printed wiring board on which an analog circuit section and a digital circuit section are mixedly mounted. This is to prevent the generation of noise caused by a standing wave caused by a large fluctuation in the power supply current. And
By preventing the generation of noise, it is possible to obtain a power supply circuit with a configuration in which a high-speed logic circuit on a printed wiring board on which an analog circuit unit and a digital circuit unit are mixed does not adversely affect the analog circuit unit. .

[0010]

According to the present invention, in the structure of the power supply to be supplied to the high-speed logic circuit section on the printed wiring board on which the analog circuit and the digital circuit are mixed, the power supply on the printed wiring board is provided. Two systems, in which the VCC layer, which is a layer, is a VCC layer A and a VCC layer B are provided.

That is, since the VCC layer A is provided so as to have a physical shape which is sufficiently smaller than the wavelength of the change in the power supply current of the CMOS IC, no potential difference occurs in the VCC layer A, Also, by providing a low-pass filter, the voltage change is limited to within the VCC layer A.
The power supply circuit has a structure that does not affect the ND layer and that the voltage change does not propagate to the VCC layer B due to the action of the bypass capacitor.

[0012]

(1) In the case of the present invention, the setting of the respective values of the low-pass filter and the bypass capacitor should be selected so as not to affect the operation of the high-speed logic circuit. (2) The low-pass filter of the present invention is composed of the L component and the C component, and the L component is the VCC layer A and the VCC layer B.
Is provided by a wiring system path forming a through-hole portion for electrically connecting to and. In addition, there is a small value not only for the C component but also for the L component in the capacitor that gives the C component. Similarly, the bypass capacitor also has a small L component.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1- (A) is a conceptual diagram showing the structure of a high speed logic circuit and a power supply circuit formed on a printed wiring board 7 according to the present invention. FIG. 1- (B) shows an electrically equivalent circuit of the structure of the power supply circuit according to the present invention. Further, in FIG. 1- (C), by providing the VCC layer A1 of the present invention, the voltage drop caused by the change in the power supply current of the CMOS IC3 is limited to the inside of the VCC layer A1 by the low-pass filter 5, and the FIG. 3 is a conceptual diagram for explaining the principle of not affecting.

(1) The concept of the structure of the power supply circuit for the high speed logic circuit according to the present invention is shown in FIG. 1- (A). As shown in the drawing, the VCC layers B2 and G, which are power supply layers on the printed wiring board 7 in the structure according to the related art, are shown.
In addition to the ND layer 4, the VCC layer A1 is additionally provided. That is, the VCC on which the CMOS IC3 is mounted
Between the printed wiring board 7 on the layer B2 side and the GND layer 4, VC
The C layer A1 was provided. The configuration of the VCC layer A1 is compared with the wavelength of the power supply current change of the CMOS IC3 as shown in the figure,
The physical dimensions were sufficiently small.

(2) With the structure of the power supply circuit provided with the VCC layer A1 described above, as shown in FIG. 1- (C), no potential difference occurs in the VCC layer A1 and the low-pass filter 5 is provided. By providing, the voltage change is only in the VCC layer A1 and does not affect the GND layer 4. Further VCC layer B
The voltage change is not propagated to 2 by the action of the low-pass filter 5. Therefore, the structure of the power supply circuit for the high speed logic circuit of the present invention configured as described above enables power supply with less noise. That is, even in a high-speed logic circuit in which the analog circuit section and the digital circuit section are mixedly mounted on the printed wiring board 7, it is possible to realize a power supply circuit that does not adversely affect the analog circuit section due to noise.

(3) An electrically equivalent circuit of the power supply circuit for the high speed logic circuit of the present invention is shown in FIG. 1- (B). That is, the low-pass filter 5 is L which is an inductive component.
It is composed of a component 11 and a C component 12, which is a capacitive component.
The L component 11 is provided in the wiring path forming the through hole portion 8 that electrically connects the VCC layer A1 and the VCC layer B2. Further, the L component 9 of the capacitor that provides the C component 12 also exists with a small value, and the bypass capacitor 6 also has the L component 9 of a similar small value. Then, considering them, C should be set so that the desired filter characteristics are obtained.
The component 12 may be selected and determined.

[0017]

Since the present invention is configured as described above, it has the following effects. (1) With the structure of the power supply circuit of the present invention, noise does not occur even if the power supply current fluctuation caused by using a large number of CMOS ICs in the high-speed logic circuit becomes large. Also, there is no longer a problem that the analog circuit portion is adversely affected by noise while the digital portion is mixedly mounted on the printed wiring board and a problem occurs.

(2) Therefore, according to the prior art, in a high-speed logic circuit on a printed wiring board on which an analog circuit section and a digital circuit section are mixedly mounted, the analog circuit section and the digital circuit section are supported in order to eliminate the adverse effect of noise. The power supply for the power supply is separated, and the mutual signal connection is separated by using a photocoupler, a pulse transformer, a differential driver / receiver or the like. According to the present invention, the mutual signal connection is multi-channel. Even in the case of over, the various coupling elements required for the number of signals are not needed, and the cost for that and the area for circuit formation required for separation can be significantly saved. .

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a structure of a high-speed logic circuit and a power supply circuit formed on a printed wiring board of the present invention.
FIG. 1- (A) is a conceptual diagram showing the structure of the present invention. FIG. 1- (B) shows an electrical equivalent circuit of the present invention. FIG.
-(C) is a conceptual diagram for explaining the principle of the present invention.

FIG. 2 is a conceptual diagram showing a configuration of a high speed logic circuit and a power supply circuit on a printed wiring board according to a conventional technique.
FIG. 2- (A) is a conceptual diagram showing a configuration of a conventional technique.
FIG. 2- (B) shows an electrically equivalent circuit of the related art.
FIG. 2- (C) shows a situation of generation of a standing wave by the configuration of the related art. FIG. 2D shows how the power supply current changes when the CMOS IC level is inverted.

[Explanation of symbols]

 1 VCC layer A 2 VCC layer B 3 CMOS IC 4 GND layer 5 Low pass filter 6 Bypass capacitor 7 Printed wiring board 8 Through hole 9 L component inside the capacitor 11 L component 12 C component 13 VCC layer 14 Power supply current i 15 Reflection 16 constant Standing wave

Claims (1)

[Claims] 1. On a printed wiring board (7) on which an analog circuit portion and a digital circuit portion are mounted together, a VCC layer (13), which is a power supply layer, is provided as a VCC layer A (1) and a VCC layer B (2). Provided as a system, the VCC layer A (1) is provided with a geometrical dimension sufficiently smaller than the wavelength of the power supply current change of the CMOS IC (3), and between the VCC layer A (1) and the GND layer (4). A bypass capacitor (6) is provided, and a low-pass filter (5) is provided in the path between the VCC layer A (1), the VCC layer B (2), and the GND layer (4). And a power supply circuit for high-speed logic circuit and analog circuit mixed mounting.